US3906256A - Drive pulse generator for use in electronic analog display clock apparatus - Google Patents

Drive pulse generator for use in electronic analog display clock apparatus Download PDF

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Publication number
US3906256A
US3906256A US523724A US52372474A US3906256A US 3906256 A US3906256 A US 3906256A US 523724 A US523724 A US 523724A US 52372474 A US52372474 A US 52372474A US 3906256 A US3906256 A US 3906256A
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United States
Prior art keywords
output
binary counter
delay circuit
drive
logic gate
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Expired - Lifetime
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US523724A
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English (en)
Inventor
Yasoji Suzuki
Hisaharu Ogawa
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Toshiba Corp
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Tokyo Shibaura Electric Co Ltd
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G3/00—Producing timing pulses
    • G04G3/02—Circuits for deriving low frequency timing pulses from pulses of higher frequency
    • G—PHYSICS
    • G04—HOROLOGY
    • G04C—ELECTROMECHANICAL CLOCKS OR WATCHES
    • G04C3/00—Electromechanical clocks or watches independent of other time-pieces and in which the movement is maintained by electric means
    • G04C3/14—Electromechanical clocks or watches independent of other time-pieces and in which the movement is maintained by electric means incorporating a stepping motor
    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G5/00—Setting, i.e. correcting or changing, the time-indication
    • G04G5/02—Setting, i.e. correcting or changing, the time-indication by temporarily changing the number of pulses per unit time, e.g. quick-feed method

Definitions

  • ABSTRACT Disclosed is a circuit for generating in a pulse motor drive coil an initial pulse motor drive pulse in a unit length of time during which a second hand is driven by one step, after resetting for time correction has been released.
  • the output of a divider chain for frequencydividing a standard frequency signal from a quartz oscillator into a signal having a period equal to the unit length of time is delayed by a delay circuit, and by a logic gate responsive to the output of the delay circuit and the output of the divider chain there is produced an output pulse signal having a period equal to the unit length of time and a narrower width.
  • the output of the logic gate is supplied to a binary counter.
  • An output circuitry responsive to the output of the binary counter and the output of the logic gate generates drive pulses in the drive coil.
  • the reset signal is applied to the delay circuit and at least a frequency divider stage producing the signal the period of which equals the unit length of time.
  • This invention relates to a drive pulse generator for use in an electronic analog display clock apparatus, and more particularly to a drive pulse generator suited for time correction.
  • the analog display clock apparatus having a quartz oscillator oscillating at a precise frequency, it is required for the purpose of step-advancing a second hand for every unit length of time, e.g., at an interval of 1 second that drive pulse currents are permitted to flow in a drive coil of a pulse motor in opposite directions at an interval of unit length of time.
  • a standard frequency signal of the quartz oscillator is frequency-divided in turn by a frequency divider chain comprised of binary counters cascade-connected in a number of n to produce an output signal having a predetermined period.
  • the output signal of the divider chain is delayed by a delay circuit responsive to the output of the mth binary counter (m n) of the divider chain by a predetermined period (equal to half the output period of the mth stage binary counter).
  • the output of the nth stage counter; the complementary output of the delay circuit, and the complementary output of the nth stage counter; the output of the delay circuit are supplied to a pair of two-input logic gates, respectively. Further, the outputs of the pair of logic gates are supplied to'a pair of inverters, respectively. Between the outputs of the pair of inverters is connected a drive coil. Where the output of the mth stage counter has a period of seconds, drive pulse currents flow in the drive coil at an interval of 1 second in mutually opposite directions.
  • the above-mentioned drive pulse generator is disclosed in Japanese magazine Electronics,,.Vol. 18, No. 11, 1349 (1973).
  • the negative pulse after release of resetting effected after generation of a negative pulse does not act to drive the'pulse motor,whereas the negative pulse after release of resetting effected after generation of a'positive p ulse acts to drive the pulse motor.
  • the conventional clock apparatus is so arranged as not to be operated through a lock mechanism by a pulse generated immediately after release of resetting, and therefore becomes complicated in construction and resultantly expensive.
  • the object of the invention is to provide a drive pulse generator capable of generating a drive pulse in a unit length of time after release of resetting.
  • This invention is characterized in that between the n-lth stage divider and the nth stage divider of a divider chain for frequency-dividing a standard frequency signal from a crystal oscillator there are disposed a delay circuit for delaying the output of the n-l th stage divider by a predetermined length of time and a logic gate responsive to the output of the delay circuit and the output of the n-l th stage divider to produce an output pulse having a predetermined period and width, the nth stage divider being triggered by the output of the logic gate; and a reset signal being supplied to the delay circuit and at least the n1 th stage divider.
  • FIG. 1 is a schematic block diagram of a general electronic analog display clock apparatus
  • FIG. 2 is a block diagram of a drive pulse generator according to an embodiment of the invention.
  • FIG. 3 is a detailed logic circuit diagram of part of the block diagram of FIG. 2;
  • FIG. 4 shows output waveforms of respective sections of FIG. 2
  • FIGS. 5A and 5B are waveforms for explaining the reset operation
  • FIG. 6 illustrates a connection diagram of the drive coil and inverters
  • FIG. 7 is a modification of FIG. 2;
  • FIG. 8 is another modification of FIG. 2.
  • a conventional electronic analog display clock apparatus is comprised of a crystal oscillator 11, frequency divider chain 12, output circuitry 13 including output logic circuits and driving circuit, pulse motor means 14 and analog display section 15 having a second hand, minute hand and hour hand.
  • the oscillator 1 1, divider chain 12 and output circuitry 13 constitute a drive pulse generator 16 powered from a battery 17 to generate drive pulses for driving a pulse motor 14.
  • the drive pulse generator 16 is comprised of a C-MOS integrated circuit operable with a low voltage.
  • FIG. 2 is a block diagram of a drive according to the invention, the same parts and sections as those of FIG. 1 being denoted by the same reference numerals.
  • the crystal oscillator 11 oscillates at a standard frequency of, for example, 32.768 kHz.
  • the standard frequency signal from the oscillator 1 1 is frequency-divided in turn by the n-l cascade-connected +2 dividers or binary counters 12-1, l2-m, l2-n-1 of the divider chain 12.
  • the number of binary counter stages of the divider chain 12 is determined by a length pulse generator .of time'required for the second hand of the analog dissignal having a period equal to the unit length of time.
  • the stage number of the divider chain is chosen to be (n 1 l5).
  • such signals Qn-l and Orr-1 having a period of 1 second as shown in FIG. 4, i.e., a frequency of 1 Hz areobtained from the n-l th stage binary counter 12-n-1 of the divider chain 12.
  • Theoutput Qn-1 of the n 1 th binary counter 12- n-l is coupled to the input terminal of a delay circuit 18 which may be a'half bit shift register.
  • This delay cir cuit performs the delay operation in response to the output Q m and itscomplement 6m of the mth stage counter l2-m (m nl) generating higher frequency signals than then-1 th stage counter. l2-n.l, and the length'of time delay of the delay circuit is equal to half the length of period of the output of the mth stage counter l2-m. .-'The-delayed output M as shown in FIG. 4 appearing at the ,output terminal 0 of the delay circuit and the complement On I of n-l th stage binary counter output 'QnQ-I are applied to a NOR gate 19.
  • the output X 'show'n'in FIG. 4 which has a pulse width equal to half theperiod of the output of the mthbinary counter l2-m, i.e., a pulse width equal to the time delay length given by the delay circuit, and which has a period of 1 second.
  • the output Xof the NOR gate 19 and the complement Y thereof-obtained from an inverter are applied to theinputs Inand In, respectively, .of a binary counter ,1 2 -r,1 to produce outputs Qnand On shown in FIG.
  • first NAND'gate 21 To the first NAND'gate 21 are coupled the outputX of the NOR gate 19 and the output Qn of the binary counter lZ-n. To the second NAND gate22 are coupled the outputs X and On. The outputs of the first and second NAND gates 21 and 22 are respectively coupled to the inputs of first and second inverters 23 and 24, between the outputs of which is connected a drive'coil for driving a pulse motor.
  • the delay circuit 18 and the binary counters of the divider chain 12 are supplied, when time correction is desired, with a resetsignal from reset signal supply means27 through a reset line 26. Since a reset button 28 is opened during the operation of the drive pulse generator, the reset line 26 is connected to ground potential through a resistor 29. When the reset button 28 is closed at the time of resetting, a positive reset signal from a battery 30 is applied to the delay circuit and binary counters. In response to the reset signal, for example, the binarycounter- 12-n-1 compulsively produces the output Qn-l of zero volt irrespective of output condition, prior to resetting and the delay circuit 18 holds the output prior to resetting.
  • the stage position of counters for supplying operating signals to the delay circuit 18 is determinedby the length of response time of the pulse motor, and thus the stage position at which relatively low or high frequency signals are produced is not desirable.
  • FIG. 3 illustrates an example of a logical diagram of the binary counters 12-n-1 and 12-n and delay circuit 18.0f FIG. 2.
  • the binary counter 12-rr.1 beingsupplied with reset signals comprised of clocked inverters and NOR gates is thesame as a static binary counter with a reset terminals: shown in FIGS. 6A and 6B in the copending US. patent application Ser. No. 333,145 filed Feb. 16', 1973.
  • the binary counter l2-n is the same as the static binary counter shown in FIGS. 4A and 4B in the copending application.
  • ones being supplied with reset signals may have the same construction as the binary counter l2- n1 and ones being supplied with no reset signals may have the same construction as the binary counter 12-n.
  • those binary counters of the divider chain 12 which are operating at a relatively high frequency are not always required tobe of static type but may be of dynamic type having no clocked inverter connected in parallel with a NOR gate or having no clocked inverter connected inparallel with an inverter.
  • the delay circuitv 18 is a 5 half-bit static shift register comprised of clocked invert: ers 31 and 3'2,' NAND"gate 33 and ihverter 34. i FIG.
  • FIG. 6 illustrates a connection betweenthe driv'coil 25 andthe firstand s'econd'inver ters 23' and'24 of FIG. 2.
  • the first inve'rter23 is coiiiprised of a'F t:haiin'el MOS transistor 23? and N-chann'eI'MOStransistor 23N whose drain-source paths Y are series-connected across a power source.
  • the second inverter 24 is comprised :of a P-channelandN-charinel MOS transistors24P and 24N whose drain-source paths are series-connectedqacross a powersourcen-Ihedrive coil 25 is connected between the junctionbetween, the transistors 23Pand-23N of the first inverter p23and the junction between the transistors 24? and 24N of the inverter 24.
  • the output of the first NAND gate 21 is zero volt and the output of the second NAND gate 22 is positive
  • the P-channel transistor 23? and N- channel transistor 24N are rendered both conductive to cause drive current to be flowed through the drive coil 25 in a direction indicated by an arrow of solid line.
  • the transistors 24P and 23N are rendered both conductive to cause drive current to be flowed through the drive coil 25 in a direction indicated by an arrow of dotted line.
  • the N-channel transistors 23N and 24N are rendered both conductive. Accordingly, both ends of the drive coil 25 are at zero volt so that no drive current flows through the drive coil 25.
  • the P-channel transistors 231 and 24P are rendered both conductive to cause source voltage to be applied to both ends of the drive coil 25. Also in this case, no current is passed through the drive coil 25.
  • FIGS. 5A and 5B illustrate waveforms for explaining the resetting operation
  • FIG. 5A illustrating waveforms where resetting is effected after the output 0,, has been produced from the first inverter 23
  • FIG. 5B illustrating waveforms where resetting is effected after the output 0,; has been produced from the second inverter 24. Where resetting is effected after the output 0,, has
  • the output Qn-1 of the binary counter l2-n-l is compulsively reduced to zero volt by the action of the NOR gate upon receipt of a positive reset signal, while the output M of the delay circuit 18 is held at the positive level prior to resetting by the action of the inverter 34 and NAND gate 33. Since the level of output M of the delay circuit 18 does not vary during resetting, the level of output X of the NOR gate 19 does not vary but is held at a level of zero volt. Accordingly, theoutputs On and 6h of thebinary counter 12-n are also held at the levels prior to resetting. For this reason, the first and second inverters 23 and 24 do not produce the outputs O and during resetting.
  • the second inverter 24 when resetting is released, the level of output Qn-l of the binary counter 12-n-l, accordingly, the level of the output M of the delay circuit 18 varies to cause the NOR gate 19 to produce the output X in the unit length of time after release of resetting. For this reason, the second inverter 24'produces the output 0 Where resetting is effected after the first inverter 23 has produced the output 0,, the second inverter 24 produces the output 0,, in the unit length of time after release of resetting. Where resetting is effected after the second inverter 24 has pro-.
  • the first inverter 23 produces the Accord ng outputQ ir the unit length of time after releaseof resetting, as illustrated in no; saline is due to thefact that the binary counter 12- n is supplied with no reset sign to bekeptlat the output levelprior to resetting. the construction of -FIG. 2, therefore, it neverhappens that the sarne kindof drive,.pulses are generatje dboth priorto resetting and..after release of resetting. Therefore, any locking, mechanism becomes unnesessary; to simplify the clock apparatus construction.
  • the time error- is producedin accordancewith the stage position of a binary counter. being supplied with .the reset .signal.
  • the reset signal is supplied to the ninth to 15th stage binary counters, a time error within the output period, i.e., 1/128 sec., of the eighth stage binary counter is produced.
  • FIG. 7 is a modification of FIG. 2 wherein reset signal is applied to the delay circuit 18 and binary counters through an AND gate 36; the other input terminal of the AND gate 36 is supplied with the output Y of the inverter 20.
  • This modification is so arranged that the resetting operation is not performed during the period in which the outputs X and Y illustrated in FIGS. 5A
  • FIG. 8 illustrates an embodiment so constructed that the reset signal is applied also to the binary counter
  • the output level of the binary counter l2-n is also reset by the reset signal
  • the output produced in the unit length of time after release of resetting is limited to 0 or 0,; only.
  • the NAND gate 33 of the delay circuit 18 of FIG. 3 may be replaced by a NOR gate 37 as illustrated in FIG. 8, and in this case the inverter 34 becomes unnecessary. Where the NAND gate 33 is replaced by the NOR gate 37, the NOR gate 19 is replaced by a NAND gate 38.
  • the drive pulse generator according to the invention is constituted by complementary MOS transistors, but can of course be constituted by the P- channel or N-channel MOS transistors only.
  • a drive pulse generator for use in an electronic analog display clock apparatus which is adapted to supply drive pulses to the drive coil of motor means for driving time indication hands, comprising:
  • a frequency divider chain having binary counters cascade-connected in a number of n-l and connected to receive the output of said signal source for frequency-dividing said standard frequency signal in turn;
  • a delay circuit connected to receive the output of the n-l th stage binary counter of said frequency divider chain for delaying the output of said n-l th stage binary counter in response to the output of one binary counter in said divider chain which pro- Iduces a higher frequency signal than the output frequency of said nl th stage binary counter;
  • logic gate means connected to receive the output of said delay circuit and an output of said n-l th stage binarypounter for producing an output pulse signal having a predetermined period and pulse width;
  • nth stage a binary counter (nth stage)-connected to receive .
  • a drive pulse generator according to claim 1 wherein said logic circuit means includes first and second two-input logic gates, one side-inputs of said first and second two-input logic gates being coupled to an output of said logic gate means and the other sideinputs to the complementary outputs of said nth binary counter, and first and second inverters respectively connected to receive the outputs of said first and second two-input logic gates, said drive coil being connected between the outputs of said first and second inverters.
  • a drive pulse generator according to claim 1 wherein said resetting means includes means for stopping, when the output of said logic gate means is at a predetermined level, supply of the reset signal in response to said output of said logic gate means.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Electromechanical Clocks (AREA)
  • Electrophonic Musical Instruments (AREA)
  • Control Of Stepping Motors (AREA)
US523724A 1974-03-09 1974-11-14 Drive pulse generator for use in electronic analog display clock apparatus Expired - Lifetime US3906256A (en)

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Application Number Priority Date Filing Date Title
JP49027546A JPS581394B2 (ja) 1974-03-09 1974-03-09 キカイヒヨウジシキトケイソウチ ノ ケイスウカイロ

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US (1) US3906256A (enrdf_load_stackoverflow)
JP (1) JPS581394B2 (enrdf_load_stackoverflow)
CH (1) CH613086B (enrdf_load_stackoverflow)
FR (1) FR2263546B1 (enrdf_load_stackoverflow)
GB (1) GB1480754A (enrdf_load_stackoverflow)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4110968A (en) * 1975-11-18 1978-09-05 Jean Claude Berney Control for a step motor for the measurement of time
US4150536A (en) * 1976-01-28 1979-04-24 Citizen Watch Company Limited Electronic timepiece
US4464774A (en) * 1982-03-15 1984-08-07 Sperry Corporation High speed counter circuit
US6731149B2 (en) * 1999-02-17 2004-05-04 Kabushiki Kaisha Toshiba Synchronizing circuit for generating a signal synchronizing with a clock signal

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS597951B2 (ja) * 1978-02-13 1984-02-21 セイコーエプソン株式会社 時計
CH624538B (fr) * 1979-04-04 Ebauches Sa Piece d'horlogerie electronique.

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3765163A (en) * 1972-03-17 1973-10-16 Uranus Electronics Electronic timepiece
US3852951A (en) * 1972-07-12 1974-12-10 Suisse Horlogerie Electronic correction

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1343330A (en) * 1970-07-27 1974-01-10 Suwa Seikosha Kk Electric timepieces
JPS4895868A (enrdf_load_stackoverflow) * 1972-03-21 1973-12-08
JPS5647515B2 (enrdf_load_stackoverflow) * 1972-03-27 1981-11-10
JPS5442276B2 (enrdf_load_stackoverflow) * 1973-04-07 1979-12-13

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3765163A (en) * 1972-03-17 1973-10-16 Uranus Electronics Electronic timepiece
US3852951A (en) * 1972-07-12 1974-12-10 Suisse Horlogerie Electronic correction

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4110968A (en) * 1975-11-18 1978-09-05 Jean Claude Berney Control for a step motor for the measurement of time
US4150536A (en) * 1976-01-28 1979-04-24 Citizen Watch Company Limited Electronic timepiece
US4464774A (en) * 1982-03-15 1984-08-07 Sperry Corporation High speed counter circuit
US6731149B2 (en) * 1999-02-17 2004-05-04 Kabushiki Kaisha Toshiba Synchronizing circuit for generating a signal synchronizing with a clock signal

Also Published As

Publication number Publication date
FR2263546B1 (enrdf_load_stackoverflow) 1977-11-04
JPS581394B2 (ja) 1983-01-11
CH613086B (de)
CH613086GA3 (enrdf_load_stackoverflow) 1979-09-14
JPS50136077A (enrdf_load_stackoverflow) 1975-10-28
FR2263546A1 (enrdf_load_stackoverflow) 1975-10-03
GB1480754A (en) 1977-07-27

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