US3895486A - Timekeeper - Google Patents

Timekeeper Download PDF

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US3895486A
US3895486A US236774A US23677472A US3895486A US 3895486 A US3895486 A US 3895486A US 236774 A US236774 A US 236774A US 23677472 A US23677472 A US 23677472A US 3895486 A US3895486 A US 3895486A
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memory
output
frequency
coupled
input
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Walter Hammer
Eric Andre Vittoz
Jean Hermann
Hubert Choffat
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Centre Electronique Horloger SA
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Centre Electronique Horloger SA
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
    • H03K23/662—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by adding or suppressing pulses
    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G3/00—Producing timing pulses
    • G04G3/02—Circuits for deriving low frequency timing pulses from pulses of higher frequency
    • G04G3/022—Circuits for deriving low frequency timing pulses from pulses of higher frequency the desired number of pulses per unit of time being obtained by adding to or substracting from a pulse train one or more pulses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/68—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using pulse rate multipliers or dividers pulse rate multipliers or dividers per se

Definitions

  • a timekeeper comprises a quartz crystal resonator [51] ll'll. Cl. G04b 27/00 having a Stable frequency but with a relatively large [58] Fleld 0f Search 307/225; 328/48, I20; tolerance and a frequency divider with an adjustable 58/23 23 23 divison ratio.
  • Said divider has auxiliary electrical in- 23 50 152 57; 3 l0/8'l puts the logical state of which determines the division ratio, and a memory, for example an electrically alter- [56] References cued able electronic memory, supplies stored data to deter- UNITED STATE PATENT mine the logical state of the auxiliary inputs and hence 3,166,888 1/1965 Kartaschoff 58/23 R the division ratio.
  • the memory may comprise volatile 3,540,207 11/1970 and permanent parts, the permanent part intermit- 3,581,066 5/1971 tently regenerating data stored in the volatile part.
  • the invention relates to timekeepers of the type comprising a resonator and a frequency divider with an adjustable division ratio.
  • the required output frequency of pulses from the frequency divider is generally obtained by providing both that the time base, usually formed by a quartz-crystal-controlled pulse generator or a diapason (tuning fork), has an exactly determined frequency, and that the frequency divider has an exactly determined division ratio.
  • Both the suspension and the casing may, during the final stages of manufacture, modify the frequency of the quartz resonator by several units X 10' This frequency difference can be partly compensated for by providing an adjustment after closing the casing, and by arranging two windows through which a metallic layer can be deposited on the ends of the quartz crystal bar before closing the windows and evacuating the casing; however, this is a complex and costly operation.
  • the final adjustment is usually carried out by means of an adjusting capacitor in series with the quartz crystal in the resonator circuit.
  • adjusting capacitor is also a fairly expensive component and takes up valuable space.
  • Dividers with adjustable division ratios operating according to otherprinciples are also known and used, in particular in frequency synthetisers.
  • most types have characteristics which render them inapplicable to use in wrist watches, either because of difficulties that would be involved in providing them in integrated form, or for diverse other reasons. For example,
  • the general aim of the invention is to eliminate these drawbacks and to enable the introduction of new possibilities of adjustment of a timekeeper which could not be carried out by the previously known means.
  • a specific aim is to propose a satisfactory solution to the problem of obtaining a precisely adjustable timekeeper comprising a quartz resonator whose frequency is stable but may be comprised within relatively large tolerances.
  • a timekeeper comprises a resonator, a frequency divider with an adjustable division ratio, said divider having auxiliary electrical inputs the logical state of which determines the division ratio, and a memory connected to said auxiliary inputs, said memory storing coded data which determine the logical state of said auxiliary inputs and therefore the division ratio of the divider.
  • the other components of the timekeeper can be digital components whose individual variations or tolerances can be fairly great without influencing the accuracy of the timekeeper.
  • the frequency adjusting operation can take place by means of integratable circuits, which contributes to the reliability of the timekeeper, enables miniaturization, and makes mass production with the consequent low manufacturing cost possible.
  • the increase in complexity of the circuitry is not very great and does not involve an appreciable increase in the consumption if complementary MOS transistors (with substantially dynamic consumption) are employed.
  • the increase in the complexity of the circuitry does not unfavourably influence the overall price, because of the economy made in other components such as the miniature switches and in the number of connections.
  • Another aim of the invention is to facilitate ajustment of the division ratio by electrical control.
  • the invention makes possible a rapid frequency setting by the sequential introduction of data concerning the division ratio. Introduction of this data can take place by means of one connections to a single input terminal of the circuit.
  • memory is an electrically alterable memory.
  • an electrically alterable memory enables, at any time, a change of the division ratio solely by means of electrical pulses, without having to modify connections of the circuit.
  • FIG. 1 shows a clock comprising a time base and a frequency divider forming a conventional timekeeper
  • FIG. 2 is a block diagram of a first embodiment of timekeeper according to the invention.
  • FIG. 3 shows one type of the memory of the timekeeper of FIG. 2, in the form of a shift register
  • FIG. 4 shows another form of memory
  • FIGS. 5 and 6 show two variants of part of a memory respectively including a MNOS component and a FAMOS component;
  • FIG. 7 shows in detail the logical circuit of unit 13 of FIG. 2;
  • FIG. 8 is a diagram illustrating the operation of the logical circuit of FIG. 7;
  • FIG. 9 shows in detail the logical circuit of unit of FIG. 2;
  • FIG. 10 is a diagram illustrating the operation of the logical circuit of FIG. 9;
  • FIG. 11 shows the unit 9 of FIG. 2, namely a logical gate
  • FIG. 12 is a diagram illustrating the operation of the gate of FIG. 11;
  • FIG. 13 shows in detail the logical circuit of unit 7 of FIG. 2;
  • FIG. 14 is a diagram illustrating the operation of the logical circuit of FIG. 13;
  • IG. 15 is a block diagram of a second type of adjustable divider formed by a single division stage carrying out division either by one or by two;
  • FIG. 16 is an explanatory graph showing operation of the stage of FIG. 15;
  • FIG. 17 shows a third type of adjustable frequency divider having a dividing chain formed of four stages and a comparator adjusting the dividing chain according to the principle described with reference to FIGS. 15 and 16;
  • FIG. 18 is an explanator graph showing operation of the divider of FIG. 17;
  • FIG. 19 shows a fourth example of adjustable divider comprising a dividing chain and a comparator adjusting the dividing chain
  • FIG. 20 is an explanatory diagram showing the operation of the divider of FIG. 19;
  • FIG. 21 shows an example of volatile electronic memory intended to be connected to the comparator of a timekeeper including the divider shown in FIG. 17
  • FIG. 22 shows a device for supplying the memory of FIG. 21
  • FIG. 23 shows another type of memory for a timekeeper including the divider of FIG. 17 or 19, this memory being in the form of a counter;
  • FIG. 24 shows a device for having access to the memory of FIG. 23
  • FIG. 25 shows a device for controlling the zeroing and inscription in a memory of the type shown in FIG. 23;
  • FIG. 26 is a diagram explaining the operation of the device of FIG. 25;
  • FIG. 27 shows another example of a memory
  • FIG. 28 shows a variant of the memory of FIG. 27.
  • FIG. 1 shows a known type of clock comprising a quartz-crystal-controlled pulse generator 1, a series of binary dividers (flip-flops) 2, and a step-by-step motor 3 driving a motion work (or dial-train) 4.
  • the dividing chain formed by the dividers 2 has a given division ratio, and to ensure the accuracy of the clock, the frequency of the generator 1 must be exactly adjustedlln such a clock, the frequency of the generator could be 2 8192 Hz and the dividing chain could comprise fourteen binary dividers, so that the output frequency of the chain is 0.5 Hz, suitable for driving the step-bystep motor 3.
  • FIG. 2 is a block diagram of a first embodiment of timekeeper according to the invention.
  • the dividing chain comprises fourteen binary dividers and the quartz crystal, whose nominal frequency must be 8192 Hz, is supposed to be adjusted to a precision of 10", the precision of the timekeeper being adjustable to 3.8
  • the timekeeper shown in FIG. 2 comprises a quartzcrystal-controlled pulse generator 5, a first binary divider 6, a sequential logical circuit 7 one input A of which receives output pulses from the divider 6 and whose output B supplies a chain of 13 further binary dividers 8.
  • the logical circuit 7 also comprises an input C supplied by a thermal compensation device or alternatively by a time setting device (not shown), and an input D supplied by the output of a unit 9.
  • the effect of the logical circuit 7 is to block the supply of pulses from the divider 6 to the first of the dividers 8 when the input C has the logical value 1 and to block the supply of only a single pulse from the divider 6 to the first of the dividers 8 each time that the input D takes the logical value 1, whatever be the duration during which this input D holds the logical value 1.
  • the sequential circuit 7 and its operation will be described in full detail further on with reference to FIGS. 13 and 14.
  • the functional unit 9 has two inputs E and F and one output connected to the input D of the circuit 7. This unit 9 is formed by an AN D logical gate carrying out the operation D EF, and will be described with reference to FIGS. 11 and 12.
  • the output of the final divider 8 of the chain supplies: the input of a step-by-step motor 10 controlling a motion-work 11; the first divider of a chain of five binary dividers l2; and the input E of the unit 9.
  • the inputs L, M, N, O, P of the unit 13 are supplied by the corresponding outputs of a memory 14 storing data for the adjustment of the division ratio of the chain of dividers 8.
  • This memory is an electronic memory, examples of which will be described with reference to FIGS. 3, 4, 5 and 6 and FIGS. 21 to 28.
  • the two outputs Q and R of the unit 13 supply two 9 corresponding inputs of a unit 15 whose output supplies the input F of unit 9.
  • the purpose of this unit 15 is to suppress the redundant logical states 1 of the variable Q. It is formed by a sequential logical circuit which will be structurally and operatively described with reference to FIGS. 9 and 10.
  • FIG. 3 is a partial view of a first'embodiment of the memory 14 of FIG. 2.
  • This memory 14 is formed by'a shift register comprising five D-type flip-flops, 16, 17, 18, 19 and 20 whose inputs are indicated by U, the outputs by V, and the controls by W.
  • Each of these groups of seriesconnected elements is connected on the one hand to a line held at a potential 0 and onthe other hand to a line held at a potential 1.
  • a line held at a potential 0 To choose the out;uts L, M, N, O, P of the memory of FIG. 4, it suffices to rupture one of each pair of fusible elements 21 and 22.
  • a large current can be passed between an appropriate set terminal and the line 0; after rupture of the element 21, the output L will thus always remain at a potential 1.
  • the memory can be used to apply the logical values obtained to the auxiliary inputs of the unit 13 (FIG. 2).
  • FIGS. 5 and 6 each represent a single cell comprising an output L of two types of permanent electrically alterable electronic memory.
  • This type of memory resolves the problem of the loss of data when changing the supply battery or cell.
  • FIG. 5 shows a known type of MNOS transistor, i.e. a MOS transistor with a supplementary layer of nitride which enables variation of the transistor threshold. The application of a high voltage to the inscription or set input enables this threshold value of the MNOS transistor to be changed. The output L will take the value 1 if the threshold is low and 0 if the threshold is high.
  • FIG. 6 shows a FAMOS transistor also of known type, this being a MOS transistor with a floating grid.
  • the grid may be charged by the application of a high voltage to its drain by the inscription set terminal.
  • the FAMOS transistor will thus be conducting and the output L will take the value 1.
  • the grid To reset L to 0, the grid must be discharged, which can be achieved by ultra-violet radiation or X-rays.
  • FIG. 7 is a detailed block of the logical circuit shown by unit 13 of FIG. 2.
  • This circuit comprises five AND gates 23 each with two inputs connected to respective ones of the outputs G, H, I, J, K of the dividers l2 and to respective ones of the outputs L, M, N, 0, P of the memory 14.
  • the fiveoutputs of the AND gates 23 are connected to five corresponding inputs of an OR gate 24 having an output Q.
  • the second output R of the circuit is connected directly to the output K. Operation of this circuit is schematically illustrated in the graph of FIG. 8.
  • the graphs G and K represent the output pulses of successive dividers 12, the frequency being in each case half the frequency of the previous divider. If the quartz crystal had the nominal frequency indicated above, 2 8192, the frequency of signal G would be 2 2 2 0.25- I-Iz, the corresponding half-period of 2 seconds being indicated on graph G.
  • the duration of the first pulse of signal Q will be equal to n times the duration of one pulse of signal G, namely 2n seconds. If the outputs of the block 14 of FIG. 2 are for example n LMNOP 01010 2 2 10,
  • the duration of the first pulse of the signal Q is thus 10 times the duration of a pulse G, namely 20 seconds.
  • pulses of duration 2n see. are then repeated every 32 seconds.
  • FIG. 9 shows a sequential logical circuit forming the unit 15 of FIG. 2, the purpose of which is to suppress unwanted logical states 1 of the signal Q.
  • the signal 0 is applied to one of the inputs of an AND gate 25 the other input of which is supplied by the output of an OR gate 26.
  • One of the inputs of the OR gate 26 is supplied by the output signal F of the AND gate 25 and the other by the output of an AND gate 27.
  • One of the inputs of the AND gate 27 is supplied by the output of a reverser (throw over switch) 28 whose input is supplied by the output of an AND gate 29 also supplying one of the inputs of an OR gate 30 whose other input is supplied by the output signal P.
  • the other input of the AND gate 27 as well as one of the inputs of the AND gate 29 are supplied by the signal R, the other input of the AND gate 29 being supplied by the output of the OR gate 30.
  • this logical circuit can best be seen by referring to FIG. 10, showing the output signal F deduced from the input signal Q by suppression of pulses other than the above-referred-to pulses of duration proportional to n LMNOP produced while R has the value 1, pulses F thus having a periodicity of 64 seconds.
  • FIG. 11 shows, in conventional logical symbolism, the unit 9 of FIG. 2 which is formed by a single AND gate 48 whose inputs are respectively supplied by the signals E and F. Since the signal E is formed by pulses with a period of 2 sec. and the signal F is formed by pulses of logical value 1 with a duration of Zn sec.
  • the output signal D of the gate 48 will be formed by trains of n pulses emitted every 64 seconds, this being clearly illustrated in FIG.
  • FIG. 13 shows a sequential logical circuit forming the unit 7 of Flg. 2.
  • the purpose of this circuit is to prevent the supply of the pulses from the binary divider 6 to the first division stage 8 whilst the input signal C has the logical value 1, and to only prevent the supply of a single pulse when the signal D takes the logical value 1, this independently of the duration during which the signal D holds this value, this being clearly shown in FIG. 14.
  • the sequential logical circuit of FIG. 13 comprises an AND gate 31 one input of which receives the signal A via an inverter 49 and whose output is connected to the input of an OR gate 32.
  • the output of this latter is applied, on the one hand, to the other input of the gate 31 and, on the other hand, to one of the three inputs of an OR gate 33 whose output supplies the signal B.
  • the input signal D is applied to one of the inputs of an AND gate 34 and to one of the three inputs of another AND gate 35.
  • the signal A moreover supplies another of the inputs of both the AND gate 35 and the OR gate 33.
  • the circuit also comprises an OR gate 36 supplying, on the one hand, the second input of the AND gate 34 and, on the other hand, the third input of the AND gate 35 via a reverser 37.
  • the two inputs of the OR gate 36 are respectively supplied by the outputs of AND gates 31 and 34, and the second input of the OR gate 32 is supplied by the output of AND gate 35.
  • the input signal C is applied to the third input of the OR gate 33.
  • the signal C may come from a thermal compensation circuit, or alternatively a time-setting device.
  • the step-by-step motor operates at 0.5 Hz, it is not possible to block it for only 1 second. If the setting of the seconds hand of the clock took place by mechanically acting on the motor, it could only have a precision of about i 1 second. Setting by blocking the division remedies this drawback.
  • the above described units may be grouped so as to form more complex units, which can in certain cases lead to an overall simplification.
  • Each blockage must lower the frequency deviation by 3.8 X 10, since this is the precision that it is desired to reach, as indicated above.
  • t it may be necessary to have a maximum of 10 3.8 X 10 26 blocking operations to compensate for the maximum deviation in the frequency which has been fixed at, or assumed to be, 10".
  • the unit 14 must thus be able to memorize numbers n comprised between 0 and 26. In pure binary code, five binary variables are therefore required, as provided in the memories of FIGS. 3 to 6.
  • the signal D could serve to reduce the division ratio if the initial frequency of the quartz crystal were lower then 2 8192 Hz.
  • FIG. 15 A second embodiment of adjustable divider is shown in FIG. 15.
  • This divider 51 comprises a single binary dividing stage 52, whose input I is connected on the one hand to a resonator, not shown, for example a quartz crystal resonator, and on the other hand to a first input of an AND gate 53.
  • the output of the stage 52 is connected to a first input of a second AND gate 54.
  • the second inputs of the gates 53 and 54 are on the one hand connected together via an inverter 55 and, on the other hand, connected to an auxiliary input terminal L.
  • the outputs of the gates 53 and 54 are connected to respective inputs of an OR gate 56, whose output S provides the output signal of the divider.
  • FIG. 16 shows the output signal obtained at the output terminal S of the divider as a function of the signals applied to the inputs I and L. It can be seen that the divider divides by two when no signal of value I is applied to the input L. As soon as a signal I is applied to the input L, the gate 53 conducts and the input signal I passes directly to the output S. The division stage 52 is thus by-passed.
  • FIG. 17 shows a third type of adjustable frequency divider.
  • This divider 57 comprises four binary division stages 58, 59, 60 and 61 connected in series, the input I of the first stage 58 being connected to a resonator, not shown.
  • the outputs of the stages 58 to 61 are respectively connected to inputs L, M, N, and O of four two modulo gates 62, 63, 64 and 65 (also known as EXCLUSIVE OR gates), the output of the stage 61 also being connected to an output terminal S of the timekeeper.
  • the outputs of the gates 62 to 65 are connected to corresponding inputs of an AND gate 66 through inverters 62' to 65.
  • Each second input of the gates 62 to 65 is connected to an auxiliary input terminal L, M, N and respectively, these auxiliary inputs L, M, N, 0 being controlled by a memory arranged to supply a logical signal 0 or I to each of the inputs L, M, N and 0. Examples of this memory will be described in detail further on.
  • the output Z of the AND gate 66 is connected to four zeroing inputs of the stages 58 to 61.
  • the four binary stages 58 to 61 of this divider function to count the pulses I" supplied by the resonator, and are set to zero when the output Z of the gate 66 has the value I.
  • the zeroing variable Z has the value 1 when the state of the counter is identical to the state of the auxiliary inputs, that is when L L, M M, N, and O 0'. Consequently, the counter formed by the stages 58 to 61 counts by a number which corresponds to the state of the auxiliary inputs in binary code.
  • FIG. 18 shows the output signal Z (of AND gate 66) as a function of the inputs T", L, M, N, O, by way of example, for the auxiliary input values L l, M O, N 0, O l, (1001), which is the binary expression of the chosen number 9. It can be noted that two successive zeroing pulses l at the output Z of gate 66 are separated by an amount corresponding to nine periods of the input I.
  • FIG. 19 shows a fourth form of adjustable divider, comprising an inhibition circuit formed by an RS flipflop 67, an inverted AND gate 68 and an inverter 69, said circuit being connected between an input I connected to a resonator, not shown, and four binary division stages 70, 71, 72 and 73.
  • the outputs of these four stages 70 to 73 are connected to the inputs of four corresponding AND gates 74, 75, 76 and 77, the outputs of which lead to an OR gate 78 connected to the flipfiop 67.
  • the second inputs of the AND gates 74 to 77 'form the auxiliary inputs L, M, N, O which are connected to a memory, not shown.
  • FIG. 19 shows a fourth form of adjustable divider, comprising an inhibition circuit formed by an RS flipflop 67, an inverted AND gate 68 and an inverter 69, said circuit being connected between an input I connected to a resonator, not shown, and four binary division stages 70, 71, 72
  • the inhibition circuit formed by the flip-flop 67, the gate 68 and the inverter 69 is controlled by the auxiliary inputs L, M, N and O and by the division chain formed by the four stages 70 to 73 via the gates 74 to 78. It is thus possible to eliminate one input pulse 1 every 2, 4, 8 or 16 periods of the variable x (at the output of gate 68) according to whether either one of L, M, N or 0 have the value 1.
  • the overall division ratio will thus be respectively 24, 20, 18 or 17.
  • timekeepers which are adjustable by means of the auxiliary inputs are coupled with memories which can be of several types, a few examples of which will now be described.
  • a simple memory in the form of fusible elements such as that shown in FIG. 4, enables the desired logical values to be applied at the auxiliary inputs of an adjustable divider.
  • This type of memory however has the drawback of requiring a large number of inputs in the integrated division circuit. Also, subsequent modification of the memorized value is not possible.
  • a volatile electronic memory such as that shown in FIG. 21, is more suitable than a system of switches for example.
  • the type of volatile memory of FIG. 21, provided for example by means of two looped inverters 80 and 81 and an input 82 enabling the desired state to be produced, has the advantage of being entirely compatible with the circuit technology used for the adjustable divider, and the assembly can be integrated. The result is the elimination of a bulky and delicate electromechanical member as well as of numerous interconnections, therefore an increase in the reliability and a reduction of the unit cost by mass production.
  • FIG. 23 shows a counter formed by four binary stages 86, 87, 88, 89 having two input terminals, an input terminal IN receiving pulses to be counted and an input terminal R2 for zeroing the counter.
  • the outputs L, M, N, O are taken at the output of each of the stages 86 to 89.
  • a first input of each of the gates 90 and 91 is connected to a'single input terminal FI and the second inputs of these two gates 90 and 91 are connected, on the one hand, together via an inverter 92 and, on the other hand, to an auxiliary input A which is connected to the output of the divider shown in FIG. 19 and will thus receive a signal beating the seconds. It is thus possible, by acting on the input F, during even seconds, to zero the counter for example, and during a subsequent odd second, to place it in the desired state by acting on this same input.
  • an external frequency setting apparatus can be used.
  • This apparatus comprises a device schematically shown in FIG. 25 which must give a zeroing pulse when a button 93 is pressed (during an even second) and which must, one second later, automatically deliver the number of pulses corresponding to a number given by means 94 for preselecting the division ratio. Setting of the frequency by means of this automatic device greatly simplifies this delicate operation. For watches with a digital electronic display,
  • a device of the same type as that of FIG. 25 also enables setting the time.
  • the impulse 95 corresponds to setting to zero during even seconds and the pulses 96 comes from the output F of the device of FIG. 25 after 1 second.
  • Certain of the permanent electrically alterable memories which have just been dscribed require relatively large reading currents. To remedy this, it is possible to provide a permanently supplied volatile buffer memory 97 (FIG. 27) with a low consumption, regenerated at long intervals of time by the permanent memory 98 which is supplied only upon the regeneration of the volatile memories.
  • the permanent memory 98 is connected to the volatile memory 97 by AND gates 99, 100, 101 and 102.
  • the volatile memory is directly connected to a current source 103, whilst the permanent memory 98 is connected to this source 103 via a switch 104 controlled from a terminal F which will only be supplied to periodically regenerate the volatile memory by means of data stored in the permanent memory.
  • Another advantageous mixed type of memory consists of using a permanent memory 105 (FIG. 28)
  • timekeepers comprise four binarystages and the memories for adjusting the division ratio also store four variables. It is however clear that thenumber of binary stages of the timekeepers, and the number of variables of the memories, can be increased.
  • a timekeeper of the described type could have 19 division stages and a memory storing from four to variables.
  • electromechanical memories In the above-described timekeepers, two types of memories have been used: electromechanical memories, and electrically alterable electronic memories. Whilst the electrically alterable electronic memories are more complex and more costly than electromechanical memories, they nevertheless have numerous advantages.
  • the division operation takes place entirely within the integrated circuit and neither an intermediate dynamic output nor an intermediate input is necessary, which eliminates ohmic and capacitative losses of such outputs or inputs and avoids disturbance of the division operation.
  • the value of the division ratio may be comprised within very wide limits without the circuit requiring any precision analogue component, nor an undue increase in its complexity, bulk of manufacturing cost.
  • the number of inputs in a watch can be reduced to one by using a memory with sequential input, for example a counter, and a means for routing the data controlled by an internal variable made visible by the watch display (for example the second displayed).
  • a separate supply can be used for the memory. This eliminates the drawback of loss of data at the moment of changing the supply cell.
  • Such separate supply may be either by a miniature cell with a useful life of several years, or a capacitor or rechargeable buffer cell disconnected from the supply cell by electronic means for holding the voltage at the terminals of the memory during changing of the supply cell.
  • the memory can be. provided in various manners using different technological means, providing that its outputs are of logical values compatible with the adjustable divider.
  • electromechanical, volatile electronic, electrically alterable permanent electronic memories, and so on can be used.
  • Electrically alterable permanent memories may require a high power for reading thereof; this drawback can be avoided by transferring the data stored in such memories at long intervals of time to a volatile buffer memory which can be permanently read with a low power consumption.
  • a self-adjusting timekeeping apparatus comprising: a resonator producing a pulsed output signal having a non-adjusted frequency; a frequency divider coupled to said resonator for dividing the frequency of the output singal of said resonator, said frequency divider including auxiliary input means for adjusting the frequency division ratio thereof; memory means for store ing coded data in the form of a plurality of binary data bits; and frequency adjusting means coupling said memory means to said auxiliary input means for adjusting the frequency division ratio of said frequency divider as a function of the coded data stored in said memory means to thereby adjust the output frequency of said frequency divider, said frequency adjusting means including means for comparing the binary coded data bits stored in said memory means with a corresponding plurality of data bits produced at intermediate outputs of said divider, means coupled to said comparing means for generating an output signal when at least one set of compared memory and divider data bits are in coincidence, said output signal comprising a plurality of pulses the number of which is determined by said binary
  • said output signal generating means comprises an AND gate having a plurality of inputs coupled to respective outputs of said EXCLUSIVE OR gates, the output of said AND gate being coupled to said auxiliary input means by said feedback means.
  • said auxiliary input means includes means to reset said frequency divider to zero as a function of an output signal produced by said AND gate.
  • said auxiliary input means comprises a NAND gate having a first input coupled to the output of said resonator and an output coupled to an input of said frequency divider; and said comparing means comprises a plurality of AND gates having first inputs coupled to corresponding outputsof said memory means and second inputs coupled to corresponding ones of said frequency divider intermediate outputs.
  • said output signal generating means comprising and OR gate having a plurality of inputs coupled to respective outputs of said AND gates
  • said feedback means comprises an RS flip-flop having an input coupled to an output of said OR gate and an output coupled to a second input of said NAND gate.
  • auxiliary inpt means comprises means coupled to said output signal generating means for inhibiting only a single pulse of the divided resonator output signal during the period of each pulse of said generating means output signal.
  • said frequency divider comprises a chain of dividing stages
  • said auxiliary input means comprises intermediary circuit means coupled in series in said divider chain for supplying to succeeding divider stages in said chain a mean number of pulses different from the mean number of pulses received at its input, the difference between said mean numbers of pulses corresponding to a number stored in said memory; and i said feedback, means comprises a control circuit having one input coupled to at least one output of one stage of said dividing chain, a second input coupled to said output signal generating means, and an output coupled'to an input of said intermediary circuit means.
  • said comparing means comprises first gate means for gating the intermediate outputs of said divider with the stored data outputs from said memory means and said signal generating means comprises means for generating a first logic signal having a duration which is determined by the coded data stored in said memory means; suppressor means coupled to the output of said signal generating means for suppressing all outputs from said first gate means other than said first logic signal during a preset period; and said feedback means comprising further gate means for gating the output of said suppressor means with a further'intermediate output of said frequency divider, the output of said further gate means being fed back to the auxiliary input means of said frequency divider to adjust the frequency division ratio thereof.
  • Timekeeper according to claim 13, in which the memory is a memory with sequential inscription of data.
  • Timekeeper according to claim 13, in which the memory comprises at :least one inscription input connected to a logical variable which controls time display means.
  • Timekeeper according to claim 2, comprising autonomous means coupled to and supplying the memory with frequency adjustment signals.

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  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Electric Clocks (AREA)
  • Electronic Switches (AREA)
US236774A 1971-10-15 1972-03-21 Timekeeper Expired - Lifetime US3895486A (en)

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CH1511771A CH554015A (sr) 1971-10-15 1971-10-15

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US3895486A true US3895486A (en) 1975-07-22

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US (1) US3895486A (sr)
JP (1) JPS5623116B2 (sr)
BE (1) BE780107A (sr)
CA (1) CA951913A (sr)
CH (1) CH554015A (sr)
DE (1) DE2211441A1 (sr)
FR (1) FR2156523B1 (sr)
GB (1) GB1392524A (sr)
HK (1) HK18380A (sr)
IT (1) IT950298B (sr)
NL (1) NL7204364A (sr)

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US3967442A (en) * 1973-02-01 1976-07-06 Berney Jean Claude Electric watch having an electromechanical movement including a correction mechanism for small errors
US4015419A (en) * 1972-10-02 1977-04-05 Citizen Watch Co., Ltd. Electronic timepiece
US4020626A (en) * 1974-05-14 1977-05-03 Kabushiki Kaisha Daini Seikosha Electronic timepiece
US4043109A (en) * 1973-01-11 1977-08-23 Kabushiki Kaisha Suwa Seikosha Electronic timepiece
US4045952A (en) * 1975-03-08 1977-09-06 Casio Computer Co., Ltd. Electronic timepiece apparatus
US4051663A (en) * 1973-12-05 1977-10-04 Kabushiki Kaisha Suwa Seikosha Electronic timepiece
US4055945A (en) * 1975-12-15 1977-11-01 Timex Corporation Frequency adjustment means for an electronic timepiece
US4062178A (en) * 1973-04-19 1977-12-13 Kabushiki Kaisha Suwa Seikosha Electronic timepiece
US4068462A (en) * 1976-05-17 1978-01-17 Fairchild Camera And Instrument Corporation Frequency adjustment circuit
US4086755A (en) * 1974-11-14 1978-05-02 Kabushiki Kaisha Daini Seikosha Apparatus for correcting second hand of electronic timepiece
US4098070A (en) * 1975-01-13 1978-07-04 Kabushiki Kaisha Suwa Seikosha Digital display electronic wristwatch
US4106278A (en) * 1974-12-18 1978-08-15 Kabushiki Kaisha Suwa Seikosha Electronic timepiece utilizing semiconductor-insulating substrate integrated circuitry
US4114363A (en) * 1975-06-18 1978-09-19 Kabushiki Kaisha Suwa Seikosha Electronic timepiece
US4118922A (en) * 1975-12-27 1978-10-10 Canon Kabushiki Kaisha Electronic watch or clock and accessory devices therefor
US4133169A (en) * 1974-08-30 1979-01-09 Ebauches S.A. Electronic circuit for a quartz crystal watch
US4134254A (en) * 1974-12-17 1979-01-16 Casio Computer Co., Ltd. Electronic timepiece device
US4141208A (en) * 1976-01-19 1979-02-27 Hughes Aircraft Company Digitally tuned timepiece
US4150536A (en) * 1976-01-28 1979-04-24 Citizen Watch Company Limited Electronic timepiece
US4155218A (en) * 1976-04-23 1979-05-22 Ebauches S.A. Electronic watch
FR2409637A1 (fr) * 1977-09-23 1979-06-15 Bunker Ramo Generateur d'impulsions et dispositif d'accord pour ce generateur
US4162608A (en) * 1974-06-05 1979-07-31 Kabushiki Kaisha Suwa Seikosha Electronic timepiece frequency regulating circuit
US4165605A (en) * 1976-05-29 1979-08-28 Casio Computer Co. Ltd. Electronic timepiece
US4254494A (en) * 1975-01-31 1981-03-03 Sharp Kabushiki Kaisha Accuracy correction in an electronic timepiece
EP0031403A2 (en) * 1979-12-28 1981-07-08 International Business Machines Corporation Data processing apparatus including a time of day clock
US4282595A (en) * 1979-12-21 1981-08-04 Timex Corporation Method for digital frequency trimming an oscillator in an electronic timepiece
US4290130A (en) * 1979-12-21 1981-09-15 Timex Corporation Digital frequency trimmed electronic timepiece
US4292680A (en) * 1974-10-31 1981-09-29 Citizen Watch Company Limited Electronic timepiece
US4300224A (en) * 1977-10-18 1981-11-10 Kabushiki Kaisha Suwa Seikosha Electronic timepiece
US4321698A (en) * 1978-02-07 1982-03-23 Kabushiki Kaisha Suwa Seikosha Temperature compensated quartz wristwatch with memory stored predetermined temperature compensating data
US4345320A (en) * 1977-02-28 1982-08-17 Jean-Claude Berney Sa Integrated circuit for a time-piece
US4370067A (en) * 1978-04-11 1983-01-25 Citizen Watch Company Limited Electronic timepiece with gain/loss adjustment
US4378167A (en) * 1979-03-29 1983-03-29 Kabushiki Kaisha Suwa Seikosha Electronic timepiece with frequency correction
US4400093A (en) * 1981-07-06 1983-08-23 Omega Louis Brandt & Frere S.A. Method for inspecting the running of a timepiece and timepiece adapted for such method
US4407019A (en) * 1977-07-21 1983-09-27 Kabushiki Kaisha Suwa Seikosha Electronic wristwatch
US4724366A (en) * 1982-05-17 1988-02-09 International Business Machines Corporation Randomized motor drive
US4763309A (en) * 1986-07-10 1988-08-09 Em Microelectronic-Marin Sa Programming arrangement for a non-volatile memory for a timepiece
US4897860A (en) * 1988-03-02 1990-01-30 Dallas Semiconductor Corporation Programmable time base circuit with protected internal calibration
EP0479265A2 (de) * 1990-10-05 1992-04-08 D.I.E.N.E.S. Apparatebau Gmbh Steuerbarer Frequenzgenerator
US7031696B2 (en) 2001-04-27 2006-04-18 Csem Centre Suisse D'electronique Et De Microtechnique Sa-Recherche Et Developpement Timekeeper with automatic time setting and time setting method for same
EP1748561A1 (fr) 2005-07-25 2007-01-31 Jaquet Ingénieur Conseils Sàrl Procédé de thermocompensation d'une base de temps à quartz
EP2854293A1 (en) 2013-09-30 2015-04-01 Micro Crystal AG Temperature compensated timing signal generator
EP2854294A1 (en) 2013-09-30 2015-04-01 Micro Crystal AG Temperature compensated timing signal generator

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JPS4919854A (sr) * 1972-06-12 1974-02-21
JPS549912B2 (sr) * 1972-09-22 1979-04-28
JPS49130774A (sr) * 1973-04-19 1974-12-14
JPS5756034B2 (sr) * 1973-09-10 1982-11-27
JPS5759508B2 (sr) * 1973-09-21 1982-12-15 Suwa Seikosha Kk
US3945194A (en) * 1973-12-15 1976-03-23 Itt Industries, Inc. Electronic quartz clock with integrated circuits
CH1377974A4 (sr) * 1974-10-14 1976-10-29
JPS5156677A (sr) * 1974-11-14 1976-05-18 Seiko Instr & Electronics
JPS6024433B2 (ja) * 1975-08-01 1985-06-12 シチズン時計株式会社 時計用回路
JPS5227247A (en) * 1975-08-26 1977-03-01 Seikosha Co Ltd Signal generator with gt-cut quatz vibrator
JPS6046389B2 (ja) * 1975-09-18 1985-10-15 シャープ株式会社 電子時計
DE2616398C2 (de) * 1976-04-14 1978-06-01 Siemens Ag, 1000 Berlin Und 8000 Muenchen Schaltungsanordnung zur Regelung der Impulsfolgefrequenz eines Signals
CH608333GA3 (en) 1976-11-29 1979-01-15 Electronic time-measuring device
CH620565B (fr) * 1977-02-28 Ebauches Sa Piece d'horlogerie electronique.
CH617058B (fr) * 1977-07-18 Berney Sa Jean Claude Piece d'horlogerie electronique.
JPS6124957Y2 (sr) * 1979-12-28 1986-07-26
JPS56140281A (en) * 1980-04-01 1981-11-02 Citizen Watch Co Ltd Electronic timepiece
CH643106B (fr) * 1980-11-26 Suisse Horlogerie Garde-temps comprenant une chaine de diviseurs au rapport de division ajustable.
JPS6121116U (ja) * 1985-02-28 1986-02-07 セイコーエプソン株式会社 時間標準器

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US3581066A (en) * 1968-03-06 1971-05-25 Lear Siegler Inc Programmable counting circuit
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Cited By (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4015419A (en) * 1972-10-02 1977-04-05 Citizen Watch Co., Ltd. Electronic timepiece
US4043109A (en) * 1973-01-11 1977-08-23 Kabushiki Kaisha Suwa Seikosha Electronic timepiece
US3967442A (en) * 1973-02-01 1976-07-06 Berney Jean Claude Electric watch having an electromechanical movement including a correction mechanism for small errors
US4062178A (en) * 1973-04-19 1977-12-13 Kabushiki Kaisha Suwa Seikosha Electronic timepiece
US4051663A (en) * 1973-12-05 1977-10-04 Kabushiki Kaisha Suwa Seikosha Electronic timepiece
US4020626A (en) * 1974-05-14 1977-05-03 Kabushiki Kaisha Daini Seikosha Electronic timepiece
US4162608A (en) * 1974-06-05 1979-07-31 Kabushiki Kaisha Suwa Seikosha Electronic timepiece frequency regulating circuit
US4133169A (en) * 1974-08-30 1979-01-09 Ebauches S.A. Electronic circuit for a quartz crystal watch
US4292680A (en) * 1974-10-31 1981-09-29 Citizen Watch Company Limited Electronic timepiece
US4302828A (en) * 1974-10-31 1981-11-24 Citizen Watch Company Limited Electronic timepiece
US4086755A (en) * 1974-11-14 1978-05-02 Kabushiki Kaisha Daini Seikosha Apparatus for correcting second hand of electronic timepiece
US4134254A (en) * 1974-12-17 1979-01-16 Casio Computer Co., Ltd. Electronic timepiece device
US4106278A (en) * 1974-12-18 1978-08-15 Kabushiki Kaisha Suwa Seikosha Electronic timepiece utilizing semiconductor-insulating substrate integrated circuitry
US4098070A (en) * 1975-01-13 1978-07-04 Kabushiki Kaisha Suwa Seikosha Digital display electronic wristwatch
US4254494A (en) * 1975-01-31 1981-03-03 Sharp Kabushiki Kaisha Accuracy correction in an electronic timepiece
US4045952A (en) * 1975-03-08 1977-09-06 Casio Computer Co., Ltd. Electronic timepiece apparatus
US4114363A (en) * 1975-06-18 1978-09-19 Kabushiki Kaisha Suwa Seikosha Electronic timepiece
US4055945A (en) * 1975-12-15 1977-11-01 Timex Corporation Frequency adjustment means for an electronic timepiece
US4118922A (en) * 1975-12-27 1978-10-10 Canon Kabushiki Kaisha Electronic watch or clock and accessory devices therefor
US4141208A (en) * 1976-01-19 1979-02-27 Hughes Aircraft Company Digitally tuned timepiece
US4150536A (en) * 1976-01-28 1979-04-24 Citizen Watch Company Limited Electronic timepiece
US4155218A (en) * 1976-04-23 1979-05-22 Ebauches S.A. Electronic watch
US4068462A (en) * 1976-05-17 1978-01-17 Fairchild Camera And Instrument Corporation Frequency adjustment circuit
US4165605A (en) * 1976-05-29 1979-08-28 Casio Computer Co. Ltd. Electronic timepiece
US4345320A (en) * 1977-02-28 1982-08-17 Jean-Claude Berney Sa Integrated circuit for a time-piece
US4407019A (en) * 1977-07-21 1983-09-27 Kabushiki Kaisha Suwa Seikosha Electronic wristwatch
US4199726A (en) * 1977-09-23 1980-04-22 Bukosky Allen A Digitally tunable integrated circuit pulse generator and tuning system
FR2409637A1 (fr) * 1977-09-23 1979-06-15 Bunker Ramo Generateur d'impulsions et dispositif d'accord pour ce generateur
US4300224A (en) * 1977-10-18 1981-11-10 Kabushiki Kaisha Suwa Seikosha Electronic timepiece
US4321698A (en) * 1978-02-07 1982-03-23 Kabushiki Kaisha Suwa Seikosha Temperature compensated quartz wristwatch with memory stored predetermined temperature compensating data
US4370067A (en) * 1978-04-11 1983-01-25 Citizen Watch Company Limited Electronic timepiece with gain/loss adjustment
US4378167A (en) * 1979-03-29 1983-03-29 Kabushiki Kaisha Suwa Seikosha Electronic timepiece with frequency correction
US4282595A (en) * 1979-12-21 1981-08-04 Timex Corporation Method for digital frequency trimming an oscillator in an electronic timepiece
US4290130A (en) * 1979-12-21 1981-09-15 Timex Corporation Digital frequency trimmed electronic timepiece
EP0031403A3 (en) * 1979-12-28 1981-07-15 International Business Machines Corporation Data processing apparatus including a time of day clock
EP0031403A2 (en) * 1979-12-28 1981-07-08 International Business Machines Corporation Data processing apparatus including a time of day clock
US4400093A (en) * 1981-07-06 1983-08-23 Omega Louis Brandt & Frere S.A. Method for inspecting the running of a timepiece and timepiece adapted for such method
US4724366A (en) * 1982-05-17 1988-02-09 International Business Machines Corporation Randomized motor drive
US4763309A (en) * 1986-07-10 1988-08-09 Em Microelectronic-Marin Sa Programming arrangement for a non-volatile memory for a timepiece
US4897860A (en) * 1988-03-02 1990-01-30 Dallas Semiconductor Corporation Programmable time base circuit with protected internal calibration
EP0479265A2 (de) * 1990-10-05 1992-04-08 D.I.E.N.E.S. Apparatebau Gmbh Steuerbarer Frequenzgenerator
EP0479265A3 (en) * 1990-10-05 1992-05-13 D.I.E.N.E.S. Apparatebau Gmbh Controllable frequency generator
US7031696B2 (en) 2001-04-27 2006-04-18 Csem Centre Suisse D'electronique Et De Microtechnique Sa-Recherche Et Developpement Timekeeper with automatic time setting and time setting method for same
EP1748561A1 (fr) 2005-07-25 2007-01-31 Jaquet Ingénieur Conseils Sàrl Procédé de thermocompensation d'une base de temps à quartz
EP2854293A1 (en) 2013-09-30 2015-04-01 Micro Crystal AG Temperature compensated timing signal generator
EP2854294A1 (en) 2013-09-30 2015-04-01 Micro Crystal AG Temperature compensated timing signal generator

Also Published As

Publication number Publication date
HK18380A (en) 1980-04-18
JPS4848163A (sr) 1973-07-07
CA951913A (en) 1974-07-30
FR2156523B1 (sr) 1977-01-14
NL7204364A (sr) 1973-04-17
GB1392524A (en) 1975-04-30
FR2156523A1 (sr) 1973-06-01
CH1511771A4 (sr) 1973-12-28
DE2211441A1 (de) 1973-04-19
JPS5623116B2 (sr) 1981-05-29
CH554015A (sr) 1974-09-13
IT950298B (it) 1973-06-20
BE780107A (fr) 1972-07-03

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