US3895486A

US3895486A - Timekeeper

Info

Publication number: US3895486A
Application number: US236774A
Authority: US
Inventors: Walter Hammer; Eric Andre Vittoz; Jean Hermann; Hubert Choffat
Original assignee: Centre Electronique Horloger SA
Current assignee: Centre Electronique Horloger SA
Priority date: 1971-10-15
Filing date: 1972-03-21
Publication date: 1975-07-22
Anticipated expiration: 1992-07-22
Also published as: CA951913A; JPS4848163A; DE2211441A1; BE780107A; IT950298B; JPS5623116B2; CH554015A; GB1392524A; FR2156523B1; FR2156523A1; NL7204364A; HK18380A; CH1511771A4

Abstract

A timekeeper comprises a quartz crystal resonator having a stable frequency but with a relatively large tolerance, and a frequency divider with an adjustable divison ratio. Said divider has auxiliary electrical inputs the logical state of which determines the division ratio, and a memory, for example an electrically alterable electronic memory, supplies stored data to determine the logical state of the auxiliary inputs and hence the division ratio. The memory may comprise volatile and permanent parts, the permanent part intermittently regenerating data stored in the volatile part.

Description

United States Patent 1191 Hammer et al.

[ July 22, 1975 [54] TIMEKEEPER 3,629,582 12/197] Koehler 58/23 X 3,719,838 3 I973 P d t t l 310 [75] Inventors: Walter Hammer, Boudry, NE; Eric I e u o e a /8 I Andre vifloz, Cernier NE; Jean FOREIGN PATENTS OR APPLICATIONS Hermann, Neuchatel, NE; Hube 1,299,023 7/1969 Germany 58/23 R Choffat, Saint-Blaise, NE, all of Switzerland OTHER PUBLICATIONS Bentchkowsky, ROM can be electrically programed [73] Assigneez Centre Electronique I-Iorloger S.A., and repmgramedand reprogramed l Electronics Neuchatel, Switzerland May 10 1971 pp. [22] Filed: Mar. 21, 1972 Primary Examiner+Stephen J. Tomsky [21] Appl' 236774 Assistant ExaminerU. Weldon Attorney, Agent, or Firm-Stevens, Davis, Miller & [30] Foreign Application Priority Data Mosher Oct. 15, 1971 Switzerland 15117/71 [57] ABSTRACT [52] US. Cl. 58/23 R; 58/85.5 A timekeeper comprises a quartz crystal resonator [51] ll'll. Cl. G04b 27/00 having a Stable frequency but with a relatively large [58] Fleld 0f Search 307/225; 328/48, I20; tolerance and a frequency divider with an adjustable 58/23 23 23 divison ratio. Said divider has auxiliary electrical in- 23 50 152 57; 3 l0/8'l puts the logical state of which determines the division ratio, and a memory, for example an electrically alter- [56] References cued able electronic memory, supplies stored data to deter- UNITED STATE PATENT mine the logical state of the auxiliary inputs and hence 3,166,888 1/1965 Kartaschoff 58/23 R the division ratio. The memory may comprise volatile 3,540,207 11/1970 and permanent parts, the permanent part intermit- 3,581,066 5/1971 tently regenerating data stored in the volatile part. 3,621,403 11 1971 3,624,517 11/1971 Kobayashi 328/48 x 21 Clams, 28 Drawlng Flgures SEQUENTIAL LOGICAL 5 5 7 CIRCUIT 8 A B r 2 +2 2 PULSE GEN.

COMPARING MEMOR CIRCUIT 1 4 Y 13 AND LOGICAL GATE NI I a 7R 0 i 1-1 l SUPPRESSION CIRCUIT mmnmmzz ms E 3.895486 SHEET I 1 2 PRIOR ARTFIg. 1 4

L I MOTOR PULSE GEN.

SEQUENTIAL LOGICAL MOTOR 5 5 7 CIRCUIT 8 PULSE GEN.

c \D E G H I .7 \K

MEMORY g r 1 1' L GICAL a i N a R u I 1 i J'K Fig.2

' \SUPPRESSION CIRCUIT Fig.

SET

PATENTEDJUL 22 ms F ELF "T I 53 Fig. 15

1, TIMEKEEPER,

The invention relates to timekeepers of the type comprising a resonator and a frequency divider with an adjustable division ratio.

In timekeepers comprising a time base and a frequency divider, the required output frequency of pulses from the frequency divider is generally obtained by providing both that the time base, usually formed by a quartz-crystal-controlled pulse generator or a diapason (tuning fork), has an exactly determined frequency, and that the frequency divider has an exactly determined division ratio.

This necessitates a careful adjustment of the time base which, for example in the case of a quartz crystal resonator, is carried out with the following steps:

1. Rough adjustment, in which the relative divergence Af/ f between the natural frequency of the quartz resonator and its nominal value passes from about 10 to l;

2. Fine adjustment, in which Af/f passes from 10 to

several units X

10 and 3. Final adjustment and compensation for ageing, in which Af/f passes from several units X to less than 10 These steps each require delicate and costly operations, especially difficult to carry out for miniature quartz crystals intended for portable timekeepers such as those for wrist watches. In effect, for energy consumption reasons, miniature quartz crystals must oscillate at low frequencies, typically comprised between 8 and 64 KHz. Such resonators are formed by bars oscillating in flexion and their small dimensions, in particular the reduced thickness, require an extremely great precision in cutting the crystal. The rough adjustment takes place by filling the ends of the bars, in very difficult working conditions. The required frequency precision of 10 for encapsulated quartz resonators is particularly difficult to achieve, since for wrist watches the resonators must have a shock-resistant suspension, the

rigidity tolerances of which have an appreciable influ-.'

ence on the frequency, and a small casing. Both the suspension and the casing may, during the final stages of manufacture, modify the frequency of the quartz resonator by several units X 10' This frequency difference can be partly compensated for by providing an adjustment after closing the casing, and by arranging two windows through which a metallic layer can be deposited on the ends of the quartz crystal bar before closing the windows and evacuating the casing; however, this is a complex and costly operation. Lastly, the final adjustment is usually carried out by means of an adjusting capacitor in series with the quartz crystal in the resonator circuit.

This procedure has numerous drawbacks which adversely effect both the precision and the cost of the finished product, for example a wrist watch. The rougn and fine adjustments are detrimental to the frequency stability of the quartz resonator and increase ageing effects. The final adjustment requires use of an adjustable element (capacitor) the stability of which also effects the-frequency stability of the resonator, which therefore becomes sensitive to exterior influences such as 'the temperature, humidity, dust, and so on.

Moreover, the rough and fine adjustment operations being delicate, they must be carried out using complex equipment and taking special'precautions, which considerably adds to the cost price of the resonator. The

adjusting capacitor is also a fairly expensive component and takes up valuable space.

It has been proposed (W. German published patent application DAS l, 946, 166, Timex corresponding to US. Pat. No. 3,540,207 to Rieler) to do away with the adjusting capacitor by employing a frequency divider whose division ratio is adjustable by means of an inhibition member. One of the described embodiments provides a potentiometer for adjusting the duration of this inhibition, which amounts to replacing one precisely adjustable element by another component subject to the same requirements of maintaining a stable value. Another of the described embodiments provides switches (commutators) which enable modification of the division ratio by inhibition of a number of pulses equal to 2 to the power of any whole positive number (including zero), i.e. l, 2, 4, 8 pulses. These embodiments thus also replace one delicate electromechanical component by another one subject to the same problems of stability, bulk and cost. Pulses from an integrated circuit, to which the switch is exterior, pass through the switch, which can involve dangers such as errors in operation, excessive consumption, and overloading of the circuit, especially in a humid, corrosive or dusty atmosphere. Moreover, it can easily be shown that this arrangement enables neither a very large correction of the division ratio, nor a fine adjustment of this ratio.

Dividers with adjustable division ratios operating according to otherprinciples are also known and used, in particular in frequency synthetisers. However, most types have characteristics which render them inapplicable to use in wrist watches, either because of difficulties that would be involved in providing them in integrated form, or for diverse other reasons. For example,

a known adjustable frequency divider operatingby inhibition (W. German Patent Publication No. l, 299,

023, Lorenz) requires, in addition to a principal frequency divider, an auxiliary counter operating at the same frequency as the principal divider, which doubles the power consumption and requires switches (commutators) which can be arranged in combinations to determine the desired division ratios. The inclusion of such switches would involve problems of availability of space, cost and, especially, would make adjustment of running of a timekeeper rather difficulty, especially for the user or an after-sales service. 1

The general aim of the invention is to eliminate these drawbacks and to enable the introduction of new possibilities of adjustment of a timekeeper which could not be carried out by the previously known means. A specific aim is to propose a satisfactory solution to the problem of obtaining a precisely adjustable timekeeper comprising a quartz resonator whose frequency is stable but may be comprised within relatively large tolerances.

'According to the invention, a timekeeper comprises a resonator, a frequency divider with an adjustable division ratio, said divider having auxiliary electrical inputs the logical state of which determines the division ratio, and a memory connected to said auxiliary inputs, said memory storing coded data which determine the logical state of said auxiliary inputs and therefore the division ratio of the divider.

Several important advantages stem from the arrangement according to the invention.

Manufacture of the resonator is simplifed, requiring operations to ensure a stable frequency and defined temperature characteristics, but requiring only a minimum of precautions concerning the frequency tolerances. This has a decisive influence on the cost price of the resonator.

The other components of the timekeeper, including the frequency adjustment means, can be digital components whose individual variations or tolerances can be fairly great without influencing the accuracy of the timekeeper.

The frequency adjusting operation can take place by means of integratable circuits, which contributes to the reliability of the timekeeper, enables miniaturization, and makes mass production with the consequent low manufacturing cost possible.

The increase in complexity of the circuitry is not very great and does not involve an appreciable increase in the consumption if complementary MOS transistors (with substantially dynamic consumption) are employed. The increase in the complexity of the circuitry does not unfavourably influence the overall price, because of the economy made in other components such as the miniature switches and in the number of connections.

Another aim of the invention is to facilitate ajustment of the division ratio by electrical control. In particular, the invention makes possible a rapid frequency setting by the sequential introduction of data concerning the division ratio. Introduction of this data can take place by means of one connections to a single input terminal of the circuit.

In a preferred embodiment of the invention, the

memory is an electrically alterable memory.

The advantage of an electrically alterable memory is that it enables, at any time, a change of the division ratio solely by means of electrical pulses, without having to modify connections of the circuit.

Embodiments of the invention will now be particularly described, by way of example, with reference to the accompanying schematic drawings, in which;

FIG. 1 shows a clock comprising a time base and a frequency divider forming a conventional timekeeper,

' as well as a motor and motion-work actuated by the frequency divider;

FIG. 2 is a block diagram of a first embodiment of timekeeper according to the invention;

FIG. 3 shows one type of the memory of the timekeeper of FIG. 2, in the form of a shift register;

FIG. 4 shows another form of memory;

FIGS. 5 and 6 show two variants of part of a memory respectively including a MNOS component and a FAMOS component;

FIG. 7 shows in detail the logical circuit of unit 13 of FIG. 2;

FIG. 8 is a diagram illustrating the operation of the logical circuit of FIG. 7;

FIG. 9 shows in detail the logical circuit of unit of FIG. 2;

FIG. 10 is a diagram illustrating the operation of the logical circuit of FIG. 9;

FIG. 11 shows the unit 9 of FIG. 2, namely a logical gate;

FIG. 12 is a diagram illustrating the operation of the gate of FIG. 11;

FIG. 13 shows in detail the logical circuit of unit 7 of FIG. 2;

FIG. 14 is a diagram illustrating the operation of the logical circuit of FIG. 13;

IG. 15 is a block diagram of a second type of adjustable divider formed by a single division stage carrying out division either by one or by two;

FIG. 16 is an explanatory graph showing operation of the stage of FIG. 15;

FIG. 17 shows a third type of adjustable frequency divider having a dividing chain formed of four stages and a comparator adjusting the dividing chain according to the principle described with reference to FIGS. 15 and 16;

FIG. 18 is an explanator graph showing operation of the divider of FIG. 17;

FIG. 19 shows a fourth example of adjustable divider comprising a dividing chain and a comparator adjusting the dividing chain;

FIG. 20 is an explanatory diagram showing the operation of the divider of FIG. 19;

FIG. 21 shows an example of volatile electronic memory intended to be connected to the comparator of a timekeeper including the divider shown in FIG. 17

or 18 to adjust the division ratio;

FIG. 22 shows a device for supplying the memory of FIG. 21;

FIG. 23 shows another type of memory for a timekeeper including the divider of FIG. 17 or 19, this memory being in the form of a counter;

FIG. 24 shows a device for having access to the memory of FIG. 23;

FIG. 25 shows a device for controlling the zeroing and inscription in a memory of the type shown in FIG. 23;

FIG. 26 is a diagram explaining the operation of the device of FIG. 25;

FIG. 27 shows another example of a memory; and

FIG. 28 shows a variant of the memory of FIG. 27. FIG. 1 shows a known type of clock comprising a quartz-crystal-controlled pulse generator 1, a series of binary dividers (flip-flops) 2, and a step-by-step motor 3 driving a motion work (or dial-train) 4. The dividing chain formed by the dividers 2 has a given division ratio, and to ensure the accuracy of the clock, the frequency of the generator 1 must be exactly adjustedlln such a clock, the frequency of the generator could be 2 8192 Hz and the dividing chain could comprise fourteen binary dividers, so that the output frequency of the chain is 0.5 Hz, suitable for driving the step-bystep motor 3.

FIG. 2 is a block diagram of a first embodiment of timekeeper according to the invention. The dividing chain comprises fourteen binary dividers and the quartz crystal, whose nominal frequency must be 8192 Hz, is supposed to be adjusted to a precision of 10", the precision of the timekeeper being adjustable to 3.8

Y X 10 by acting on the division ratio of the chain.

The timekeeper shown in FIG. 2 comprises a quartzcrystal-controlled pulse generator 5, a first binary divider 6, a sequential logical circuit 7 one input A of which receives output pulses from the divider 6 and whose output B supplies a chain of 13 further binary dividers 8. The logical circuit 7 also comprises an input C supplied by a thermal compensation device or alternatively by a time setting device (not shown), and an input D supplied by the output of a unit 9. The effect of the logical circuit 7 is to block the supply of pulses from the divider 6 to the first of the dividers 8 when the input C has the logical value 1 and to block the supply of only a single pulse from the divider 6 to the first of the dividers 8 each time that the input D takes the logical value 1, whatever be the duration during which this input D holds the logical value 1. The sequential circuit 7 and its operation will be described in full detail further on with reference to FIGS. 13 and 14. The functional unit 9 has two inputs E and F and one output connected to the input D of the circuit 7. This unit 9 is formed by an AN D logical gate carrying out the operation D EF, and will be described with reference to FIGS. 11 and 12. The output of the final divider 8 of the chain supplies: the input of a step-by-step motor 10 controlling a motion-work 11; the first divider of a chain of five binary dividers l2; and the input E of the unit 9.

Five outputs G, H, I, J, K of the respective dividers 12 supply corresponding inputs of a unit 13 comprising five further inputs L, M, N, O, P and two outputs Q, R. This unit 13 is formed by a combinative logical circuit carrying out the logical functions:

R K, and will be described in detail with reference to FIGS. 7 and 8.

The inputs L, M, N, O, P of the unit 13 are supplied by the corresponding outputs of a memory 14 storing data for the adjustment of the division ratio of the chain of dividers 8. This memory is an electronic memory, examples of which will be described with reference to FIGS. 3, 4, 5 and 6 and FIGS. 21 to 28.

The two outputs Q and R of the unit 13 supply two 9 corresponding inputs of a unit 15 whose output supplies the input F of unit 9. The purpose of this unit 15 is to suppress the redundant logical states 1 of the variable Q. It is formed by a sequential logical circuit which will be structurally and operatively described with reference to FIGS. 9 and 10.

FIG. 3 is a partial view of a first'embodiment of the memory 14 of FIG. 2. This memory 14 is formed by'a shift register comprising five D-type flip-flops, 16, 17, 18, 19 and 20 whose inputs are indicated by U, the outputs by V, and the controls by W.

To introduce an instruction number L, M, N, O or P, the logical values of P, O, N, M, L in the indicated order are successively applied to the terminal S, each time applying a control pulse to the terinal T. This will result in the terminals L, M, N, O, P being brought to the required logical values. Hence, all possible combinations can be obtained at these outputs L, M, N, O, P of the memory. Because each output can take two

states

1 or 0 and the described memory of FIG. 3 has five output terminals, there are 2 32 different combinations. For example, the output terminals can take the binary number 01010. Another type of memory is shown in FIG. 4. This memory comprises five groups of fusible metallized elements each composed of two

elements

21 and 22 connected in series. Each of these groups of seriesconnected elements is connected on the one hand to a line held at a potential 0 and onthe other hand to a line held at a potential 1. To choose the out;uts L, M, N, O, P of the memory of FIG. 4, it suffices to rupture one of each pair of

fusible elements

21 and 22. To rupture the element 21 for the output L for example, a large current can be passed between an appropriate set terminal and the line 0; after rupture of the element 21, the output L will thus always remain at a potential 1. When one of the

elements

21 or 22 of each pair is ruptured,

the memory can be used to apply the logical values obtained to the auxiliary inputs of the unit 13 (FIG. 2).

The variants of FIGS. 5 and 6 each represent a single cell comprising an output L of two types of permanent electrically alterable electronic memory. This type of memory resolves the problem of the loss of data when changing the supply battery or cell. FIG. 5 shows a known type of MNOS transistor, i.e. a MOS transistor with a supplementary layer of nitride which enables variation of the transistor threshold. The application of a high voltage to the inscription or set input enables this threshold value of the MNOS transistor to be changed. The output L will take the value 1 if the threshold is low and 0 if the threshold is high. FIG. 6 shows a FAMOS transistor also of known type, this being a MOS transistor with a floating grid. The grid may be charged by the application of a high voltage to its drain by the inscription set terminal. The FAMOS transistor will thus be conducting and the output L will take the value 1. To reset L to 0, the grid must be discharged, which can be achieved by ultra-violet radiation or X-rays.

Certain of these electrically alterable memories require high reading currents. It is however possible to provide a permanently supplied volatile buffer memory with low consumption, regenerated at relatively long intervals of time by the permanent memory which is supplied only when the volatile memory is regenerated. Such a system is described in connection with FIG. 27.

FIG. 7 is a detailed block of the logical circuit shown by unit 13 of FIG. 2. This circuit comprises five AND gates 23 each with two inputs connected to respective ones of the outputs G, H, I, J, K of the dividers l2 and to respective ones of the outputs L, M, N, 0, P of the memory 14. The fiveoutputs of the AND gates 23 are connected to five corresponding inputs of an OR gate 24 having an output Q. The second output R of the circuit is connected directly to the output K. Operation of this circuit is schematically illustrated in the graph of FIG. 8. The graphs G and K represent the output pulses of successive dividers 12, the frequency being in each case half the frequency of the previous divider. If the quartz crystal had the nominal frequency indicated above, 2 8192, the frequency of signal G would be 2 2 2 0.25- I-Iz, the corresponding half-period of 2 seconds being indicated on graph G.

It can be seen that since the outputu Q is represented by the function Q=GL+ HM+IN+JO+KP, and since the binary number n LMNOP,

the duration of the first pulse of signal Q will be equal to n times the duration of one pulse of signal G, namely 2n seconds. If the outputs of the block 14 of FIG. 2 are for example n LMNOP 01010 2 2 10,

the duration of the first pulse of the signal Q is thus 10 times the duration of a pulse G, namely 20 seconds. As can be seen on FIG. 8, pulses of duration 2n see. are then repeated every 32 seconds.

FIG. 9 shows a sequential logical circuit forming the unit 15 of FIG. 2, the purpose of which is to suppress unwanted logical states 1 of the signal Q. The signal 0 is applied to one of the inputs of an AND gate 25 the other input of which is supplied by the output of an OR gate 26. One of the inputs of the OR gate 26 is supplied by the output signal F of the AND gate 25 and the other by the output of an AND gate 27. One of the inputs of the AND gate 27 is supplied by the output of a reverser (throw over switch) 28 whose input is supplied by the output of an AND gate 29 also supplying one of the inputs of an OR gate 30 whose other input is supplied by the output signal P. The other input of the AND gate 27 as well as one of the inputs of the AND gate 29 are supplied by the signal R, the other input of the AND gate 29 being supplied by the output of the OR gate 30.

The purpose of this logical circuit can best be seen by referring to FIG. 10, showing the output signal F deduced from the input signal Q by suppression of pulses other than the above-referred-to pulses of duration proportional to n LMNOP produced while R has the value 1, pulses F thus having a periodicity of 64 seconds.

FIG. 11 shows, in conventional logical symbolism, the unit 9 of FIG. 2 which is formed by a single AND gate 48 whose inputs are respectively supplied by the signals E and F. Since the signal E is formed by pulses with a period of 2 sec. and the signal F is formed by pulses of logical value 1 with a duration of Zn sec.

which repeat every 64 seconds, the output signal D of the gate 48 will be formed by trains of n pulses emitted every 64 seconds, this being clearly illustrated in FIG.

FIG. 13 shows a sequential logical circuit forming the unit 7 of Flg. 2. The purpose of this circuit is to prevent the supply of the pulses from the binary divider 6 to the first division stage 8 whilst the input signal C has the logical value 1, and to only prevent the supply of a single pulse when the signal D takes the logical value 1, this independently of the duration during which the signal D holds this value, this being clearly shown in FIG. 14. For this purpose, the sequential logical circuit of FIG. 13 comprises an AND gate 31 one input of which receives the signal A via an inverter 49 and whose output is connected to the input of an OR gate 32. The output of this latter is applied, on the one hand, to the other input of the gate 31 and, on the other hand, to one of the three inputs of an OR gate 33 whose output supplies the signal B. The input signal D is applied to one of the inputs of an AND gate 34 and to one of the three inputs of another AND gate 35. The signal A moreover supplies another of the inputs of both the AND gate 35 and the OR gate 33. The circuit also comprises an OR gate 36 supplying, on the one hand, the second input of the AND gate 34 and, on the other hand, the third input of the AND gate 35 via a reverser 37. The two inputs of the OR gate 36 are respectively supplied by the outputs of AND

gates

31 and 34, and the second input of the OR gate 32 is supplied by the output of AND gate 35. Finally, the input signal C is applied to the third input of the OR gate 33. The signal C may come from a thermal compensation circuit, or alternatively a time-setting device. As the step-by-step motor operates at 0.5 Hz, it is not possible to block it for only 1 second. If the setting of the seconds hand of the clock took place by mechanically acting on the motor, it could only have a precision of about i 1 second. Setting by blocking the division remedies this drawback.

Naturally, the above described units may be grouped so as to form more complex units, which can in certain cases lead to an overall simplification.

Operation of the described ti mekeeper is as follows:

Each blockage must lower the frequency deviation by 3.8 X 10, since this is the precision that it is desired to reach, as indicated above. During one period t, it may be necessary to have a maximum of 10 3.8 X 10 26 blocking operations to compensate for the maximum deviation in the frequency which has been fixed at, or assumed to be, 10". The unit 14 must thus be able to memorize numbers n comprised between 0 and 26. In pure binary code, five binary variables are therefore required, as provided in the memories of FIGS. 3 to 6.

So that each blockage lowers the frequency deviation by 3.8 X 10*, the transmission of pulses is blocked during two periods of oscillation of the quartz crystal, this occurring every 1 2 X 64 seconds.

It would also be possible to block the transmission of pulses during a single period of oscillation of the quartz crystal. Blockage would thus have to take place every 32 seconds, but the consumption of the unit 7, which increases as the working frequency increases, would thus be increased. In this case, the unit 7 would be connected directly after the output of the generator 5 instead of after the first divider 6.

As a variant, the signal D could serve to reduce the division ratio if the initial frequency of the quartz crystal were lower then 2 8192 Hz.

A second embodiment of adjustable divider is shown in FIG. 15. This divider 51 comprises a single binary dividing stage 52, whose input I is connected on the one hand to a resonator, not shown, for example a quartz crystal resonator, and on the other hand to a first input of an AND gate 53. The output of the stage 52 is connected to a first input of a second AND gate 54. The second inputs of the

gates

53 and 54 are on the one hand connected together via an inverter 55 and, on the other hand, connected to an auxiliary input terminal L. The outputs of the

gates

53 and 54 are connected to respective inputs of an OR gate 56, whose output S provides the output signal of the divider. Itcan immediately be seen that the routing formed by the

gates

53, 54, 56 and the inverter 55 receives the output signal of the divider and the input signal, as well as a control signal applied to the auxiliary input terminal L. According to the

logical value

1 or 0 applied to the auxiliary input L, the divider 51 will divide by l or by 2. FIG. 16 shows the output signal obtained at the output terminal S of the divider as a function of the signals applied to the inputs I and L. It can be seen that the divider divides by two when no signal of value I is applied to the input L. As soon as a signal I is applied to the input L, the gate 53 conducts and the input signal I passes directly to the output S. The division stage 52 is thus by-passed.

FIG. 17 shows a third type of adjustable frequency divider. This divider 57 comprises four binary division stages 58, 59, 60 and 61 connected in series, the input I of the first stage 58 being connected to a resonator, not shown. The outputs of the stages 58 to 61 are respectively connected to inputs L, M, N, and O of four two modulo

gates

62, 63, 64 and 65 (also known as EXCLUSIVE OR gates), the output of the stage 61 also being connected to an output terminal S of the timekeeper. The outputs of the gates 62 to 65 are connected to corresponding inputs of an AND gate 66 through inverters 62' to 65. Each second input of the gates 62 to 65 is connected to an auxiliary input terminal L, M, N and respectively, these auxiliary inputs L, M, N, 0 being controlled by a memory arranged to supply a logical signal 0 or I to each of the inputs L, M, N and 0. Examples of this memory will be described in detail further on. The output Z of the AND gate 66 is connected to four zeroing inputs of the stages 58 to 61.

In operation, the four binary stages 58 to 61 of this divider function to count the pulses I" supplied by the resonator, and are set to zero when the output Z of the gate 66 has the value I. The zeroing variable Z has the value 1 when the state of the counter is identical to the state of the auxiliary inputs, that is when L L, M M, N, and O 0'. Consequently, the counter formed by the stages 58 to 61 counts by a number which corresponds to the state of the auxiliary inputs in binary code.

FIG. 18 shows the output signal Z (of AND gate 66) as a function of the inputs T", L, M, N, O, by way of example, for the auxiliary input values L l, M O, N 0, O l, (1001), which is the binary expression of the chosen number 9. It can be noted that two successive zeroing pulses l at the output Z of gate 66 are separated by an amount corresponding to nine periods of the input I.

FIG. 19 shows a fourth form of adjustable divider, comprising an inhibition circuit formed by an RS flipflop 67, an inverted AND gate 68 and an inverter 69, said circuit being connected between an input I connected to a resonator, not shown, and four binary division stages 70, 71, 72 and 73. The outputs of these four stages 70 to 73 are connected to the inputs of four corresponding AND

gates

74, 75, 76 and 77, the outputs of which lead to an OR gate 78 connected to the flipfiop 67. The second inputs of the AND gates 74 to 77 'form the auxiliary inputs L, M, N, O which are connected to a memory, not shown. As for the embodiment of FIG. 19, it can be seen that the inhibition circuit formed by the flip-flop 67, the gate 68 and the inverter 69 is controlled by the auxiliary inputs L, M, N and O and by the division chain formed by the four stages 70 to 73 via the gates 74 to 78. It is thus possible to eliminate one input pulse 1 every 2, 4, 8 or 16 periods of the variable x (at the output of gate 68) according to whether either one of L, M, N or 0 have the value 1. The overall division ratio will thus be respectively 24, 20, 18 or 17.

As mentioned above, the timekeepers which are adjustable by means of the auxiliary inputs are coupled with memories which can be of several types, a few examples of which will now be described.

A simple memory in the form of fusible elements, such as that shown in FIG. 4, enables the desired logical values to be applied at the auxiliary inputs of an adjustable divider. This type of memory however has the drawback of requiring a large number of inputs in the integrated division circuit. Also, subsequent modification of the memorized value is not possible.

A volatile electronic memory, such as that shown in FIG. 21, is more suitable than a system of switches for example. The type of volatile memory of FIG. 21, provided for example by means of two looped

inverters

80 and 81 and an input 82 enabling the desired state to be produced, has the advantage of being entirely compatible with the circuit technology used for the adjustable divider, and the assembly can be integrated. The result is the elimination of a bulky and delicate electromechanical member as well as of numerous interconnections, therefore an increase in the reliability and a reduction of the unit cost by mass production. It is clear that to supply each of the four inputs L, M, N, O of the dividers shown in FIGSJ17 and 19, a pair of inverters and 81 would be provided as well as one input 82 for each of the variables L, M, N and 0. With such memories, precautions must be taken to avoid a loss of data, for example when changing the supply cell. It is possible, for example, to use a separate long-life cell to supply the memories. It is also possible to provide a buffer capacitor charged by the cell and disconnected from the cell when the voltage of the latter begins to drop. The circuit shown in FIG. 22 is a simple embodiment of this idea, in which the disconnection of a capacitor 83 is provided by a diode 84 supplied by a cell 85. The buffer capacitor 83 can also be replaced by a rechargeable cell or an accumulator. With the circuit of FIG. 22, the output S is used for supplying the circuit (frequency divider, time base, and so on) and the output S to supply the memory.

To reduce the number of inscription inputs, it is possible to provide a series or sequential inscription memory by means of a shift register or counter. The number of inputs is thus reduced to two, whatever be the complexity of the memory. FIG. 23 shows a counter formed by four

binary stages

86, 87, 88, 89 having two input terminals, an input terminal IN receiving pulses to be counted and an input terminal R2 for zeroing the counter. The outputs L, M, N, O are taken at the output of each of the stages 86 to 89.

It is possible to even further reduce the number of inputs in the integrated circuit for having access to the memory by connecting the two inputs IN and R2 of the counter of FIG. 23 to the outputs of a routing circuit controlled by a logical variable made visible by a display, for example the variable beating the seconds, the input of the routing circuit being the only input resulting in access to the memory. Such a routing circuit is shown in FIG. 24, formed by two AND gates 90 and 91 whose outputs IN and R2 are applied to the corresponding inputs of the counter of FIG. 23. A first input of each of the gates 90 and 91 is connected to a'single input terminal FI and the second inputs of these two gates 90 and 91 are connected, on the one hand, together via an inverter 92 and, on the other hand, to an auxiliary input A which is connected to the output of the divider shown in FIG. 19 and will thus receive a signal beating the seconds. It is thus possible, by acting on the input F, during even seconds, to zero the counter for example, and during a subsequent odd second, to place it in the desired state by acting on this same input.

To carry out this inscription, an external frequency setting apparatus can be used. This apparatus comprises a device schematically shown in FIG. 25 which must give a zeroing pulse when a button 93 is pressed (during an even second) and which must, one second later, automatically deliver the number of pulses corresponding to a number given by means 94 for preselecting the division ratio. Setting of the frequency by means of this automatic device greatly simplifies this delicate operation. For watches with a digital electronic display,

a device of the same type as that of FIG. 25 also enables setting the time.

In the explanatory diagram of FIG. 26, the impulse 95 corresponds to setting to zero during even seconds and the pulses 96 comes from the output F of the device of FIG. 25 after 1 second.

Certain of the permanent electrically alterable memories which have just been dscribed require relatively large reading currents. To remedy this, it is possible to provide a permanently supplied volatile buffer memory 97 (FIG. 27) with a low consumption, regenerated at long intervals of time by the permanent memory 98 which is supplied only upon the regeneration of the volatile memories. The permanent memory 98 is connected to the volatile memory 97 by AND

gates

99, 100, 101 and 102. The volatile memory is directly connected to a current source 103, whilst the permanent memory 98 is connected to this source 103 via a switch 104 controlled from a terminal F which will only be supplied to periodically regenerate the volatile memory by means of data stored in the permanent memory.

Another advantageous mixed type of memory, consists of using a permanent memory 105 (FIG. 28)

for large correction values, and a volatile memory 106 for the fine adjustment of the division ratio. In this case, a possible loss of data of the volatile memory will only effect the running of the timekeeper or watch to a small extent.

For the sake of simplicity of the drawings, the described embodiments of timekeepers comprise four binarystages and the memories for adjusting the division ratio also store four variables. It is however clear that thenumber of binary stages of the timekeepers, and the number of variables of the memories, can be increased. A timekeeper of the described type could have 19 division stages and a memory storing from four to variables.

In the above-described timekeepers, two types of memories have been used: electromechanical memories, and electrically alterable electronic memories. Whilst the electrically alterable electronic memories are more complex and more costly than electromechanical memories, they nevertheless have numerous advantages.

ADVANTAGES OF ELECTRICALLY ALTERABLE MEMORIES To alter the division ratio following a modification of the characteristics of the quartz crystal, it suffices to change the data supplied by the memory, without having to modify the internal connection of the circuit and without being dependant on an analogue component such as a trimmer capacitor or potentiometer (sensitive to humidity).

The division operation takes place entirely within the integrated circuit and neither an intermediate dynamic output nor an intermediate input is necessary, which eliminates ohmic and capacitative losses of such outputs or inputs and avoids disturbance of the division operation.

The value of the division ratio may be comprised within very wide limits without the circuit requiring any precision analogue component, nor an undue increase in its complexity, bulk of manufacturing cost.

Inscription of the value of the division ratio can take place by means of an electrical apparatus. This operation can take place entirely automatically and, for a watch, does not require any manual operation to be effected inside the casing.

Inscription in the memory can take place by means of a limited number of inputs by inscription in a given series or sequence.

The number of inputs in a watch can be reduced to one by using a memory with sequential input, for example a counter, and a means for routing the data controlled by an internal variable made visible by the watch display (for example the second displayed).

If a volatile memory is used, a separate supply can be used for the memory. This eliminates the drawback of loss of data at the moment of changing the supply cell. Such separate supply may be either by a miniature cell with a useful life of several years, or a capacitor or rechargeable buffer cell disconnected from the supply cell by electronic means for holding the voltage at the terminals of the memory during changing of the supply cell.

If the value of the division ratio must be modifiedas a function of certain parameters, these parameters could act directly on the memory. The separation of the memory into two parts, a permanent part serving for rough adjustment and volatile part for a fine adjustment of the division ratio, eliminates the risk of any substantial error in the timekeeping if the supply cell should be changed without taking certain precautions. This solution also simplifies the making of corrections, since an action on only the volatile memory is sufficient to carry out small corrections.

The memory can be. provided in various manners using different technological means, providing that its outputs are of logical values compatible with the adjustable divider. For example, electromechanical, volatile electronic, electrically alterable permanent electronic memories, and so on, can be used.

Electrically alterable permanent memories may require a high power for reading thereof; this drawback can be avoided by transferring the data stored in such memories at long intervals of time to a volatile buffer memory which can be permanently read with a low power consumption.

What is claimed is:

l. A self-adjusting timekeeping apparatus comprising: a resonator producing a pulsed output signal having a non-adjusted frequency; a frequency divider coupled to said resonator for dividing the frequency of the output singal of said resonator, said frequency divider including auxiliary input means for adjusting the frequency division ratio thereof; memory means for store ing coded data in the form of a plurality of binary data bits; and frequency adjusting means coupling said memory means to said auxiliary input means for adjusting the frequency division ratio of said frequency divider as a function of the coded data stored in said memory means to thereby adjust the output frequency of said frequency divider, said frequency adjusting means including means for comparing the binary coded data bits stored in said memory means with a corresponding plurality of data bits produced at intermediate outputs of said divider, means coupled to said comparing means for generating an output signal when at least one set of compared memory and divider data bits are in coincidence, said output signal comprising a plurality of pulses the number of which is determined by said binary coded data bits stored in said memory means, and means for feeding said output signal back to said auxiliary input means for adjusting the output frequency of said divider.

2. The apparatus according to claim 1, wherein said comparing means comprises:

a plurality of EXCLUSIVE OR gates having first inputs coupled to corresponding outputs of said memory means and second inputs coupled to corresponding ones of said intermediate frequency divider outputs; and said output signal generating means comprises an AND gate having a plurality of inputs coupled to respective outputs of said EXCLUSIVE OR gates, the output of said AND gate being coupled to said auxiliary input means by said feedback means. 3. The apparatus according to claim 2, wherein said auxiliary input means includes means to reset said frequency divider to zero as a function of an output signal produced by said AND gate.

4. The apparatus according to claim 1, wherein: said auxiliary input means comprises a NAND gate having a first input coupled to the output of said resonator and an output coupled to an input of said frequency divider; and said comparing means comprises a plurality of AND gates having first inputs coupled to corresponding outputsof said memory means and second inputs coupled to corresponding ones of said frequency divider intermediate outputs.

said output signal generating means comprising and OR gate having a plurality of inputs coupled to respective outputs of said AND gates, and said feedback means comprises an RS flip-flop having an input coupled to an output of said OR gate and an output coupled to a second input of said NAND gate.

5. The apparatus according to claim 4, further comprising means for inverting an output signal of said resonator interposed between said resonator output and a second input of said RS flip-flop.

6. The apparatus according to claim 1, wherein said auxiliary inpt means comprises means coupled to said output signal generating means for inhibiting only a single pulse of the divided resonator output signal during the period of each pulse of said generating means output signal.

7. The apparatus according to claim 1, wherein:

said frequency divider comprises a chain of dividing stages;

said auxiliary input means comprises intermediary circuit means coupled in series in said divider chain for supplying to succeeding divider stages in said chain a mean number of pulses different from the mean number of pulses received at its input, the difference between said mean numbers of pulses corresponding to a number stored in said memory; and i said feedback, means comprises a control circuit having one input coupled to at least one output of one stage of said dividing chain, a second input coupled to said output signal generating means, and an output coupled'to an input of said intermediary circuit means.

8. The apparatus according to claim 7, further comprising a time display member coupled to an intermediate output of said dividing chain.

9. The apparatus according to claim 7, in which the frequency of the resonator is greater than a nominal frequency corresponding to the minimum division ratio of the divider, said intermediary circuit being a transmission stage comprising means for making a single division by two when a control pulse is applied thereto.

10. The apparatus according to claim 7, in which the intermediary circuit is a pulse adder.

1 l. The apparatus according to claim 1, wherein said comparing means comprises first gate means for gating the intermediate outputs of said divider with the stored data outputs from said memory means and said signal generating means comprises means for generating a first logic signal having a duration which is determined by the coded data stored in said memory means; suppressor means coupled to the output of said signal generating means for suppressing all outputs from said first gate means other than said first logic signal during a preset period; and said feedback means comprising further gate means for gating the output of said suppressor means with a further'intermediate output of said frequency divider, the output of said further gate means being fed back to the auxiliary input means of said frequency divider to adjust the frequency division ratio thereof.

12. The apparatus according to claim 1 1, wherein the output of the last stage of said frequency divider is coupled to said suppressor means to determine the length of said preset period.

I 13. Timekeeper according to claim 1, in which the memory is an electrically alterable memory having at least one electrical input for the inscription of data.

14. Timekeeper according to claim 13, in which the memory is a volatile electronic memory.

15. Timekeeper according to claim 13, in which the memory is a memory with sequential inscription of data.

16. Timekeeper according to claim 15, in which the memory is a shift register.

17. Timekeeper according to claim 13, in which the memory is a permanent memory.

18. Timekeeper according to claim 13, in which the memory comprises a volatile memory coupled with a permanent memory.

19. Timekeeper according to claim 13, in which the memory comprises a permanent memory for large corrections to the division ratio and a volatile memory for small corrections to the division ratio.

20. Timekeeper according to claim 13, in which the memory comprises at :least one inscription input connected to a logical variable which controls time display means.

21. Timekeeper according to claim 2, comprising autonomous means coupled to and supplying the memory with frequency adjustment signals.

Claims

1. A self-adjusting timekeeping apparatus comprising: a resonator producing a pulsed output signal having a non-adjusted frequency; a frequency divider coupled to said resonator for dividing the frequency of the output singal of said resonator, said frequency divider including auxiliary input means for adjusting the frequency division ratio thereof; memory means for storing coded data in the form of a plurality of binary data bits; and frequency adjusting means coupling said memory means to said auxiliary input means for adjusting the frequency division ratio of said frequency divider as a function of the coded data stored in said memory means to thereby adjust the output frequency of said frequency divider, said frequency adjusting means including means for comparing the binary coded data bits stored in said memory means with a corresponding plurality of data bits produced at intermediate outputs of said divider, means coupled to said comparing means for generating an output signal when at least one set of compared memory and divider data bits are in coincidence, said output signal comprising a plurality of pulses the number of which is determined by said binary coded data bits stored in said memory means, and means for feeding said output signal back to said auxiliary input means for adjusting the output frequency of said divider.

2. The apparatus according to claim 1, wherein said comparing means comprises: a plurality of EXCLUSIVE OR gates having first inputs coupled to corresponding outputs of said memory means and second inputs coupled to corresponding ones of said intermediate frequency divider outputs; and said output signal generating means comprises an AND gate having a plurality of inputs coupled to respective outputs of said EXCLUSIVE OR gates, the output of said AND gate being coupled to said auxiliary input means by said feedback means.

3. The apparatus according to claim 2, wherein said auxiliary input means includes means to reset said frequency divider to zero as a function of an output signal produced by said AND gate.

4. The apparatus according to claim 1, wherein: said auxiliary input means comprises a NAND gate having a first input coupled to the output of said resonator and an output coupled to an input of said frequency divider; and said comparing means comprises a plurality of AND gates having first inputs coupled to corresponding outputs of said memory means and second inputs coupled to corresponding ones of said frequency divider intermediate outputs. said output signal generating means comprising and OR gate having a plurality of inputs coupled to respective outputs of said AND gates, and said feedback means comprises an RS flip-flop having an input coupled to an output of said OR gate and an output coupled to a second input of said NAND gate.

7. The apparatus according to claim 1, wherein: said frequency divider comprises a chain of dividing stages; said auxiliary input means comprises intermediary circuit means coupled in series in said divider chain for supplying to succeeding divider stages in said chain a mean number of pulses different from the mean number of pulses received at its input, the difference between said mean numbers of pulses corresponding to a number stored in said memory; and said feedback, means comprises a control circuit having one input coupled to at least one output of one stage of said dividing chain, a second input coupled to said output signal generating means, and an output coupled to an input of said intermediary circuit means.

11. The apparatus according to claim 1, wherein said comparing means comprises first gate means for gating the intermediate outputs of said divider with the stored data outputs from said memory means and said signal generating means comprises means for generating a first logic signal having a duration which is determined by the coded data stored in said memory means; suppressor means coupled to the output of said signal generating means for suppressing all outputs from said first gate means other than said first logic signal during a preset period; and said feedback means comprising further gate means for gating the output of said suppressor means with a further intermediate output of said frequency divider, the output of said further gate means being fed back to the auxiliary input means of said frequency divider to adjust the frequency division ratio thereof.

12. The apparatus according to claim 11, wherein the output Of the last stage of said frequency divider is coupled to said suppressor means to determine the length of said preset period.

13. Timekeeper according to claim 1, in which the memory is an electrically alterable memory having at least one electrical input for the inscription of data.

16. Timekeeper according to claim 15, in which the memory is a shift register.

20. Timekeeper according to claim 13, in which the memory comprises at least one inscription input connected to a logical variable which controls time display means.