US3812669A

US3812669A - Electronic timepiece

Info

Publication number: US3812669A
Application number: US00246533A
Authority: US
Inventors: F Wiget
Original assignee: Ebauches SA
Current assignee: ETS SA A SWISS CORP
Priority date: 1971-04-22
Filing date: 1972-04-24
Publication date: 1974-05-28
Anticipated expiration: 1991-05-28
Also published as: DE2219493B2; IT952693B; JPS5625636B1; FR2133872A1; DE2219493C3; CH540520A; DE2219493A1; GB1370564A; FR2133872B1; CH585271A4

Abstract

In an electronic timepiece in which a piezoelectric oscillator acts as a time base and controls a display device through a frequency division chain, the scale of division in the chain is adjustable for regulating the timepiece. A digital comparator compares the logic state of a binary reference with that of specific stages of the division chain, the comparator being alternately blocked during a natural period of the division chain and unblocked during the ensuing period. That ensuing period is cut short and the specific stages of the division chain are reset when there is coincidence between the logic states of the specific stages and the reference.

Description

United States Patent Wiget May 28, 1974 l l ELECTRONIC TIMEPIECE Primar ExaminerRichard B. Wilkinson 7 1 F d w t h't 1, Y l 51 Inventor x ggg Neuc d 3 Assistant Examiner-Edith Simmons lackmon n 5' or anriliei t krsrifiayis [73] Assignee: Ebauches S.A., Neuchatel,

Switzerland [5 7] ABSTRACT 22 Fil Apt 24, 1972 In an electronic timepiece in which a piezoelectric oscillator acts as a time base and controls a display delzl] PP N05 6 5 ,37 vice through a frequency division chain, the scale of division in the chain is adjustable for regulating the [30] Apphcamn Pnomy Data timepiece. A digital comparator compares the logic Apr. 22, 1971 Switzerland ..5852/71 state of a binary reference with that of specificstages of the division chain, the comparator being alternately [52] US. Cl. 58/23 R, 328/48 blocked during a natural period of the division chain [51] Int. Cl G04c 3/00 and unblocked during the ensuing period. That ensu- [58] Field of Search 58/23, 23 R, 23 A, 24 R, ing period is cut short and the specific stages of the 58/50 R; 307/225; 321/6l; 328/48, 49; 318/60 division chain are reset when there is coincidence be- I tween the logic states of the specific stages and the [56] References Cited reference.

UNITED STATES PATENTS 6 Claims, 3 Drawing Figures 3,230,383 l/l966 Mac Arthur 235/92 T 3,541,779 1l/l970 Langley 58/50 R 3,581,066 5/197] Maure 328/48 X g M/Vfl/ 0 //0 //0 #0 [m #0 #0 #0 [f0 /V /V*/ 1W2 MAI-l MW AM A/ 056/244 rap 1 r I 42 4144 411 L l 5' 0/6/ '42 cou /124709 m ni/f5 J 2 f4 4/ away em m/czja/a/mz PATENTEI] MAY 28 I974 SHEET 1 BF 3 1 ELECTRONIC TIMEPIECE FIELD OF THE'INVENTION This invention relates to electronic timepieces and to timing arrangements or movements of electronic timepieces.

An electronic timepiece movement generally comprises:

a. an oscillator the resonator of which is a piezoelectric crystal of a well-defined form such as a rod, a turning fork, or a plate or lenticular body, the oscillation of the resonator being maintained by a suitable electronic circuit at a frequency which generally'lies between a few KH and a few MH b. a frequency divider which divides the frequency of the oscillator by a constant factor so as to obtain a lower-order frequency,

c. a frequency integrator which integrates this low frequency so as to'produce a time scale and which is constituted for example by a synchronous or step-bystep motor which drives a train carrying the conventional hands or by an electronic counter'with a'digital time display, and

d. an electrical power source which supplies the items mentioned above.

The accuracy of the timepiece is identical with that of the oscillator, or, expressed'more precisely, with that v of the frequency-determining resonator of the oscillator. In industrial manufacture it is impossible to obtain in an economic'manner piezoelectric cystals with a tolerance less than a few units of l' 'relative to the frequency, this corresponding to accurate timekeeping to STATEMENT OF PRIOR ART When great accuracy is required, it has therefore been necessary to provide, for regulating the frequency of the oscillator. driving means causing the frequency to depart to a greater or'lesser extent from the natural frequency of the resonator. It is thus possible to fabricate an accurate oscillator and to re-establish the accuracy (within certain limits) when it deteriorates. To this end, a variable capacitor called a trimmer is mounted, for example, in series with a crystal resonator, the trimmer making it possible to regulate the oscillator frequency.

This well-known method, quite commonly adopted, introduces considerable penalties. Firstly, by artificially driving the oscillator frequency far from the natural frequency of the resonator the stability characteristics of the oscillator are impaired, the effect increasing with the frequency difference (which provides the required correction). The chronometric performance of the arrangement tends therefore to be seriously compromised. Secondly, the employment ofa trimmer capacitor prevents the obtaining, at one and the same time, of a wide range of correction as well as great accuracy. Thirdly, when developing an electronic wrist-watch of small size, the design of the trimmer capacitor poses numerous problems, both from the point of view of manufacture and from the technical point of view. This trimmer is in fact an expensive, bulky, delicate and scarcely viable part.

SUMMARY OF THE INVENTION The invention avoids these various drawbacks by proceeding in quite another manner to regulate the movement of the timepiece.

In the device according to the invention, (a) the frequency of the oscillator is identical with that of the resv onator, which oscillates at its natural frequency so that its oscillations are not perturbed in any way, and (b) the scale of division in the electronic divider is adjusted so as to obtain, while proceeding from the arbitrary frequency of the oscillator, a time scale possessing the required accuracy. For example, if the scale of division of the divider is of the order of 10 the accuracy of the time scale may be adjusted to approximately 10", that is, to less than 0.1 second a day, this being over a range as wide as may be desired.

The present invention therefore provides an electronic timepiece movement which comprises a piezoelectric oscillator'which acts as the time base, a frequency-division chain and a display device controlled at least indirectly by the output signal from the said division chain, characterised by means which make it possible to adjust the scale of division of the said chain within certain limits, the said means being constituted by:

a. a digital comparator intended to compare the logic state of a binary reference of M bits with that of M stages in the said division chain,

b. a device which makes it possible alternately to block the said comparator during a natural period of the division chain, and to unblock it during the ensuing period, and

c. a circuit which cuts short the said ensuing period from the instant when there is coincidence between the logic state of the said reference and that of the said M stages, the said M stages of the chain being reset to zero.

An embodiment of the invention will now be described by way of example with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an electronic timepiece embodying the invention,

FIG. 2 is a diagram of one possible form of the digital comparator and of the binary reference, and

FIG. 3 is a diagram of one possible form of a monostable multivibrator which indicates the rate of the electrical signals.

F,,, the frequency of the oscillator shown in FIG. 1, is divided by a division chain made up of N+M+P flipflops designated FFD. The scale of division of this chain is A 2**' and the natural period of the chain is T 2 -F The last flip-flop in this chain controls a monostable multivibrator, MONO l, which on the one hand operates the time display device H, and on the other hand operates the CLEAR" input of a controlling flip-flop FFC.

The outputs of the division-chain flip-flops with the superscripts N+l to N+M are connected to the inputs A, to A of a digital comparator of M bits. The M 0utputs of a binary reference of M bits are connected to the inputs B to B of the digital comparator of M bits.

The mode of operation of this comparator is as follows: I

a. if the blocking input, BLO, of the comparator is at a logic level 1, the comparator is blocked and its output S remains permanently at a logic level zero.

b. If the contents of the stages N+l to N+M of the division chain are first of all zero, and subsequently increase regularly, and if the blocking input, BLO, is at a logic level zero, the output of the comparator, which is initially equal to zero, passes over to the logic level 1 at the moment that there is a coincidence between the binary number K contained in the binary reference and the binary number contained in stages N-l-l to N+M of the division chain. The contents of these stages are therefore equal to K.

A description will now be provided of the operation of the system. Let us consider the instant at which the monostable multivibrator MONO 1 has just emitted its pulse on the one hand to the display system, and on the other hand to thecontrolling flip-flop. The latter, operated by its CLEAR" input, has flipped over, and its output has altered to the zero state. The digital comparator is thus unblocked. The chain of division flipflops is in the zero state, and the natural period of division starts. Immediately, however, the contents of the FFDs, N l to N+ M, attain the value K as stored in the binary reference, the digital comparator will emit a logic-level signal to the set input of the controlling flip-flop. The latter will flip over, and its output Q will alter to the state '1 The comparator will be once more blocked, and the multivibrator MONO 2 will emit a pulse which will reduce the FFDs N+1 to N+M to'Zeroqlt can be shown that the assembly ofFFDs will then once more be at' zero. The entirety of these procedures will have taken up a time T,,, an abbreviated period which has the value T 2- K- F...

A new natural period ofcounting will commence immediately and will continue until its termination, the comparator then being blocked. At the end of this natural period, the monostable MONO I will emit its pulse and the cycle will be reproduced in identical form.

It can be shown that in these conditions the real period T, of the system is equal to the sum of the abridged period T,, and of the natural period T,,. It may be written thus:

This means that it becomes possible to manufacture an electronic timepiece regulatable to that is, to about 0.1 of a second a day, with an oscillator the resonator of which will be manufactured to an accuracy of 10', i.e. .1 percent, a result that is impossible to achieve by methods of regulation based on the use of trimmers.

FIG. 2 is a diagram of a possible form of a comparator and of a binary reference. The arrangement is designed for 4 bits (M= 4) and K= 6 to explain the working more clearly. Use is made of NOR gates in positive logic. It will be noted that. in this particular case. the logic reference has to pass the complementary value of K to the comparator. The logic reference is taken in 10 this simple example to be constituted by switches.

FIG. 3 shows a possible form of a monostable multivibrator such as that designated MONO l or MONO 2 in FIG. 2. It is arrived at by the use of a type-D flip-flop (tapped off at two points from the division chain) and of a NOR gate. The form of the signals at various points on the circuit is set out beneath the circuit diagram.

1 claim:

1. An electronic timepiece movement comprising: a piezoelectric oscillator acting as a time base, a frequency-division chain, a display devicecontrolled at least indirectly by the output signal of the frequency-division chain, and means to adjust within certain limits the scale of division of the frequency-division chain and constituted by:

a. a digital comparator for comparing the logic state of a binary reference of M bits with that of M stages of the frequency-division chain, a b. a device for alternately blocking the comparator during a natural period of the frequency-division chain and unblocking the comparator during the ensuing period, and I c. a circuit which cuts short .the ensuing period from the instant when there is coincidence between the logic state of thereference and that of the M stages, the M stages of the chain being reset to zero, and the binary reference being constituted by a set of M switches which supply logic-level signals 0 or 1 to the inputs of the digital comparator.

2. A movement according to claim 1, comprising a flip-flop which controls the blocking input to the comparator, the flip-flop being'itself controlled alternately 40 by the comparator output and the division chain output.

3. A movement according to claim 2 wherein the output of the flip flop is connected through the agency of a monostable multivibrator to the reset-to-zero inputs of a certain number of stages of the division chain.

4. In an electronic timepiece movement, the combination of: a piezoelectric oscillator functioning as a time base, a frequency-division chain, a display device controlled indirectly by the output signal of the frequency-division chain, and means to adjust within certain limits the scale of division of the frequency-chain constituted by:

a. a digital comparator for comparing the logic state of a binary reference of M bits with that of M stages of the frequency division chain,

b. a device for alternately blocking the comparator during a natural period of the frequency-division chain and for unblocking the comparator during the ensuing period, and

c. a circuit for cutting short the ensuing period from the instant when there is coincidence between the logic state of the binary reference and that of the M stages, the M stages of the frequency-division chain being reset to zero.

5. In the movement according to claim 4, wherein the binary reference is constituted by an electronic mem- 5 ory.

6. in the movement according to claim 5, wherein the electronic memory consists' of a shift register.

Claims

1. An electronic timepiece movement comprising: a piezoelectric oscillator acting as a time base, a frequency-division chain, a display device controlled at least indirectly by the output signal of the frequency-division chain, and means to adjust within certain limits the scale of division of the frequencydivision chain and constituted by: a. a digital comparator for comparing the logic state of a binary reference of M bits with that of M stages of the frequency-division chain, b. a device for alternately blocking the comparator during a natural period of the frequency-division chain and unblocking the comparator during the ensuing period, and c. a circuit which cuts short the ensuing period from the instant when there is coincidence between the logic state of the reference and that of the M stages, the M stages of the chain being reset to zero, and the binary reference being constituted by a set of M switches which supply logic-level signals 0 or 1 to the inputs of the digital comparator.

2. A movement according to claim 1, comprising a flip-flop which controls the blocking input to the comparator, the flip-flop being itself controlled alternately by the comparator output and the division chain output.

4. In an electronic timepiece movement, the combination of: a piezoelectric oscillator functioning as a time base, a frequency-division chain, a display device controlled indirectly by the output signal of the frequency-division chain, and means to adjust within certain limits the scale of division of the frequency-chain constituted by: a. a digital comparator for comparing the logic state of a binary reference of M bits with that of M stages of the frequency - division chain, b. a device for alternately blocking the comparator during a natural period of the frequency-division chain and for unblocking the comparator during the ensuing period, and c. a circuit for cutting short the ensuing period from the instant when there is coincidence between the logic state of the binary reference and that of the M stages, the M stages of the frequency-division chain being reset to zero.

5. In the movement according to claim 4, wherein the binary reference is constituted by an electronic memory.

6. In the movement according to claim 5, wherein the electronic memory consists of a shift register.