JPS6046389B2 - electronic clock - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a computer-equipped electronic timepiece, and more particularly to an adjustment device as a timepiece.

For example, when using a crystal oscillator as an oscillator for an electronic watch,
Due to manufacturing variations in crystal oscillators, a trimmer was attached to the oscillator when assembling the watch.

The oscillation frequency is adjusted to a constant reference frequency by adjusting the capacitor. However, crystal oscillators are affected by temperature changes and aging, and their oscillation frequency fluctuates.
To adjust this, an oscillation frequency stabilization circuit is used in the oscillator.

Alternatively, it is possible to incorporate a temperature compensation circuit, but these are all analog and have the disadvantage that they increase the size of the device and are particularly difficult to implement in wristwatches. In view of the various characteristics of the electronic timepiece with a calculator, the present invention allows the rate correction amount to be entered directly from the keyboard as a numerical value, and digitally processes it to correct the rate.
The purpose is to eliminate the above drawbacks.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of the main parts of an electronic clock/meter showing an embodiment of the present invention.

The oscillation circuit 1 includes a crystal oscillator and outputs a reference signal of 32,768 KHz.

The frequency dividing circuit 2 includes a large number of T-type flip-flops F2, ~F.

n, and a reference signal f. Divide up to 1H2. In this frequency dividing circuit 2, an or gate OR is inserted between the lower flip-flops F22 and F23 of the second and third stages, and the output signal f of the second stage flip-flop FF22. /4
In addition, a delay correction signal Pd and a lead correction signal Pf, which will be described later, are also input to the T terminal of the third stage flip-flop FF2a. The frequency-divided 1H2 signal s is sequentially input to a second counter 3, a minute counter 4, an hour counter 5, a day counter 6, etc., and the respective time information is countered. Displays the time. The second counter 3 consists of a 1st digit second counter and a ■ digit counter, respectively.
It performs decimal and hexadecimal operations, and the second counter 3 performs six-value operation.

The logical values of each BCD output of the second counter 3 are as shown in Tables 1 and 2. These BCD outputs are input to the correction reference signal generation decoder 7 and the aforementioned seconds display decoder (not shown). The correction reference signal generation decoder 7 which receives the BCD output of the second counter 3 as an input has the content of the second counter 3 as R6! , Rl2J, rl4yo, Rl8
Yo, R24yo, R28yo, R3OJ, r36! ,142
Signals D6 and Dl each have a logical value of 1 when 148, 148, and R59. , . . . Output D59. Outputs D6, Dl2, . . . of the decoder 7 for generating correction reference signals
The correction reference signal generation circuit 8 which receives D59 as an input is connected to each D59.
6, D6+Dl29D6+Dl2+Dl49D6+Dl
2+Dl4+Dl89D6+Dl2+Dl4+Dl8+
D24+D28+D3O+D36+D42+D48+D
Correcting reference signals Fl, F2, F3, based on the logic of 59.
...Outputs Fll. The outputs Fl, F2, F3, . On the other hand, the rate correction amount you want to correct, for example, 0 if the clock tends to advance by 1 circle per month.
-10J or 1+2 if the clock is 20 seconds behind each month
When "0" is input from the keyboard to the key input unit 10, the key input information output from the key input unit 10 is read into the numeric register 11 using the clock signal φ.

The switch 12 is used to read the contents of the numeric register 11 into the buffer register 13. When the switch 12 is pressed and turned on, voltage V+ is applied to the timing signal generation circuit 14 for reading the numeric value, and the logical value is 1. Enter.

After key-inputting the rate correction amount, when the switch 12 is pressed and turned on by external operation, the timing signal generation circuit 14 for reading the numerical value outputs a word signal, and the input information read into the number register 11 is The contents at a predetermined location are read into the buffer register 13.

The output signals A, B, C, D, and E, F, G of the buffer register 13 are the K1 outputs of the 1st and 10th digits of the key-input numerical value, respectively, and their logical values are the same as those in Table 1. It's the same. Further, the output signal H of the buffer register 13 is a signal representing a sign, and takes a logic value of 0 when it is positive, and takes a logic value of 1 when it is negative. The output of the buffer register 13 is input to a numerical value detection gate circuit 15.

That is, this numerical value detection gate circuit 15 detects 3 to 7, 8 to 12, and 13 to 1 from the memory KD output of the buffer register 13.
8, 19-23, 24-28, 29-34, 35-39
, 40-44, 45-49, 50-55, 56-60 according to the logic shown in Table 3 to obtain number/value detection signals Cl, C2.
,...CLL is generated. That is, in this embodiment, the rate correction amount that can be entered by key is meaningless unless it is within 6 [phases]/month. Outputs Fl, F2, F3, . . . Fll of the correction reference signal generation circuit and outputs Cl, C2, C3, . . . of the numerical value detection gate circuit 15.
. . . Rate correction amount selection gate circuit 9 that receives CLL as input.
In, the correction reference signals Fl, F2,...Fll
and numerical detection signals Cl, C2, .
That is, when the numerical value detection signal C1 has a logical value of 1, the output P of the rate correction amount selection gate circuit 18 is ANDed with F1 to become a 1/60 Hz signal.

When the detection signal C2 has a logical value of 1, the output P is ANDed with F2 and becomes a 2/60Hz signal. Similarly, when the numerical value detection signals C3 and Cll each have a logical value of 1, the output P becomes a signal of 3/60 Hz, 4/60 Hz, and 11/60 Hz.

The output P of the rate correction amount selection gate circuit 9 is sent to a delay signal generation circuit 16 or an advance signal generation circuit 17 via an AND gate AND1 or an AND gate AND2, respectively.
is input.

Further, the sign discrimination signal H is inputted to the other side of the AND gate AND1, and the sign discrimination signal H is inverted by the inverter INV2 and inputted to the other side of the AND gate AND2. That is, in key input, when a positive value is input, the output P of the rate correction amount selection gate circuit 9 is inputted to the advance correction signal generation circuit 17, and conversely, when a negative value is input, the output P of the rate correction amount selection gate circuit 9 is input to the delay correction signal generation circuit. 16. Details of the delay correction signal generation circuit 16 and correction signal generation circuit 17 are shown in FIGS. 2 and 3, respectively. In the delay correction signal generation circuit 16 of FIG. 2, the logical product P- of the output signal P of the rate correction amount selection gate circuit 9 and the sign discrimination signal H
H is input to the D terminal of the D-type flip-flop FFl6-1, and the Q-terminal output of this D-type flip-flop FFl6-1 is input to the D terminal of the next stage D-type flip-flop FFl6-2. These D-type flip-flops Fl6-
1. The T terminal of FF16-2 has a clock pulse,
Reference signal F of oscillator 1. The inverted signal F. , the lower F2 of the first and second stage T-type flip-flops of the frequency divider circuit 2
l, output signal F of FF22. The output of a NAND gate NANDl6 which receives inputs /2 and f0/4 is input. AND gate ANDl6 is a D-type flip-flop FFl6-
1 and the Q terminal and η terminal outputs of FF, 6-2 are input, and the output is used as the delay correction signal Pd to the second terminal of the frequency dividing circuit 2.
stage, third stage T-type flip-flop FF2. , FF are input to the OR gate 0R inserted between them. In the advance correction signal generating circuit 17 of FIG. 3, the logical product p-yes of the output signal P of the rate correction amount selection gate circuit 9 and the inverted signal presence of the sign discrimination signal H is determined by the D-type flip-flop under Fl7-1.
, and its Q terminal output is input to the D terminal of the next stage D-type flip-flop FFl7-2.

Below these D type flip-flops Fl7-1, FF17-
The output signal F of the lower D-type flip-flop F22 in the second stage of the frequency divider circuit 2 is supplied to the T terminal of the frequency divider circuit 2 as a clock pulse.
/4 is input. AND gate ANDl7-1 is D
Input the Q terminal output and n terminal output of type flip-flops FFl7-1 and FFl7-2, and
NDl7-2 is the output of the AND gate ANDl7-1, and output signal F via the inverter INVl7-1 and INl7-2. /2, f0/4 inverted signal F. /2,f0
/4 and the reference signal F of the oscillation circuit 1. is the input. The output of the AND gate ANDl7・-2 is the advance correction signal "signal P"
It is input to the OR gate 0R as f. FIG. 4 is a block diagram showing the entire structure of the electronic timepiece with calculator according to the embodiment of the present invention. Oscillator circuit 1, frequency divider circuit 2, key input section 10
, replacement register 11, and buffer register 13 are as explained above, and corresponding to the second counter 3, minute counter 5, hour counter 6, and day counter 7 in FIG. Decoder 7 for generating a correction reference signal and circuit 8 for generating a correction reference signal in FIG.
, the rate correction amount selection gate circuit 9, the numerical value detection gate circuit 15, the delay correction signal generation circuit 16, the advance correction signal generation circuit 17, etc., are all combined into the speed control circuit 1.
It is shown as 9. As a calculator, input information from a key input unit 10 having keys for inputting numerical signals and function signals is inputted to an arithmetic unit 21 via a number register 11 and a switch 20. The arithmetic unit 21 processes the numerical information introduced from the input unit according to an arithmetic processing instruction from the input unit, and outputs the final result to the computer display register 22. The display is displayed on the display section 2 via the switch 23.
It will be held in 4. key input section 10, replacement register 11,
The lock signal and various timing signals necessary for the arithmetic unit 21 and the computer display register 22 are preferably supplied from the oscillation circuit 1, the frequency dividing circuit 2, etc., although not shown. Function switching is performed by operating switches 20 and 23 from the outside.

When the electronic clock with calculator is displaying the time, the numeric register 11 is connected to the buffer register 13 via the switch 20, and the time display register 25 is connected to the buffer register 13 via the switch 20.
It is connected to the display unit 24 via 3.

At this time, directly enter the amount of rate you want to correct using the keyboard, for example, 1-5J for a watch that tends to gain 5 seconds per month, or 1+10J for a watch that tends to lose 5 seconds per month. Enter numerical values from . Then, when the switch 12 shown in FIG. 1 is pressed and turned on, the information input from the keyboard is stored in the buffer register 13, and the content is detected by the numerical value detection gate circuit 15, and the corresponding numerical value is detected. Signal Q, C2,...
・Output a logic value of 1 from CLL. For example, in the case of R5J as described above, a numerical value of 3 to 7 is detected, and the numerical value detection signal C1 outputs a logical value of 1. Then, in the rate correction amount selection gate circuit 9. A correction reference signal F1 is output based on this numerical value detection signal C1. 1 on the keyboard
When a negative sign is input, the sign discrimination signal H becomes a logical value of 1. The output signal F1 of the rate correction amount selection gate circuit 9 is transmitted through an AND gate ANDl. The signal is input to the delay correction signal generation circuit 16. FIG. 5 is a time chart for explaining the operation of the delay correction signal generation circuit 16. The NAND gate NANDl6 is the reference signal F of the oscillation circuit 1. The first and second stage T-type flip-flops FF2l and FF2 of the inverted signal frequency divider circuit 2. output signal F. /
2. Input f0/4, then ・ (FO/2) ・(FO
/4). D type flip-flop FFl6-
When the logic value of the D terminal of 1 becomes 1, the NAND gate NAN
The first rising edge of the output of Dl6 causes its Q terminal to output a logic value of 1. (Time chart Ql6-1). At the next rising edge, the Q terminal of the D-type flip-flop FFl6-2 in the next stage also outputs a logic value of 1 (time chart Ql6-2
).

The AND gate ANDl6 connects the Q terminal output of these D-type flip-flops FFl6-1 and FFl6-2 and the Q
The terminal outputs the logic of Ql6-1 and Ql6-2 and outputs it as a delay correction signal Pd. Delay correction signal P
d is output 1 signal F. It has a pulse width of one period of /4,
and output signal F. In order to reach the logic value 1 between two consecutive logic values 1 of /4, the OR gate 0R takes the logic of Pd+FO/4, and as is clear from the time chart, the output signal F. /4 erases one logic value 1 pulse. For example, as mentioned above, if the correction reference signal F1 is input to the delayed correction signal generation circuit 16, the correction reference signal F1 will generate one pulse for every six mackerel, so it will generate one pulse per minute. Output signal F.

One logic value 1 pulse of /4 will be erased.
Output signal F. 4/326 seconds delay when one logical value of /4 1 pulse is erased.Therefore, if one pulse per minute is input to the delay correction signal generation circuit 19, 60 pulses per day
x60 x 24 x (1/60) = 14 logical value 1 pulses are canceled and delayed by (4/32768) x 1440 = 0.1 seconds. In other words, if one month is calculated as 30 days, the delay will be 0.176 x 30 = 5.28 seconds per month. In the numerical value detection gate circuit 15, 8 to 12
When the numerical value detection signal C2 becomes a logical value 1 after detecting , the correction reference signal F2 is input to the delay correction signal generation circuit 16, and the output signal F is input.

Since one pulse with a logical value of /4 is canceled twice as much as the correction reference signal F1, a delay of 10.5 times per month can be achieved. Similarly, in the numerical value detection gate circuit 15, 13-28, 19-23, 24-28, 29-3, respectively.
4, 35-39, 40-44, 45-49, 50-55
, 15.8 per month if 56-6α is detected.
4 seconds, 21.0 seconds, 26.37 seconds, 31.6 seconds 2, 36
．． (company) seconds, 42.18 seconds, 47.46 seconds, 52.74
Seconds, 58. It can be delayed by a few seconds. Conversely, when 1 plus is input from the keyboard, the sign discrimination signal H takes a logical value of 0, so the output signal P of the rate correction amount selection gate circuit 9 advances to the correction signal generation circuit 17 via the AND gate AND2. is input.

The operation of the advance correction signal generation circuit 17 will be explained with reference to the time chart of FIG.

The D terminal of the D-type flip-flop FFl7-1 has a logic value of 1.
When it becomes, the output signal F. At the first rise of /4, the Q terminal output outputs a logic value of 1 (time chart Ql7-1).
), at the next rising edge, the Q terminal output of the D-type flip-flop FFl7-2 outputs a logical value of 1 (time chart Ql
7-2). AND gate ANDl7-1 is Ql7-1
・Take the logic of Ql7-2 and use the AND gate ANDl7-2
is input. AND gate ANDl7-2 further Ql
7-13Q17-2IG71 parody 7Σ0f0 logic is taken as reference signal F. The output signal F has a pulse width corresponding to 1/2 of the period of the output signal F. It outputs an advance correction signal Pf which becomes a logical value 1 while /4 becomes a logical value 0. F by OR gate 0R. If we take the logic of /4+Pf, the output signal F. /4 plus one logic value 1 pulse. This is performed every time the signal p-present inputted to the correction signal generation circuit 17 reaches a logical value of 1, so the numerical value detection gate circuit 15
In, 3-7, 8-12, 13-18, 19-23
, 24-28, 29-34, 35-39, 40-44,
If 45-49, 50-55, and 56-60 are detected, 5.28 seconds and 10.5 people per power month, respectively.
5.84 seconds, 21. (4) seconds, 28.37 seconds, 31.6
5 seconds, 36. (1) seconds, 42. Sec., 47. Taku second, 52
．． It is possible to advance the time by 74 seconds or 58.02 seconds. In addition,
Correction signals Fl, F2,...Fll are second counter 3
In order to obtain the ℃D output by inputting it to the correction reference signal generation decoder 7, its frequency is exactly 1/60Hz, 2
/60Hz, ... Although it is not 11/60Hz, the error can be almost ignored.

Table 4 shows the rate correction of this watch.

As is clear from this, it is possible to easily bring the rate within the range of lag/advance of 4 seconds/month by inputting the desired value from the keyboard. As described above, in this embodiment, input numerical values are classified into several ranges, but by arbitrarily setting the numerical value detection range, the correction reference signal, and the frequency division stage controlled by the correction reference signal, It is also possible to obtain other preferred damping devices. As described above, according to the present invention, the adjustment device is digitalized and integrated into one clock circuit along with other clock circuits. It can be built into an I-chip, etc., and is useful for electronic wristwatches with calculators that have limited mounting area.
It is possible to provide a convenient speed adjustment device that can correct the rate by a simple method of directly inputting a numerical value to be corrected and a code for commanding delay/advance from the keyboard.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the main parts of an electronic timepiece with a calculator showing one embodiment of the present invention, FIG. 2 is a block diagram showing the main parts of FIG. 1 in more detail, and FIG. 4 is a block diagram showing the entire electronic timepiece with calculator according to the embodiment of FIG. 1, FIG. 5 is a time chart explaining the operation of FIG. 2, and FIG. FIG. 6 is a time chart explaining the operation of FIG. 3. 1... Oscillation circuit, 2... Frequency dividing circuit, 3
. . . seconds counter, 7 . . . Decoder for generating a reference signal for correction, 8 . . . Reference signal generation circuit for correction, 9 . . . Rate correction amount selection gate. circuit, 1
0...Key input section, 11...Placement register, 13...Buffer register, 15...
... Numerical value detection gate circuit, 16 ... Delay correction signal generation circuit, 17 ... Advance correction signal generation circuit, 18 ... Time counter, 19 ... ...
Slow/slow control circuit, 21... Calculation section, 22...
...Display register for computer, 24...Display section,
25...Clock display register.

Claims (1)

[Claims] 1. Means for storing numerical values corresponding to rate correction amounts and codes for commanding delay correction and advance correction, means for deriving a plurality of correction reference signals from the low frequency stage of the clock circuit system, and the above storage means. means for selecting the correction reference signal based on a numerical value; means for generating a delay correction signal or an advance correction signal from the selected correction reference signal; means for correcting the rate by erasing one pulse of the high frequency stage of the clock circuit system by the delay correction signal and adding one pulse to the high frequency stage of the clock circuit system by the lead correction signal when correcting the lead. An electronic clock that is characterized by: