US3866186A - Logic circuit arrangement employing insulated gate field effect transistors - Google Patents

Logic circuit arrangement employing insulated gate field effect transistors Download PDF

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Publication number
US3866186A
US3866186A US358877A US35887773A US3866186A US 3866186 A US3866186 A US 3866186A US 358877 A US358877 A US 358877A US 35887773 A US35887773 A US 35887773A US 3866186 A US3866186 A US 3866186A
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Prior art keywords
transistors
read
transistor
supplied
memory
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US358877A
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English (en)
Inventor
Yasoji Suzuki
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Toshiba Corp
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Tokyo Shibaura Electric Co Ltd
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Priority claimed from JP4766772A external-priority patent/JPS5332661B2/ja
Priority claimed from JP5242872A external-priority patent/JPS4917148A/ja
Priority claimed from JP5242772A external-priority patent/JPS5317022B2/ja
Priority to US358877A priority Critical patent/US3866186A/en
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to AU55663/73A priority patent/AU476907B2/en
Priority to GB2312473A priority patent/GB1414346A/en
Priority to CA172,348A priority patent/CA1016650A/en
Priority to CH701173A priority patent/CH567839A5/xx
Priority to DE19732324787 priority patent/DE2324787C3/de
Priority to FR7317690A priority patent/FR2184914B1/fr
Priority to US05/499,924 priority patent/US3943377A/en
Publication of US3866186A publication Critical patent/US3866186A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
    • H03K19/1772—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register with synchronous operation of at least one of the logical matrixes

Definitions

  • ABSTRACT A logic circuit arrangement consisting of insulated gate field effect transistors of opposite channel types wherein the drain electrode of a single first insulated gate field effect transistor of one channel type is connected to the drain electrode of at least one second insulated gate field effect transistor of the opposite channel type constituting a logic gate.
  • the gate electrode of second transistor is supplied with a data signal and the gate electrode of first transistor and the source electrode of second transistor are supplied with clock pulse signals bearing a complementary relationship with each other.
  • the source electrode of first transistor may receive a clock pulse signal supplied to the source electrode of second transistor or constant voltage; and an output signal from the logic circuit is delivered from the junction of the first and second transistors.
  • FIG. 1A SHEEI OlUF 11
  • An electronic computer has a considerable number of logic gates provided as the components of an integrated circuit. In this case, it is demanded that as many logic gates as possible be provided in a single integrated circuit. To this end, logic gates attaining the same function should each consist of as few semiconductor elements as possible.
  • Another object ofthe invention to provide a logic circuit arrangement including very few constituent elements and adapted for formation of an integrated circuit.
  • a logic circuit arrangement comprising: a single first insulated gate field effect transistor of one channel type having a first and a second electrode defining a conduction path therebetween and a gate electrode; a logic gate means including at least one second insulated gate field effect transistor of the opposite channel type having a first and a second electrode defining a conduction path therebetween and a gate electrode; means for connecting the second electrode of the first transistor and the second electrode of the second transistor, the junction of the first and second transistors being used to draw out an output signal; means for supplying the gate electrode of the first transistor and the first electrode of the second transistor with a first and a second clock pulse signal respectively which have a complemcntary relationship with each other; and means for supplying a data signal to the gate electrode of the second transistor.
  • this invention supplies cascade connected logic circuits with clock pulse signals whose pulse width progressively increases toward the terminal unit of the cascade series.
  • all the logic circuits are supplied with common clock pulses and inverters are disposed between the preceding and succeeding logic circuits.
  • the first transistors of the preceding and succeeding logic circuits are of opposite channel types and in consequence the second transistors of the circuits are similarly are of opposite channel types. All these logic circuits are supplied with common clock pulse signals.
  • FIG. 1A is a logic circuit according to an embodiment of this invention.
  • FIG. 1B is a modification of the logic circuit of FIG. 1A;
  • FIG. 1C represents the wave forms associated with the operation of the logic circuit of FIG. 1A;
  • FIG. 2 shows a logic circuit arrangement according to an embodiment of the invention capable of preventing any erroneous operation that might occur where the logic circuits of the invention are cascade connected;
  • FIG. 3A indicates the wave forms associated with the operation of the logic circuit of FIG. 2;
  • FIG. 3B is a wave form diagram illustrating the manner in which an erroneous operation is likely to occur where the cascade connected logic circuits of the invention are supplied with common clock pulses;
  • FIG. 4 shows a logic circuit arrangement according to another embodiment of the invention capable of eliminating any erroneous operation that might arise where the logic circuits of the invention are cascade connected;
  • FIG. 5 represents the wave forms associated with FIG. 4;
  • FIG. 6 indicates a logic circuit arrangement according to still another embodiment of the invention capable of preventing any erroneous operation that might take place the logic circuits of the invention are cascade connected;
  • FIG. 7 illustrates the wave forms associated with FIG. 6.
  • FIGS. 8, 9 and 10 present read only memory circuits utilizing logic circuits of the invention.
  • referential numeral 11 denotes an n-channel type first insulated gate field effect transistor constituting a load.
  • Referential numerals l2 and 13 represent p-channel type second insulated gate field effect transistors jointly constituting a logic gate 14.
  • the drain or second electrode of the n-channel type first transistor 11 is connected to that of one p-channel type second transistor 12 whose source or first electrode is connected to the drain electrode of the other second transistor I3.
  • the semiconductor substrate of the first transister 11 is connected to a power source of -E volts, and the semiconductor substrates of the second transistors 12 and 13 are grounded.
  • the gate and source electrodes of the first transistor 11 are supplied with first and second clock pulse signals CP and 6 bearing a complementary relationship with each other.
  • the source electrode of the second transistor 13 is supplied with the clock pulse signal CP.
  • the gate electrodes of the second transistors 12 and 13 jointly constituting the logic gate 14 are supplied with data signals A and B respectively.
  • An output signal is delivered from the junction of the first transistor 11 and the second transistor 12.
  • a notation CL represents an output capacitance.
  • the gate electrode of the n-channel type first transistor 11 is supplied with a voltage bearing a positive relationship with respect to the substrate, then the conduction path defined between the source and drain is rendered conducting to present a low impedance. Conversely where the gate electrode of the n-channel type first transistor 11 is supplied with a voltage having the same level as that impressed on the substrate, then the aforesaid conduction path becomes inoperative to display a high impedance.
  • the gate electrodes of the p-channel type second transistors 12 and 13 are supplied with a voltage having the same level as that impressed on the substrate, then the conductive paths of both transistors 12 and 13 are rendered nonconducting to present a high impedance, whereas, when the gate electrodes are supplied with a voltage bearing a negative relationship with respect to the substrate, then the conduction paths of the transistors 12 and 13 become conducting to indicate a low impedance.
  • FIG. 1C the operation of the logic circuit of FIG. 1A.
  • the clock pulses CP and C1 and data signals A and B have a voltage level of either E volts or 0 volt as shown in FIG. 1C.
  • the clock pulse signal CP has a voltage level of 0 volt and i consequence the complenetary clock pulse signal CP has a voltage level of -E volts
  • the first transistor 11 is rendered conducting, causing the output capacitance CL to be charged up to -E volts through the conduction path of the first transistor 11, regardless of whether the second transistors 12 and 13 become operative o r nonoperative.
  • the first transistor 11 is rendered nonconducting.
  • the voltage across the output capacitance CL varies with the condition of the second transistors 12 and 13.
  • either of the data signals has a voltage level of 0 volt.
  • the serially connected conduction paths of the second transistors 12 and 13 collectively present a high impedance. Accordingly, the output capacitance CL charged to E volts maintains this voltage level.
  • both data signals A and B have a voltage level of -E volts
  • the second transistors 12 and 13 are rendered conducting so that the output capacitance CL has its voltage level raised to 0 volt by being discharged through the conduction paths of the second transistors 12 and 13.
  • the capacitance CL is discharged, as shown in a dotted line in FIG. 1C, with a certain time constant due to resistance occurring in the second transistors 12 and 13 when they are rendered conducting.
  • the logic circuit of FIG. 1A functions as a NOR circuit (S A+B).
  • the logic circuit acts as a NAND circuit (-8 AB).
  • the logic circuit of this invention requires only one clock pulse transistor as shown in FIG. 1A. Following is the reason. Where the gate electrodes of the second transistors 12 and 13 are impressed with a voltage of -E volts, while the output capacitance CL is charged, namely, while the first transistor 11 remains conducting, then both second transistors 12 and 13 become operative. Since, however, the source electrodes of the first transistor 11 and the second transistor 13 are supplied with the same clock pulse signal fib-E volts), the potentials at both ends of a circuit path defined by the conduction paths of the first transistor 11 and the second transistors 12 and 13 are made equal, thereby preventing the passage of direct current through the circuit path. Through the conduction paths of the transistors 11, 12 and 13 only flow switching current or transient current. Therefore, the logic circuit of this invention prominently saves power consumption.
  • the foregoing description refers to the case where the clock pulse signal CF was supplied to the source electrodes of the first transistor 11 and the second transistor 13. However, it is not always necessary to supply the source electrode of the first transistor ll'with the clock pulse signal. As easily understood, connection of the source electrode to the power source of E volts will attain the same object.
  • the second transistors 12 and 13 constituting the logic gate 14 may, if required, be connected parallel. It is further possible to connect additional transistors in series with the second transistors 12 and 13 or to connected additional transistors parallel to serially connected transistors.
  • the logic gate 14 may be formed of a single transistor 12. In this case, the logic circuit of FIG. 1A acts as an inverter or NOT circuit (S A).
  • the load transistor may be replaced by a transistor of p-channel type and the second transistors 12 and 13 constituting the logic circuit 14 may be substituted by transistors of n-channel type as shown in FIG. 1B.
  • the parts of FIG. 3B the same as those of FIG. 1A are denoted by the same notations, description thereof being omitted.
  • the gate electrode of the f rst transistor 11 is supplied with the clock pulse signal CP and the source electrode of the second transistor 13 is supplied with the complementary clock pulse signal CP.
  • the source electrode of the first transistor 11 is grounded or supplied with a clock pulse signal CP.
  • the logic circuit of FIG. 1B acts as a NAND circuit in the case of the positive logic and as a NOR circuit in the case of the negative logic.
  • FIG. 2 represents a plurality of cascade connected logic circuits of this invention.
  • a logic circuit 1 is cascade connected to a logic circuit 3 and a logic circuit 2 to the logic circuit 3.
  • This logic circuit may be further cascade connected to the following logical circuit.
  • load transistors 11-1, 11-2 and 11-3 consist, as in FIG. 1A, a n-channel type transistors, and the logic gates 14-1, 14-2 and 14-3 are formed of three groups of two parallel connected p-channel type transistors 12-1, l3-1; 12-2, 13-2; and 12-3, 13-3.
  • the gate electrodes of the transistors 12-1 and 13-1 constituting the logic gate 14-1 are supplied with data signals A and B respectively.
  • the gate electrodes of the transistors 12-2 and 13-2 constituting the logic gate 14-2 are supplied with data signals C and D respectively.
  • the transistors 12-3 and l3-3 constituting the logic gate 14-3 are supplied with output signals S1 and S2 from the logic circuits 1 and 2 respectively.
  • the logic circuits 1, 2 and 3 act as NAND circuits and, in the case of the negative logic, act as NOR circuits.
  • FIG. 2 is characterized in that clock pulse signals CP2 and CP2 supplied to the second stage logic circuit 3 have a l a rger pulse width than clock pulse signals CPI and CPI supplied to the first stage logic circuits 1 and 2. This object resides in to prevent the later described erroneous operation which might take place in the logic circuit 3.
  • the capacitances C1, C2 and C3 indicated in FIG. 2 are output load capacitances each indicated by a total of the diffusion capacitance (PN junction capacitance) through the junction of the drain and substrate, wiring capacitance and the gate capacitance of the transistor of the succeeding logic circuit.
  • the insulated gate field effect transistors constituting the logic gates may be connected in series as occasion demands and have different channel widths and in consequence different values of mutual conductance gm. Accordingly, the time constant of discharge determined by the load capacitances C1, C2 and C3 and the conductance gm are likely to increase depending on the number and the connection of transistors used in the logic circuits.
  • time delays t1 and 12 in causing the capacitances Cl and C2 to be discharged to 0 volt after being charged to E volts.
  • the capacitances C1, C2 and C3 are all charged to E volts due to the load transistors 11-1, 11-2 and 11-3 being rendered conducting at the same time.
  • data signals A, B, C and D alike have a voltage level of E volts after the load transistors 11-1, 11-2 and 11-3 become inoperative, then the transistors 12-1, 13-1, 12-2 and 13-2 are jointly rendered conducting to give rise to the discharge of the capacitances C1 and C2.
  • the period in which the load transistor 11-3 of the succeeding logic circuit 3 is rendered conducting by clock pulse signals CP2 and CP2 is made longer than the conduction period of the load transistors 11-1 and 1l-2 of the preceding logic circuits 1 and 2.
  • the output capacitance C3 of the succeeding logic circuit 3 has a longer charging period to a required extent than the output capacitances Cl and C2 of the preceding logic circuits 1 and 2.
  • the capacitance C3 still continues to be charged, thereby preventing the output signal S3 from the succeeding logic circuit 3 from presenting a wrong voltage level due to the aforesaid premature discharge of the capacitance C3.
  • FIG. 4 represents a logic circuit arrangement according to another embodiment of the invention which can eliminate the above-mentioned drawbacks of the embodiment of FIG. 2.
  • a known first inverter means 20 consisting of an nchannel type transistor 21 and a p-channel type transistor 22.
  • a known second inverter means formed of an n-channel type transistor 24 and a p-channel type transistor 25.
  • the transistors 12-3 and 13-3 have the conduction paths connected in series.
  • the load transistors 11-1, 11-2 and 11-3 are jointly rendered conducting by clock pulse signals CP and CF, then the output capacitances C1, C2 and C3 are all charged to -E volts. Accordingly, output signals S1 and S2 from the first and second inverters 20 and 23 alike have 0 volt. Under this condition, the transistors 12-3 and 13-3 constituting the logic gate 3 arerendered nonconducting. Where the load transistors 1l-l and 11-2 are rendered nonconducting, then the capacitances C1 and C2 are discharged to 0 volt or kept at a voltage level of -E volts according as the transistors 12-1, 13-1, 12-2 and 13-2 are rendered conducting or nonconducting.
  • the capacitances C1 and C2 will be discharged. However, the capacitances Cl and C2 are not immediately brought to 0 volt due to the time constant of discharge. Since the transistors 21 and 24 remain nonconducting until the voltage levels of the capacitances Cl and C2 are changed from E volts to the gate threshold voltage level of the transistors 21 and 24, output signals 1 and g from the first and second inverter means 20 and 23 are kept at volt. Namely, even when the capacitances Cl and C2 begin to be discharged, the transistors 12-3 and 13-3 constituting the logic gate 14-3 are not immediately rendered conducting.
  • the source electrodes of the p-channel type transistors 22 and 25 constituting the first and second inverters 20 and 23 may be supplied with clock pulse signal CP, and the gate electrodes of the transistors with clock pulse signal (F, and the source electrodes of the n-channel type transistors 21 and 24 with clock pulse signal CP.
  • FIG. 6 presents still another embodiment of this invention which eliminates the necessity of using such inverters.
  • the load transistors 11-1 and l1-2 of the preceding logic circuits 1 and 2 are of n-channel type
  • the load transistor ll-3 of the succedding logic circuit 3 is of p-channel type and in consequence the transistors 12-3 and 13-3 constituting the logic gate 14-3 of the succeeding logic circuit 3 are of n-channel type.
  • the source electrode of the load transistor 11-3 of the succeeding logic circuit 3 is supplied with a clock pulse signal CP an l the gate electrode thereof with a clock pulse signal CP.
  • the transistors 12-3 and 13-3 constituting the succeeding logic gate 14-3 nonconducting until the voltages of the capacitances C1 and C2 reach the gate threshold voltages of the transistors 12-3 and 13-3, thereby maintaining the voltage level of the output signal 83 from the succeeding logic circuit 3 at 0 volt.
  • the transistors 12-3 and 13-3 constituting the succeeding logic gate 14-3 may be considered to have a function of acting as the inverter of FIG. 4.
  • the succeeding logic circuit of FIG. 6 do not present any erroneous operation even when it is supplied with common clock pulse signals CP and CF, FIG.
  • FIG. 7 indicates the wave forms associated with the embodiment of FIG. 6.
  • the aforementioned logic circuits of this invention are adapted for use with a read only memory.
  • FIGS. 8, 9 and 10 indicate read only memory devices ROMl and ROM2.
  • the ROMl device is a memory device for converting or decoding binary-coded decimal signals (A, A, B, E, C, C, D, I5) into decimal signals (0 to 9).
  • the ROM2 device Upon receipt of output signals from the ROMl device, the ROM2 device generates seven output signals SA to S6 for selection of the seven electrode segments of a single digit-indicating tube. This tube displays one digit by combining some of the seven electrode segments.
  • the ROM2 device is not required where there is used a digit-indicating tube commercially known as the Nixie tube which is provided with ten digit electrodes bearing the shapes of digits 0 to 9 respectively.
  • the ROMl device has 10 memory units 30 to 39 matching ten digits 0 to 9.
  • Each memory unit for example, the memory unit 30 includes one first transistor 41 and four second transistors 42. Data signals are supplied to the gate electrodes of the four second transistors 42 of the respective memory units in predetermined combinations.
  • ROM 2 device includes seven memory units (50 to 56) matching seven electrode segments.
  • the memory unit 50 has one first transistor 61 and eight second transistors 62.
  • the gate electrodes of the eight second transistors 62 are supplied with output signals from the ROMl device in a predetermined combination.
  • the memory unit 50 selects an electrode segment A, showing that indication of numerals 0, 2, 3, 5, 6, 7, 8 and 9 of the ten digits must select the electrode segment A.
  • FIG. 8 corresponds to the embodiment of FIG. 2. Accordingly, the gate electrodes of the first transistors 41 of the ROMl device and the source electrodes of the second transistors 42 of the ROM] device are supplied with first and second clock pulse signals CPI and CF] bearing a complementary relationship with each other. The gate electrodes of the first transistors 61 of the ROM2 device and the source electrodes of the second transistors 62 of the ROM2 device are supplied with another group of clock pulse signals CP2 and C P2 which have a larger width than the first group of clock pulse signals CPI and C1 1.
  • FIG. 9 corresponds to the embodiment of FIG. 4.
  • the ROMl and ROM2 devices of FIG. 9 are supplied with common complementary clock pulse signals CP and fir FIG. 10 corresponds to the embodiment of FIG. 6.
  • the first transistors of the ROMl device and the first transistors of the ROM2 device are of opposite channel types, and further supplied with common complementary clock pulse signals CP and CP.
  • a read only memory device which comprises:
  • a plurality of memory units each including one first insulated gate field effect transistor of one channel type having one gate electrode and a first and a second electrode forming a conduction path therebetween, and a plurality of second insulated gate field effect transistors of the opposite channel type to the first transistor each having one gate electrode and a first and a second electrode defining a conduction path therebetween, said conduction paths of said second transistors being connected in series with the conduction path of said first transistor, the second electrode of at least one of said second transistors being connected to the second electrode of said first transistor and an output from each memory unit being derived from the second electrode of said first transistor;
  • the read only memory device including at least two first and second read only memory devices as defined in claim 1 which are cascade connected, wherein said first transistors of said first and second read only memory devices are of the same channel type; outputs from the memory units of said first read only memory device are supplied to the gate electrodes of the second transistors of the memory units of said second read only memory device in the form of a selected combination; and said second read only memory device is supplied with clock pulse signals having a larger width than those supplied to said first read only memory device.
  • the read only memory device including at least two first and second read only memory devices as claimed in claim 1 which are cascade connected, wherein said first transistors of said first and second read only memory devices are of the same channel type; outputs from the memory units of said first read only memory device are supplied in the form of a selected combination through interposed inverter means to the gate electrodes of said second transistors of the memory units of said second read only memory device; and said first and second read only memory devices are supplied with common clock pulse signals.
  • the read only memory device including at least two first and second read only memory devices as defined in claim 1 which are cascade connected, wherein said first transistors of said first and second read only memory devices are of opposite channel types; outputs from the memory units of said first read only memory device are supplied in the form of a selected combination to the gate electrodes of said second transistors of the memory units of said second read only memory device; and said first and second read only memory devices are supplied with common clock pulse signals.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
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  • General Engineering & Computer Science (AREA)
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US358877A 1972-05-16 1973-05-10 Logic circuit arrangement employing insulated gate field effect transistors Expired - Lifetime US3866186A (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
US358877A US3866186A (en) 1972-05-16 1973-05-10 Logic circuit arrangement employing insulated gate field effect transistors
AU55663/73A AU476907B2 (en) 1972-05-16 1973-05-14 Logic circuit arrangement employing insulated gate field effect transistors
GB2312473A GB1414346A (en) 1972-05-16 1973-05-15 Circuit arrangement employing insulated gate field effect transistors
CA172,348A CA1016650A (en) 1972-05-16 1973-05-15 Logic circuit arrangement employing insulated gate field effect transistors
FR7317690A FR2184914B1 (xx) 1972-05-16 1973-05-16
CH701173A CH567839A5 (xx) 1972-05-16 1973-05-16
DE19732324787 DE2324787C3 (de) 1972-05-16 1973-05-16 Logische schaltung
US05/499,924 US3943377A (en) 1972-05-16 1974-08-23 Logic circuit arrangement employing insulated gate field effect transistors

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP4766772A JPS5332661B2 (xx) 1972-05-16 1972-05-16
JP5242772A JPS5317022B2 (xx) 1972-05-29 1972-05-29
JP5242872A JPS4917148A (xx) 1972-05-29 1972-05-29
US358877A US3866186A (en) 1972-05-16 1973-05-10 Logic circuit arrangement employing insulated gate field effect transistors
US05/499,924 US3943377A (en) 1972-05-16 1974-08-23 Logic circuit arrangement employing insulated gate field effect transistors

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AU (1) AU476907B2 (xx)
CA (1) CA1016650A (xx)
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FR (1) FR2184914B1 (xx)
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Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3703879A (en) * 1971-04-06 1972-11-28 Charles K Huthsing Jr Pressure indicator
US4017741A (en) * 1975-11-13 1977-04-12 Rca Corporation Dynamic shift register cell
US4037217A (en) * 1974-09-19 1977-07-19 Texas Instruments Incorporated Read-only memory using complementary conductivity type insulated gate field effect transistors
US4057741A (en) * 1974-01-31 1977-11-08 Lasag S.A. Logic circuit for bistable D-dynamic flip-flops
US4107548A (en) * 1976-03-05 1978-08-15 Hitachi, Ltd. Ratioless type MIS logic circuit
US4151603A (en) * 1977-10-31 1979-04-24 International Business Machines Corporation Precharged FET ROS array
US4240151A (en) * 1975-02-10 1980-12-16 Hitachi, Ltd. Semiconductor read only memory
US4646257A (en) * 1983-10-03 1987-02-24 Texas Instruments Incorporated Digital multiplication circuit for use in a microprocessor
US4661728A (en) * 1984-09-12 1987-04-28 Nec Corporation Programmable logic array circuit
US4680701A (en) * 1984-04-11 1987-07-14 Texas Instruments Incorporated Asynchronous high speed processor having high speed memories with domino circuits contained therein
US4700088A (en) * 1983-08-05 1987-10-13 Texas Instruments Incorporated Dummy load controlled multilevel logic single clock logic circuit
US4725986A (en) * 1983-09-20 1988-02-16 International Business Machines Corporation FET read only memory cell with word line augmented precharging of the bit lines
US4764691A (en) * 1985-10-15 1988-08-16 American Microsystems, Inc. CMOS programmable logic array using NOR gates for clocking
US6108765A (en) * 1982-02-22 2000-08-22 Texas Instruments Incorporated Device for digital signal processing

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1042852B (it) * 1974-09-30 1980-01-30 Siemens Ag Disposizione di circuiti logici integrata e programmabile
JPS52115637A (en) * 1976-03-24 1977-09-28 Sharp Corp Mos transistor circuit
LU76955A1 (xx) * 1977-03-15 1978-10-18
US4110633A (en) * 1977-06-30 1978-08-29 International Business Machines Corporation Depletion/enhancement mode FET logic circuit
US4291247A (en) * 1977-12-14 1981-09-22 Bell Telephone Laboratories, Incorporated Multistage logic circuit arrangement
US4429238A (en) * 1981-08-14 1984-01-31 Bell Telephone Laboratories, Incorporated Structured logic array
WO1983001160A1 (en) * 1981-09-17 1983-03-31 Western Electric Co Multistage semiconductor circuit arrangement
JPS5897922A (ja) * 1981-12-07 1983-06-10 Toshiba Corp 論理積和回路
WO1983004149A1 (en) * 1982-05-10 1983-11-24 Western Electric Company, Inc. Cmos integrated circuit
GB2120033A (en) * 1982-05-10 1983-11-23 Western Electric Co Clocked logic circuit
JPS5936427A (ja) * 1982-08-24 1984-02-28 Mitsubishi Electric Corp 出力回路
US4611133A (en) * 1983-05-12 1986-09-09 Codex Corporation High speed fully precharged programmable logic array
US4739475A (en) * 1983-09-20 1988-04-19 Mensch Jr William D Topography for sixteen bit CMOS microprocessor with eight bit emulation and abort capability
US4613772A (en) * 1984-04-11 1986-09-23 Harris Corporation Current compensation for logic gates
US4639622A (en) * 1984-11-19 1987-01-27 International Business Machines Corporation Boosting word-line clock circuit for semiconductor memory
US4652777A (en) * 1984-12-18 1987-03-24 Cline Ronald L CMOS programmable logic array
US4636661A (en) * 1984-12-21 1987-01-13 Signetics Corporation Ratioless FET programmable logic array
US4700086A (en) * 1985-04-23 1987-10-13 International Business Machines Corporation Consistent precharge circuit for cascode voltage switch logic
US4678941A (en) * 1985-04-25 1987-07-07 International Business Machines Corporation Boost word-line clock and decoder-driver circuits in semiconductor memories
US4692637A (en) * 1985-07-08 1987-09-08 At&T Bell Laboratories CMOS logic circuit with single clock pulse
US4954731A (en) * 1989-04-26 1990-09-04 International Business Machines Corporation Wordline voltage boosting circuits for complementary MOSFET dynamic memories
US4996454A (en) * 1989-06-30 1991-02-26 Honeywell Inc. Hot clock complex logic
JP3575909B2 (ja) * 1996-03-29 2004-10-13 株式会社東芝 論理回路及びその設計方法
US6509216B2 (en) * 2001-03-07 2003-01-21 United Microelectronics Corp. Memory structure with thin film transistor and method for fabricating the same
WO2010096064A1 (en) * 2009-02-23 2010-08-26 Hewlett-Packard Development Company, L.P. Dynamic impedance photodetector receiver circuit

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3250917A (en) * 1961-04-12 1966-05-10 Rca Corp Logic circuits
GB1127687A (en) * 1965-12-13 1968-09-18 Rca Corp Logic circuitry
US3526783A (en) * 1966-01-28 1970-09-01 North American Rockwell Multiphase gate usable in multiple phase gating systems
US3518451A (en) * 1967-03-10 1970-06-30 North American Rockwell Gating system for reducing the effects of negative feedback noise in multiphase gating devices
US3582674A (en) * 1967-08-23 1971-06-01 American Micro Syst Logic circuit
US3524077A (en) * 1968-02-28 1970-08-11 Rca Corp Translating information with multi-phase clock signals
DE2063639C3 (de) * 1970-03-27 1978-05-18 Rca Corp., New York, N.Y. (V.St.A.) Verknüpfungsglied
US3601627A (en) * 1970-07-13 1971-08-24 North American Rockwell Multiple phase logic gates for shift register stages
US3747064A (en) * 1971-06-30 1973-07-17 Ibm Fet dynamic logic circuit and layout
CA998746A (en) * 1972-02-14 1976-10-19 Yoshikazu Hatsukano Digital circuit

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3703879A (en) * 1971-04-06 1972-11-28 Charles K Huthsing Jr Pressure indicator
US4057741A (en) * 1974-01-31 1977-11-08 Lasag S.A. Logic circuit for bistable D-dynamic flip-flops
US4037217A (en) * 1974-09-19 1977-07-19 Texas Instruments Incorporated Read-only memory using complementary conductivity type insulated gate field effect transistors
US4240151A (en) * 1975-02-10 1980-12-16 Hitachi, Ltd. Semiconductor read only memory
US4017741A (en) * 1975-11-13 1977-04-12 Rca Corporation Dynamic shift register cell
US4107548A (en) * 1976-03-05 1978-08-15 Hitachi, Ltd. Ratioless type MIS logic circuit
US4151603A (en) * 1977-10-31 1979-04-24 International Business Machines Corporation Precharged FET ROS array
US6108765A (en) * 1982-02-22 2000-08-22 Texas Instruments Incorporated Device for digital signal processing
US4700088A (en) * 1983-08-05 1987-10-13 Texas Instruments Incorporated Dummy load controlled multilevel logic single clock logic circuit
US4725986A (en) * 1983-09-20 1988-02-16 International Business Machines Corporation FET read only memory cell with word line augmented precharging of the bit lines
US4646257A (en) * 1983-10-03 1987-02-24 Texas Instruments Incorporated Digital multiplication circuit for use in a microprocessor
US4680701A (en) * 1984-04-11 1987-07-14 Texas Instruments Incorporated Asynchronous high speed processor having high speed memories with domino circuits contained therein
US4661728A (en) * 1984-09-12 1987-04-28 Nec Corporation Programmable logic array circuit
US4764691A (en) * 1985-10-15 1988-08-16 American Microsystems, Inc. CMOS programmable logic array using NOR gates for clocking

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Publication number Publication date
FR2184914B1 (xx) 1977-04-29
US3943377A (en) 1976-03-09
DE2324787C3 (de) 1977-02-24
CH567839A5 (xx) 1975-10-15
DE2324787A1 (de) 1973-11-29
CA1016650A (en) 1977-08-30
FR2184914A1 (xx) 1973-12-28
AU5566373A (en) 1974-11-14
GB1414346A (en) 1975-11-19
AU476907B2 (en) 1976-10-07
DE2324787B2 (de) 1976-07-15

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