US3846801A - Method and apparatus for electrographic drawing - Google Patents

Method and apparatus for electrographic drawing Download PDF

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Publication number
US3846801A
US3846801A US00343397A US34339773A US3846801A US 3846801 A US3846801 A US 3846801A US 00343397 A US00343397 A US 00343397A US 34339773 A US34339773 A US 34339773A US 3846801 A US3846801 A US 3846801A
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pulses
electrodes
information
writing
writing electrodes
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US00343397A
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H Dumont
R Strohwald
H Reum
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Robert Bosch GmbH
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Robert Bosch GmbH
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/23—Reproducing arrangements

Definitions

  • the signals are distributed to the respective electrodes by time-division demultiplexers, and the pulse length of the pulses applied to the electrodes is adjustable to a value less than the burnout time by adjusting the duration of the pulse provided by a monostable flipflop inserted in the signal chain ahead of the demultiplexer input.
  • the invention relates to a method and apparatus for recording or reproducing visual information on electrosensitive sheet material, particularly on metallized paper.
  • the invention concerns the use of writing electrodes arranged next to each other in an array in which each of the electrodes is insulated from the other and is controlled by an individual controllable semiconductor device.
  • One or more groups of writing electrodes are constructed in the form of a so called electrode comb.
  • a separate signal source is used for each writing electrode and all of the signal sources simultaneously control the individual writing electrodes.
  • the simultaneous activation of the writing electrodes gives rise to the disadvantage of circuit bridging between electrodes.
  • Electrographic writing on metallized sheet material produces a small are that causes metal particles to coalesce. By thus destroying the con tinuity of the metal film locally, the maximum electrographic effect is reached when the arc burns out. It is desirable to conduct the operation without any of the electrodes being activated long enough to reach burnout, even on a maximum signal.
  • the electrodes are preferably arranged in a line which sweeps across the paper and they are preferably energized in a progressive sequence in with each is connected for energization after the preceding one in line. Any arbitrary sequence can be used, however, especially for encoded transmission cases.
  • the electrodes may, if desired, be arranged for closer packing in a staggered array, for instance, rather than all in one line.
  • a time-division demultiplexer is used to distribute time subdivisions of the signal to the respective electrodes.
  • the number of outputs of the demultiplexer must then be equal to the number of writing electrodes of the electrode group.
  • the invention is particularly useful for reproduction of line drawings and incidental lettering and printing, and other two-valued (black and white, for example) graphic information.
  • the information to be displayed on the electrosensitive sheet material is first supplied to one input of a two input NAND gate, the other input of which is constituted by the clock pulses supplied by a timing circuit.
  • the result is a series of pulses of length determined by the clock pulses (i.e., by their period, duty cycle and polarity) and their presence or absence in any clock pulse period is dependent on the state of the input information in that period.
  • the demultiplexer is advanced by means of a binary counter which operates in response to the same clock pulses that are applied to the aforesaid NAND gate.
  • the input to the demultiplexer is thus switched in turn to each of the outputs. Successive signal pulses proceed from each of these outputs in turn to the respective control electrodes of semiconductor devices each of which electrically drives one of the writing electrodes.
  • the maximum pulse length is less than the clock pulse period, so that each electrode is activated for just one pulse and one signal pulse reaches only a single electrode.
  • a monostable flip-flop (monoflop) circuit having a manually adjustable period to determine the pulse length and to interpose this circuit between the output of the NAND gate and the signal input of the demultiplexer.
  • the pulses furnished by the NAND gate to the monostable flip-flop may be either short or long, however the clock pulse gating may produce them, since the monoflop can operate either as a pulse stretcher or a pulse shortener.
  • the modification of the writing time made possible by the adjustment of the period of the monoflop circuit provides control over the point size and hence the degree of blackness of the graphic display, so that writing at various values of gray is possible.
  • the writing electrodes are grouped in a plurality of adjacent groups or sub-arrays, each of which comprises the same number of writing electrodes.
  • Such an apparatus is also drven so that all of the writing electrodes are driven in sequence and that the period for which a single electrode is activated each time is less than the period in which the writing process would come to an end by burnout.
  • each sub array of electrodes and their respective driving semiconductors is provided with one of a number of identical demultiplexers, all of which are advanced by a common binary counter.
  • a number of additional flipflops form a 3 bit binary counter provided for enabling each of the demultiplexers in turn for a complete demultiplexing cycle, so that the signal inputs of all the demultiplexers may be continuously fed in parallel with the same input signal.
  • An extra set of NAND is interposed between the pulse length determining (monoflop) circuit and each of the demultiplexers, completes the counting function of the flip-flops, in association with additional inputs on each of the demultiplexers interconnected in the counting circuit to provide the necessary sequencing of the demultiplexers.
  • the several demultiplexer units, the 3 bit flip-flop counter, and the 4 bit binary counter used to advance all the demultiplexer units may be regarded as a two-stage demultiplexing means.
  • An additional pulse forming circuit is used to provide a suitable reset pulse after all of the demultiplexer units have each gone through one demultiplexing cycle.
  • FIG. 1 is a diagram of a circuit according to the invention in which an array of 16 adjacent electrodes is operated through a demultiplexer with 16 outputs;
  • F lG. 2 is a diagram of a circuit in accordance with the invention in which five groups of 16 electrodes are operated through five demultiplexers, and
  • FIG. 3 is a graph showing pulses present in the circuits of FIGS. 1 and 2.
  • the electrosensitive paper used as the medium for graphical signal display is designated with the reference numeral 20.
  • the electrosensitive paper 20 For writing information on the electrosensitive paper 20, there is provided a group 21 of 16 writing electrodes 8,, 8,, S S, which are arranged next to each other and electrically insulated from each other. These writing electrodes are respectively driven by writing transistors T,,, T,, T T,,,, The collectors of the writing transistors are connected to the respective writing electrodes and their emitters are grounded, to the apparatus chassis, for example.
  • the electrosensitive paper 20 is connected to the writing voltage of -35 volts over a resistor 26.
  • a demultiplexer 31 of the time-division type serves the electrode group 21.
  • This demultiplexer is provided with 16 information outputs designated 0, 1, 2 and has four binary switching inputs A,, B,, C,, D, serving as tming information inputs and two enable inputs 6, and G
  • the demultiplexer 31 can accordingly be a commercial type of TTL-demultiplexer built in accordance with integrated circuit techniques, such as the type SN 74154 made by Texas Instruments.
  • the NAND gates may likewise be provided in integrated circuit form with several on one substrate (e.g., SN 7400 made by Texas Instruments).
  • the binary counter 50 used to step the demultiplexer 31 may likewise by a type SN 7493 Texas Instruments circuit unit.
  • the monoflop 41 may be an SN 74121 device of the same series.
  • the SN 74154 units used as demultiplexers are TTL logic devices in which the selected output is at LOW" logic voltage level while all the others are at HIGH logic level provided that both of the enable (or strobe) inputs G, and G are likewise at LOW logic levl (otherwise the, selected output is at HIGH logic level, the same as the unselected outputs, which corresponds to no electrographic writing in the present apparatus).
  • the LOW logic level could, for example, be 0.8 volts or less, and the HIGH logic level 2 or more volts, in a low impedance circuit.
  • the information outputs l), 1, 2, 15 of the demultiplexer 31 are connected over protective resistors R R,, R R respectively to the bases of the writing transistors T,,, T,, T,, T,,.
  • a NAND gate N with two inputs E and E is provided, to the first input of which the signal to be dis played graphically is first supplied.
  • the output P of the NAND gate N is connected to the input 41 of a monostable flip-flop circuit 40, the output pulse of which has a variable period the length of which is adjustable by a potentiometer which is not shown in the drawing.
  • the output 42 of the monostable flip-flop (monoflop) 40 is connected to the first enable input (1,, of the demultiplexer 31.
  • the second input E of the NAND gate N is connected to the pulse input 51 of a 4 bit bi-.
  • nary counter 50 of which the information outputs A B C D are connected to the information inputs A,, B,, C,, D, of the demultiplexer 31 to advance the switching circuits of the latter.
  • the second enable input G of the demultiplexer 31 is grounded and thus is held in LOW" condition.
  • a second monostable flip-flop circuit 60 is provided of which the noninverting output 61 is connected to the reset input 52 of the 4 bit binary counter 50.
  • the reset control input of monoflop 60 may be derived from the counter 50, from the demultiplexer 31 or from an external timer.
  • the information (VIDEO) to be graphically displayed on the electrosensitive paper is applied as a signal to the first input E,,,, of NAND gate N (FIG. 3, second line).
  • a clock pulse externally supplied to the circuit appears which also advances the 4 bit binary counter 50.
  • the pulses appearing at the output P of NAND gate N are shortened in duration in monoflop circuit 40 to a value 1,,- corresponding to the switching time of each of the writing electrodes S 8 ,8 515, this value being adjustable by a potentiometer not shown in the drawing. This period t,,- of the pulses appearing at the output of monoflop 40 is so adjusted that it is shorter than the time in which the electrographic effect would come to an end by burnout.
  • the monoflop 40 can operate as a pulse stretcher instead of as a pulse shortener, with the result in any event being the same.
  • the NAND gate N is not an ordinary digital gate but it is in effect a switched amplifier and the monoflop 40 switches on an amplifier or other device (not shown) during the length of its output pulse so that the output of the combined arrangement will have an amplitude corresponding to the signal at the input of the system and a pulse length determined by the setting of the monoflop 40. It is also possible to have the amplitude of the input signal very the duration of the pulse produced by monoflop 40, by means not shown, instead of the provision of the manual pulse length adjustment.
  • the pulses taken from the output of monoflop 40 are supplied to the signal input 0,, of demultiplexer 31, whereas the second signal input G is held in the LOW condition.
  • the clock pulse c advances the 4 bit binary counter 50, which is to say that it causes the outputs A B C D of the counter 50 to go through all 16 possible sets of binary conditions in logical sequence.
  • These output count pulses of the 4 bit binary counter 50 are provided to the information inputs A,, B,, C,, D, of the demultiplexer 31, causing the switching circuits of the latter to be advanced as previously mentioned.
  • the information outputs 0, 1, 2, 15 of demultiplexer 31 are caused to produce one after the other in sequence as timed by the pulses present at the first input (3,, are switched to the LOW" condition for the period p of a single pulse.
  • a writing pulse consequently appears only at the particular information outputs which, at that moment, receive a VIDEO signal with the necessary information to produce a pulse.
  • the writing pulses transmitted from the information outputs 0, l, 2, 15 of demultiplexer 31 are led to the base electrodes of writing transistors T,,, T,, T, T,,,, respectively over resistors R,,, R,, R R, After all of the writing electrodes have been connected in turn to the demultiplexer, the 4 bit binary counter 50 is reset to its original condition by a reset pulse, the duration of which is determined by monoflop 60.
  • FIG. 2 shows a second embodiment of the invention.
  • the writing electrodes of the first group 21 are designated S, S, S those of the second group 22 are designated S S S S, and so on.
  • the writing electrodes S,, S, S 5, of each group are controlled over writing transistors T,,,,,, T,,,, T T, where the subscript i may take the value 1, 2, 3, 4 and 5 according to whether it refers to the writing electrode or to the writing transistor in the first group 21, the second group 22, the third group 23, etc.
  • the collectors of the writing transistors are connected to the writing electrodes, while their emitters are grounded.
  • the electrosensitive paper is connected to the writing voltage of ---35 volts over a resistor 26.
  • Each of the five electrode groups 21, 22, 23, 24, is provided with one of the five identical demultiplexers 31, 32, 33, 34, 35.
  • Each demultiplexer is provided with two signal inputs G, G and with four binary information inputs A,, 13,, C,, D,-, where the subscript i may take the values 1, 2, 3, 4, 5 according to whethr the demultiplexer is associated with the first electrode group 21, the second electrode group 22, and so on.
  • Each of the demultiplexers also has l6 information outputs, in each case designated 0, l, 2 15. These information outputs are connected to the base of the respective writing transistors T,, T, T T,,, over the resistors R,, R, R R respectively.
  • the NAND gate N is provided with two inputs E and E
  • the output P of the NAND gate N is connected to the input 41 of a monoflop 40 of which the output pulses have a variable pulse duration i which may be varied by adjustment of a potentiometer not shown in the drawing.
  • the second input E of NAND gate N is connected to a clock pulse source (not shown) and to the pulse input 51 of a 4 bit binary counter 50, the information of which are designated A B C and D
  • NAND gates N,. N N,,, N, and N each with three inputs E, E E, are provided in connection with each of the five demultiplexers 31, 32, 33, 34, 35.
  • the first enable input G of the first deniultiplexer 3l is connected to the output P, of NAND gate N,.
  • the first enable input G of the second demultiplexer 32 is connected to the output P of NAND gate N and so on.
  • Each of the first inputs E, of the five NAND gates N,, N N N N is connected to the output 42 of monoflop 40.
  • this circuit three flip-flops F,, F, and F are provided.
  • the input 70 of first flip-flop F is connected to the output D,, of 4 bit binary counter 50.
  • the input 80 of second flip-flop F is connected to the noninverting output Q, of first flip-flop F,.
  • the input 90 of third flipflop F is connected to the noninverting ogtput Q of second flip-flop F.
  • the inverting output Q of third flip-flop F is connected to the second enable input G of fifth demultiplexer 35.
  • the noninverting output 0,, of third flip-flop F is connected to the second enable inputs G G G and G of the remaining four demultiplexers 31, 32, 33, 34.
  • the second input B 2f NAND gate N is connected to the inverting output Q, of first flip-flop F,.
  • the third input E of NAND gate N is connected to the inverting output 6 of second flip-flop F.
  • the second input E of NAND gate N is connected to the noninverting output Q, of first flipflop F,.
  • the third input E o f NAND gate N is connected to the inverting output 0, of second flip-flop F
  • the second input E of NAND gate N is connected to the inverting output 6, of first flip-flop F,.
  • the third input E of NAND gate N is connected to the noninverting output Q of second flip-flop F
  • the second input E of NAND gate N is connected to the noninverting output Q, of first flip-flop F,.
  • the third input E of NAND gate N is connected to the noninverting output 02 of second flip-flop F
  • the second input E of NAND gate N is connected to the noninverting output 0 of third flip-flop F
  • the third input E of NAND gate N is held in HIGH condition by connection to the supply voltage U
  • a second monoflop is also provided.
  • the noninverting output 61 of monoflop 60 is connected to the reset input 52 of the 4 bit binary counter 50.
  • the inverting output 62 of monoflop 60 is connected to the reset inputs 71, 81, 91 of the three flip-flops F,, F and F3.
  • the reset control connection of monoflop 60 may be derived from multiplexer 35, from flip-tlop F or from an external timer or synchronizer (not shown).
  • VIDEO The information (VIDEO) to be graphically displayed on electrosensitive paper is applied to the first input E, of NAND gate N,,.
  • a VlDEO signal is shown in the second line of FIG. 3 by way of example.
  • a clock pulse Cp which is also applied to the input of4 bit binary counter 50 to advance that counter.
  • the pulses appearing at the output P of NAND gate N has their duration shortened in monoflop 40 to a value which corresponds to the switching interval r,- of each of the individual electrodes 8,, S,, S, 5, this value being adjustable by means of a potentiometer not shown in the drawing.
  • This duration t of the pulses formed at the output 42 of monoflop 40 is so adjusted that it is shorter than the time that would end the writing process by burnout.
  • the clock pulse Cp advances at the same time the 4 bit binary counter 50, so that at its information outputs A B C D all 16 possible output combinations are provided in logical sequence.
  • These output pulses of the 4 bit binary counter 50 are supplied to the several parallel connected information inputs A,-, B,, C, and D, of the demultiplexers 31, 32, 33, 34, 35. If both of the signal inputs 0, and G of the demultiplexers were simultaneously in the LOW condition, then the information outputs 0, l, 2 l5 of the demultiplexers 31, 32, 33, 34 and 35 would each in sequence and in the red above the writing impulses be connected to the LOW condition for the duration t of a single pulse.
  • the second signal inputs G of the demultiplexers are so switched that only one demultiplexer is free to accept signalsat any time.
  • the signals appearing at the output pulses arising at the'information outputs 0, l, 2 15 of the ,demultiplexers' 31, 32, 33, 34, 35 are furnished over the protective resistances R R R R to the baseelectrodes of the respective writing transistors T ,-,'T, T 3, T which each in turn switch the writing voltage through to the electrode for the duration t,,- of the pulse.
  • the driving transistors T T,, T T may be switching type transistors, since their function is to switch the writing voltage to the electrode or not according to whether 21 VIDEO signal is present or not during the period that the particular transistor is connected through to the monoflop pulse generator 40 through the demultiplexer.
  • the monopulse flip-flop 40 will electrode comb organization together with the corresponding driving transistors, protective resistors and the multiplexers and such an electrode comb can consist of individual segments if more than one demultiplexer is used, with one segment for the equipment as- 'sociated with each demultiplexer.
  • the writing electrodes are preferably made of tungsten wire and they may very conveniently be provided by plating the end of thetungsten wire, which used to be connected to the transistor by electroplating with copper, gold, silver, tin or a combination of those metals and then soldering the plated end of the tungsten wire directly to the collector connection of the driving transistor with soft solder.
  • a method as defined in claim 3 in which the modifying of the electrical information to be recorded comprises the steps of:
  • Apparatus for displaying information on electrosensitive sheet material the electrographic effect on which is limited by a localized burnout characteristic comprising:
  • gate means N for producing gated pulses timed by said clock pulses from a signal representative of information to be displayed; demultiplexing means (31) having a successive sequencing interval, determined by said clock pulse generation, at least as long as the time required to produce local burnout on said sheet material and including a binary counter (15) responsive to said clock pulses for distributing said pulses produced in response to operation of said gate means in sequence to the individual writing electrodes of said array, said gate means accordingly being the same for all pulses, and
  • circuit means incorporated in said gate means for assuring that the duration of pulses supplied to said demultiplexing means in response to operation of said gate means is less than the time required to produce local burnout on said sheet material.
  • circuit means incorporated in said gate means is a monostable pulse forming means (40) of adjustable pulse length interposed between said gate means and said multiplexer.
  • Apparatus for displaying information on electrosensitive sheet material the electrographic effect on which is limited by a localized burnout characteristic, comprising:
  • monostable gate means N for producing, from a signal representative of information to be displayed, gated pulses timed by said clock pulse generator and having a duration less than the time required to produce local burnout on said sheet material;
  • each of said dcmultiplexers hiving two signal inputs and having individual gate means connected between a first signal input of said demultiplexer and the output of said monostable gate means, said individual gate means having a first input to which the output of said monostable circuit is connected and two additional inputs;
  • a plurality of flip-flop circuits are interconnected with each other, with the second and third inputs of said individual gate means and with the second inputs of said demultiplexers and also with said resetting circuit, so that each of said demultiplexers will be activated for a complete cycle of operation in sequence while the others of said demultiplexers are furnishing no output, whereby each one of said writing electrodes will be activated in turn.
  • Apparatus as defined in claim 8 in which one or more of said sub arrays of writing electrodes are mounted on an electrode comb consisting of individual segments which contain writing electrodes, driving semiconductor devices therefor, and demultiplexers.
  • a method of making an apparatus for electrographically displaying formation in which the ends of the tungsten wires forming the writing electrodes of said apparatus which are to be connected to the respective driving semiconductor devices of said apparatus are electroplated with a metallic material selected from the group consisting of the metals copper, gold, silver, tin, and combinations of said metals as simultaneously electroplated, and are then affixed with the thus electroplated end soldered with soft solder to the collector connection of the corresponding driving semiconductor device.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Electronic Switches (AREA)
  • Facsimile Scanning Arrangements (AREA)
  • Facsimile Heads (AREA)
  • Digital Magnetic Recording (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
US00343397A 1972-03-30 1973-03-21 Method and apparatus for electrographic drawing Expired - Lifetime US3846801A (en)

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DE19722215519 DE2215519C3 (de) 1972-03-30 Verfahren zur Aufzeichnung von Informationen und Schaltungsanordnung zur Durchführung des Verfahrens

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US (1) US3846801A (enrdf_load_stackoverflow)
JP (1) JPS5735508B2 (enrdf_load_stackoverflow)
AT (1) AT344412B (enrdf_load_stackoverflow)
CH (1) CH554579A (enrdf_load_stackoverflow)
FR (1) FR2178225B1 (enrdf_load_stackoverflow)
GB (1) GB1430861A (enrdf_load_stackoverflow)
IT (1) IT973289B (enrdf_load_stackoverflow)
NL (1) NL7304378A (enrdf_load_stackoverflow)

Cited By (11)

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US3947626A (en) * 1973-03-30 1976-03-30 U.S. Philips Corporation Method of recording cinematographic images from an electric signal produced by scanning image sequences to be displaced and device for carrying out this method
US4100551A (en) * 1975-09-09 1978-07-11 Sci Systems, Inc. Rotary electrical printer and method
US4145697A (en) * 1977-12-28 1979-03-20 Honeywell Inc. Graphic recording apparatus with stylus addressing by shift registers
US4232342A (en) * 1973-04-13 1980-11-04 Skala Stephen F Multiplexing for facsimile systems
EP0082978A1 (en) * 1981-12-29 1983-07-06 International Business Machines Corporation Circuit for controlling a multi-wire printhead
US4413269A (en) * 1981-11-23 1983-11-01 International Business Machines Corporation Method of and apparatus for controlling gray scale while printing on charge sensitive recording mediums
EP0096184A1 (en) * 1982-06-16 1983-12-21 International Business Machines Corporation Method for controlling the energization of the print elements in an electroerosion printer
US4434432A (en) 1982-06-24 1984-02-28 International Business Machines Corporation Universal image coder and controller for multicolor electrolytic printing
US4536769A (en) * 1982-03-25 1985-08-20 International Business Machines Corporation Method of recording information on an electrosensitive record carrier
US4575740A (en) * 1982-03-25 1986-03-11 International Business Machines Corporation Transistor circuit for reducing current after ignition in a metal paper printer
US20050022076A1 (en) * 2003-07-02 2005-01-27 Shinobu Nakamura Phase error determination method and digital phase-locked loop system

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JPS5655074A (en) * 1979-10-11 1981-05-15 Chiyou Lsi Gijutsu Kenkyu Kumiai Schottky barrier gate type field effect transistor
US5536967A (en) * 1980-12-30 1996-07-16 Fujitsu Limited Semiconductor device including Schottky gate of silicide and method for the manufacture of the same
JPS57113289A (en) * 1980-12-30 1982-07-14 Fujitsu Ltd Semiconductor device and its manufacture
JPS57128071A (en) * 1981-01-30 1982-08-09 Fujitsu Ltd Field-effect type semiconductor device and manufacture thereof
JPS5848968A (ja) * 1981-09-18 1983-03-23 Fujitsu Ltd 半導体装置の製造方法
JPS58103175A (ja) * 1981-12-15 1983-06-20 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JPS5916383A (ja) * 1982-07-19 1984-01-27 Sony Corp 半導体装置

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US3441946A (en) * 1965-06-29 1969-04-29 Bendix Corp Circuit for supplying writing signals for use with electrosensitive paper recorders
US3553718A (en) * 1969-06-20 1971-01-05 Itt Multiple stylus electrolytic recorder
US3611411A (en) * 1969-10-29 1971-10-05 Listening Inc Spectrum-analyzing recorder
US3613103A (en) * 1969-07-25 1971-10-12 Alden Res Found Analog signal modifying apparatus
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US3441946A (en) * 1965-06-29 1969-04-29 Bendix Corp Circuit for supplying writing signals for use with electrosensitive paper recorders
US3644931A (en) * 1968-09-10 1972-02-22 New Zealand Inventions Dev Multistyli recorders with styli cyclically moved through interstylus spacing
US3553718A (en) * 1969-06-20 1971-01-05 Itt Multiple stylus electrolytic recorder
US3613103A (en) * 1969-07-25 1971-10-12 Alden Res Found Analog signal modifying apparatus
US3611411A (en) * 1969-10-29 1971-10-05 Listening Inc Spectrum-analyzing recorder

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3947626A (en) * 1973-03-30 1976-03-30 U.S. Philips Corporation Method of recording cinematographic images from an electric signal produced by scanning image sequences to be displaced and device for carrying out this method
US4232342A (en) * 1973-04-13 1980-11-04 Skala Stephen F Multiplexing for facsimile systems
US4100551A (en) * 1975-09-09 1978-07-11 Sci Systems, Inc. Rotary electrical printer and method
US4145697A (en) * 1977-12-28 1979-03-20 Honeywell Inc. Graphic recording apparatus with stylus addressing by shift registers
US4413269A (en) * 1981-11-23 1983-11-01 International Business Machines Corporation Method of and apparatus for controlling gray scale while printing on charge sensitive recording mediums
US4470056A (en) * 1981-12-29 1984-09-04 International Business Machines Corporation Controlling a multi-wire printhead
EP0082978A1 (en) * 1981-12-29 1983-07-06 International Business Machines Corporation Circuit for controlling a multi-wire printhead
US4536769A (en) * 1982-03-25 1985-08-20 International Business Machines Corporation Method of recording information on an electrosensitive record carrier
US4575740A (en) * 1982-03-25 1986-03-11 International Business Machines Corporation Transistor circuit for reducing current after ignition in a metal paper printer
EP0096184A1 (en) * 1982-06-16 1983-12-21 International Business Machines Corporation Method for controlling the energization of the print elements in an electroerosion printer
US4434432A (en) 1982-06-24 1984-02-28 International Business Machines Corporation Universal image coder and controller for multicolor electrolytic printing
US20050022076A1 (en) * 2003-07-02 2005-01-27 Shinobu Nakamura Phase error determination method and digital phase-locked loop system
US7730366B2 (en) * 2003-07-02 2010-06-01 Sony Corporation Phase error determination method and digital phase-locked loop system

Also Published As

Publication number Publication date
JPS5735508B2 (enrdf_load_stackoverflow) 1982-07-29
FR2178225B1 (enrdf_load_stackoverflow) 1976-09-10
AT344412B (de) 1978-07-25
ATA272673A (de) 1977-11-15
IT973289B (it) 1974-06-10
DE2215519A1 (de) 1973-10-11
GB1430861A (en) 1976-04-07
NL7304378A (enrdf_load_stackoverflow) 1973-10-02
CH554579A (de) 1974-09-30
FR2178225A1 (enrdf_load_stackoverflow) 1973-11-09
JPS499914A (enrdf_load_stackoverflow) 1974-01-29

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