US3828342A

US3828342A - Monitoring and display apparatus

Info

Publication number: US3828342A
Application number: US00227208A
Authority: US
Inventors: C Burton
Original assignee: Fujitsu Services Ltd
Current assignee: Fujitsu Services Ltd
Priority date: 1971-02-17
Filing date: 1972-02-17
Publication date: 1974-08-06
Anticipated expiration: 1991-08-06
Also published as: DE2207475A1; DE2207475C3; FR2126006A5; AU3897872A; AU457150B2; GB1335302A; DE2207475B2

Abstract

Apparatus is described for displaying, on a display device having a number of spatially separated indicating positions such as a television monitor screen or a matrix of display lamps, the states of a number of elements, each elemental state being primarily indicated by signals applied over one of a number of indicating lines. The lines are connected to display converter modules which are arranged to scan the lines in sequence to produce a composite output signal which is applied to the display device. Where the number of lines is large, the serialisation of the line states may be done in stages, the first stage being the derivation of a separate composite signal from each of a number of groups of lines. The second stage then consists of deriving a final output signal by scanning the first-stage composite signals in turn.

Description

llntted States Patent [191 [11] 3,828,342 Burton Aug. 6, 1974 MONITORING AND DISPLAY APPARATUS 3,573,737 4/1971 Sandgren et a1. 340/324 AD [751 hivehihh Chiisihpheh Philip hhi-ihh, hiheiiey 2:23:33? 2113?; 23,212 332;51:11::...11:133$%ii5 Edge, England [73] Assignee: International Computers Limited,

London, England [22] Filed: Feb. 17, 1972 [21] Appl. No.: 227,208

[30] Foreign Application Priority Data Feb. 17, 1971 Great Britain 4804/71 [52] U.S. Cl 340/324 AD, 178/73 D [51] Int. Cl...; G06f 3/14 [58] Field of Search. 340/324 AD, 212, 413, 324 A; 178/7.3 D, 7.5 D

[56] References Cited UNITED STATES PATENTS 3,234,534 2/1966 Todman 340/212 X 3,336,587 8/1967 Brown 340/324 AD 3,375,509 3/1968 Mullarkey 340/213 R 3,388,391 6/1968 Clark 340/324 AD 3,530,236 9/1970 Marko 340/212 X Primary Examiner-David L. Trafton Attorney, Agent, or Firm-Keith Misegades ABSTRACT Apparatus is described for displaying, on a display device having a number of spatially separated indicating positions such as a television monitor screen or a matrix of display lamps, the states of a number of elements, each elemental state being primarily indicated by signals applied over one of a number of indicating lines. The lines are connected to display converter modules which are arranged to scan the lines in sequence to produce a composite output signal which is applied to the display device. Where the number of lines is large, the serialisation of the line states may be done in stages, the first stage being the derivation of a separate composite signal from each of a number of groups of lines. The second stage then consists of deriving a final output signal by scanning the first-stage composite signals in turn.

3 Claims, 3 Drawing Figures VIDEO Dl$PLAY MONITORING AND DISPLAY APPARATUS CROSS REFERENCE TO RELATED APPLICATION Co-pending Pat. application Ser. No. 227,209 filed 17 th Feb. 1972 and assigned to the same assignee, deals with the combination of the display converter modules into the display control system.

BACKGROUND OF THE INVENTION 1. FIELD OF THE INVENTION The invention relates to signal monitoring and display apparatus.

2. Description of the Prior Art Data I processors frequently use display lights for monitoring the states of signals at various positions within the machine. Disadvantages arise from feeding such signals in parallel to individual display lights. It is wasteful to utilize high bandwidth connections for low bandwidth signals involved. Also, extra connectors may be required together with very large multi-pin plugs and sockets if portable display panels are envisaged.

SUMMARY According to the invention signal monitoring and display apparatus includes a group of lines respectively carrying signals representative of the current states of elements to be monitored; at least one display converter module having a group of AND gates respectively corresponding each to a different one of the lines, each line being connected to a first input of the corresponding AND gate, and sequential scanning means to derive an output data signal from the module representative of the states of the signal lines respectively presented in'succession at a predetermined frequency during a scanning period; the apparatus further including a display device having a plurality of spatially separated index positions and means for applying the output data signal from the module to the display device.

The scanning may be accomplished by sequentially enabling the AND gates for example by using a shift register. 1

Alternatively, scanning may be accomplished by simultaneously enabling some or all of the AND gates using shift register means for storing the results and furnishing them serially. This type of operation results in a snapshot" where the data signal represents signals to be monitored at the same time.

Embodiments of the invention have particular application to large scale integrated arrays of circuits where access to an array is restricted by the availability of only a limited number of connections. The application 'of the display converter modules of the presentinvention to a display arrangement is set forth in co-pending application Ser. No. 227,209.

BRIEF DESCRIPTION OF THE DRAWINGS Preferred embodiments of the invention will now be described, by way of example, with reference to the drawings, in which:

FIG. 1 shows, schematically, a first type of parallelto-serial converter;

FIG. 2 shows, symbolically, the type of converter shown in FIG. 1;

FIG. 3 shows, schematicaly, an arrangement including a plurality of converters each similar to that of FIG. 1 for providing line ad frame scan type serial output signals; and

FIG. 4 shows, schematically, part of a second type of paraIIel-to-serial converter.

DESCRIPT ION OF THE PREFERRED EMBODIMENTS minals M1 to M8 to first inputs of AND gates 11 to 18,

respectively.

The AND gates have second input terminals v11b to 18b connected to transfer leads of the shift register stages 1 to 8, respectively each of which leads goes high for a predetermined state of the corresponding stage.

Terminals I and O constitute a state-determining input to the first shift register stage 1 and a staterepresentative output from the last shift register stage 8, respectively. Generally the stage configuration and external logic requirements are such that one line terminals are sufficient. A terminal S serves for shift pulses at a first repetition rate and is coupled to each A of the shift register stages 1 to 8 to cause shift register propagate operation from left to right in FIG.' I. In practice, additional circuits may be used to increase the driving capability of the shift pulses.

AND gate output terminals 11c to are connected together to a common monitor output terminal V. This is more convenient in most applications than using an OR gate.

In operation, all of the shift register stages 1 to 8 are initially in their state differing from the predetermined state. A pulse is applied, via I, to set the first stage 1 to the predetermined state. On the next shift, the predetermined state is removed from terminal I and the second input terminal 11b of the AND gate 11 goes high so enabling the signal to be monitored to appear at the monitor output terminal V via AND gate output llc.

In response to subsequent pulses at the shift terminal 5, the predetermined state. is propagated through the shift register stages in turn, causing successive enabling of the AND gates 12 to 18, and serial appearance at the monitor output terminal V of signal components representing the signals to be monitored via terminals M2 to M8 FIG. 2 shows a convenient block representation of a converter circuit of FIG. 1. In using this block, intermediate monitor signal terminals M2 and M7 will sometimes be indicated by dashes between the end monitor signal terminals M1 to M8.

FIG. 3 shows, schematically, part of a system for providing serial representations from I6 groups each of 32 signals to be monitored. As will be seen, each group will provide 32 signal components together making up one line of a l6-lines per frame video signal.

Each of these groups utilizes an arrangement, one of G1 to G16, of four converters each similar to that of FIG. 1. Only the arrangements G1, G8 and G16 are shown and, for each of these, blocks are shown only for the first and fourth converters. Each of the arrangements G1 to G16 has a single line, CS1 to C816, connecting the shift pulse terminals S of all the converters thereof to a clock bus CB. Each arrangement G1 to G16 also has a single output line, CV1 to CV16, to which the monitor output terminals V of all of the converters thereof are connected- Within each group, the converters are connected in series, with the last stage output of each converter connected to the first stage input I of the next converter. The first stage input of the first converter of each arrangement is connected to a pulse signal bus PSB. As will be described for line 104, the pulses on line PSB are at a submultiple, one-thirty-sec'ond, of the repetition rate of pulses from bus LB, which rate is not more than one-thirty-second the repetition rate of clock pulses on bus CB; Thus, the predetermined state set in the first stage of the first converter of any one of the arrangements G1. to G16, will be propagated through the shift registerstages of all four converters thereof before the next pulse appears on the bus LB. During that time, monitor components will appear serially on the lines CV1 to CV16 from all of the 32 signals to be monitored by each arrangement G1 to G16. Clearly several pulses in fact 31, will appear on bus LB before another pulse appears on line PS8 to initiate the predetermined states again.

The clock bus CB is conveniently supplied by a free running pulse source 100 having a repetition rate of about 330 KHZ, say giving a l microsecond pulse every 3 microseconds. The signal bus LB is conveniently fed by a free running source 101 of 10 KHZ pulses, say of 3 microseconds duration every 100 microseconds, and corresponds with a line sync generator for the ultimate video signal. The source 101 will be locked in by any pulse from source 100.

The monitor signals of the arrangements G1 to G16 appearing in parallel on lines CV1 to CV16 are converted to serial form using a further two series connected

converters

102 and 103 each of the type shown in FIG. 1. Lines CV1 to CV8 are connected to the monitor input terminals M1 to M8, respectively, of converter 102. Llnes CV8 to CV16 are similarly connected to converter 103.

Both of the

converters

102, 103 have their shift terminals S connected to line 104. A predetermined state which enables output from monitor output terminals V of

converters

102 and 103 is therefore propagated from stage to stage with an interval determined by pulses on line 104. In order to separately show the series of signal elements from successive ones of the lines CV1 to CV16 on a conventional television monitor, it is convenient for the pulses on line 104 to be separated by 32 times the interval between the pulses from the generator 101. On one standard monitor, this gives a spacing of about one-half inch between lines of displayed data. If the beam is defocussed to give a blob of about a quarter of an inch diameter and the beam current increased, a very satisfactory, bright display results.

It would, of course, be desirable to align a mask with the monitor screen to aid identification of the signals represented by the various possible light spot positions. Possibilities for doing this include using fixed grid reference lines and coordinates marked on a system logic diagram, fixed or interchangable film masks, or back projection systems for masks or logic diagrams. The latter two possibilities are specially suited to uses involving several arrays of FIG. 3. Alternatively, appropriate further video signals may be multiplexed in.

The pulse signals desired for line 104 can be derived from the output of generator 101 using two

converters

105, 106 of FIG. 1. The first of these, 105, has its shift pulse input S connected to the output of generator 101 to propagate between shift register stages at the rate of that pulse output. The first stage input terminal I is connected to the monitor output terminal V via an inverter 107. The monitor signal inputs of converter 105 are permanently energised by predetermined signals. In FIG. 3, the first and fifth monitor terminals are indicated by a zero and have a signal thereat that is the inverse of what would be required to seta shift register stage of the converter 105 to the predetermined state. All other monitor terminals are complementarily energised with reference to the shift register state they would induce. The result is that converter 105 will provide a last stage shift register output 0 for every fourth one of the pulses from generator 101. r

The last stage output of converter 105 is connected to the shift pulse terminal S of the converter106. The converter is connected as for converter 105 but with only its first monitor terminal energised as for the zero references above. The result is that the last stage shift register output 0 of converter 106 will appear once for every 32 of the ouput pulses of generator 101.

The ultimate serial output signals from terminals V of

converters

102 and 103 are taken to mixer 108 via line 109. The mixer 108 also received pulses from the bus LB which it combines with the signals on line 109 as line sync signals of a composite video signal for which the frame sync signal is derived from the last stage shift register output of the converter 103. The latter may also be fed back to the first stage input I for converter 102.

If RF modulation is provided for, several network arrays of the FIG. 3 type may have their output available alternatively by using a channel selector. Only a single line connection would be required for each FIG. 3 array.

Another type of basic converter results from a modification of the FIG. 1 circuit by connecting the AND gate outputs, 11 'c to l8c in FIG. 4, to determine states of corresponding shift register stages when the AND gate second inputs, ll'b to l8b in FIG. 4 are simultaneously energised. The AND gate second inputsare connected to a common line for this purpose. The result is that the states of the shift register stages represent monitored signal conditions at the time of energising the AND gate second inputs.

Arrangements of series connected converters of this other type will handle more signals to be monitored on a simultaneous or snapshot basis by connecting all the second AND gate inputs together. If the overall shift register of such an arrangement is made reentrant (i.e. its last stage output fed back to its first stage) a snapshot may be stored for continuous display.

Clearly, parallel networks of such converters and arrangements are also realisable in a manner similar to FIG. 3 for the first type of converter. Snapshot storage capabilities would be unaffected.

Slow scanning for feeding signals out for transmission, e.g., over the telephone network could be provided. It may also be desired to provide facilities whereby one or more lines can be displayed selectively, or to arrange that the order of the lines of display can be altered. This general flexibility is very useful and may be exploited by local console switching, or display subroutines which may form part of a test and maintenance procedure.

In general, for use in place of display lights for a processor, it seems convenient for an integrated circuit module for the converters to use relatively slow, cheap logic technology compatible with the signal from the type, e.g., emittercoupled logic (ECL), used in the processor.

The operation of a circuit of FIG. 1 results in an enabling signal being sequentially applied by the shift register to the AND gates. The same result can be obtained using a sequential state register, such as a counter operated at the first repetition rate, as by pulses from a clock, and a decoder having a plurality of outputs each for enabling a different AND gate. The decoder will operate to energise its outpus sequentially as the counter state changes. Enabling of the decoder at the second repetition rate completes the analogy of the operation. The decoding may be partially or fully incorporated in third and, if necessary, further inputs of the AND gates.

Each decoder may serve thirty-two ANDgates to make up the equivalent of a line, arrangement G of FIG. 3. Such a decoder could operate off the five least significant stages of a single counter with more significant stages feeding logic for providing enabling signals to determine which of several sets 'of 32 AND gates is operable.

Particular applications are envisaged where sequential states are controlled partly by free running counter operation to cycle through several lines of monitored signals, and partly by setting a number either manually or by program control to select a particular block of lines for display.

Although the use of a television monitor has been indicated, display by panels of discrete neon or gallium phosphide lamps for displaying the serial output signal from embodiments of the invention. Serial to parallel conversion could be performed by circuits on the panels themselves.

What we claim is:

1. Signal monitoring and display apparatus including a group of signal input lines to be monitored carrying input signals representative of the current states of the elements to be monitored; at least one display converter module having a group of AND gates respectively corresponding each to a different one of the signal input lines each such line being connected to a first input of the corresponding AND gate, a common control line connected to second inputs of the AND gates the control line being energisable concurrently to render each and gate effective to produce an output signal related to the state of that one of the signal input lines to be monitored connected to its first input and sequential scanning means connectedconcurrently to receive the outputs from all said AND gates and arranged during a scanning operation to derive from said outputs an output data signal from the module having serial components representing in sequence the states of the elements to be monitored; the apparatus further including a display device having a plurality of spatially separated index positions and means for applying the output data signal from the module to the display device.

2. Signal monitoring and display apparatus, as claimed in claim 1, in which the scanning means of the module includes a shift register having a plurality of two state stages a separate register stage being provided for and associated respectively with a different one of the AND gates; a connection from each AND gate output to the input of its associated register stage; a shifting control means responsive to signals at a first repetition rate for shifting the states of the register stages along the register in one direction to a last register stage; and an output connection from the last stage of the register; said output data signal being produced on said output connection.

3. Signal monitoring and display apparatus comprising; means for producing pulsed signals; means for producing control signals; a group of signal input lines carrying input signals representative of the current states of the elements to be monitored; at least one converter display module for converting the information input signals into an output signal having serial components representing in sequence the states of the elements to be monitored; and a display device responsive to said data signal to provide spacially distinct indications of said serial components; the module including a group of AND gates each having first and second inputs and an output, and respectively corresponding to a different one of the signal input lines with each said input line connected to a first input of the corresponding AND gate a shift register having a plurality of two-state stages, therebeing one such stage for each register stage and the associated AND gate output; a common control line connected to receive the control signals and connected to the second inputs of all the AND gates, whereby the latter are energisable concurrently by said control signal to render each AND gate effective to set its associated register stage to one of its two states in dependence upon the state of that one of the signal input lines connected to its first input; said shift register being responsive to said pulsed signals for shifting the states of the register stages along the register in one direction towards a last register stage; and an output connection on which said output signal is produced from said last register stage and said display devices.

Claims

1. Signal monitoring and display apparatus including a group of signal input lines to be monitored carrying input signals representative of the current states of the elements to be monitored; at least one display converter module having a group of AND gates respectively corresponding each to a different one of the signal input lines each such line being connected to a first input of the corresponding AND gate, a common control line connected to second inputs of the AND gates the control line being energisable concurrently to render each and gate effective to produce an output signal related to the state of that one of the signal input lines to be monitored connected to its first input and sequential scanning means connected concurrently to receive the outputs from all said AND gates and arranged during a scanning operation to derive from said outputs an output data signal from the module having serial components representing in sequence the states of the elements to be monitored; the apparatus further including a display device having a plurality of spatially separated index positions and means for applying the output data signal from the module to the display device.