US3205488A

US3205488A - Cathode ray tube having resistor deflection control

Info

Publication number: US3205488A
Application number: US189848A
Authority: US
Inventors: Jr Clyde Lumpkin
Original assignee: International Business Machines Corp
Current assignee: International Business Machines Corp
Priority date: 1962-04-24
Filing date: 1962-04-24
Publication date: 1965-09-07
Anticipated expiration: 1982-09-07
Also published as: GB1009029A

Description

Sept. 7, 1965 c. LUMPKlN, JR 3,205,488

CATHQDE RAY TUBE HAVING RESISTOR DEFLECTION CONTROL Filed April 24, 1962 5 Sheets-Sheet 1 FIGJ 30 46 MAIN 42 54 38 WA POSITION x YOKE CONVERTER YOKE I Y YOKE \40 DRIVERS 156 32 CHARACTER VECTOR 44 YOKE DRIVERS 14 DATA PROCESSOR INTENSITY I DECODER 26/ AMP ANALOG 18 LEVEL 54 SYNTHESIZER TIME PERIOD DISTRIBUTOR INVENTOR CLYDE LUMPKIN, JR.

avz M y ATTORNEY Sept. 7, 1 965 c. LUMPKIN, JR

CATHODE RAY TUBE HAVING RESISTOR DEFLECTION CONTROL 5 Sheets-Sheet 2 Filed April 24, 1962 Sept. 7, 1965 c. LUMPKIN, JR 3,205,488

CATHODE RAY TUBE HAVING RESISTOR DEFLECTION CONTROL Filed April 24, 1962 3 Sheets-Sheet 5 222 FIG. 6

FIG. 5 i R12 FIG. 7

FIG.4 202 1 1 R6 R5 204 R3 19e R2 FIG. 3 501 TP-1 TP-2 TP'24 United States Patent ()ffice 3,245,488 Patented Sept. 7, 1965 3,205,488 CATHODE RAY TUBE HAVING RESISTOR DEFLECTION CONTRQL Clyde Lumpkin, J12, Tulsa, Ukla, assignor to International Business Machines Corporation, New York, N.Y., a

corporation of New York Filed Apr. 24, 1962, Ser. No. 189,848 2 Claims. ((11. 340-324) This invention relates to display systems and more particularly to apparatus for converting information output of a data processor or the like into visible form.

It has been recognized that, in a number of computer usages, visual output devices other than conventional electric typewriters and other electr-o-mechanical printers are desirable from the viewpoints of speed, flexibility, and economy. This is particularly so where the information is to be conveyed by means of special symbols, as Well as conventional alpha-numeric symbols, oriented with respect to a map or diagram, or for any other reason arranged in an arbitrary, information conveying spacial relation dictated by the computer.

Most computer output display systems employ a cathode ray tube or an analogous instrumentality as the device at which the display becomes visible, or in the chain of equipment which drives the output image producing device. One method of controlling a cathode ray tube so as to produce the image of a character is to deflect the electron beam of the tube so as to draw or write the character as a series of interconnecting line segments. It is of course possible to do this under direct computer control, through suitable, general purpose control circuitry. However, it is sometimes more economical to provide a character generator, between the computer and the cathode ray tube, which will produce a complete character upon a single command from the computer.

Character generators of this kind may comprise a switching apparatus or decoder which receives the instruction from the computer and gates a selected circuit subcombination into operation, so as to synthesize complex signals for operation of the X and Y deflection apparatus of the cathode ray tube to draw the selected character. However, prior art systems have not been without defects, particularly in respect to character style, flexibility, speed and economy.

In accordance with the present invention, an improved character generator is provided whereby characters can be drawn quickly and economically in close approximation to conventional type styles, or having arbitrary forms such as may be desired for special symbols and the like. Furthermore, the equipment is organized in such manner that the, so to speak dictionary of characters available in the equipment can be altered with unusual ease.

In one preferred embodiment of the invention, computer generated digital words identifying the characters to be displayed are decoded in succession, one word per character. The decoder circuitry activates a discrete circuit unit corresponding to the selected character. Conveniently, this special circuit unit may be packaged on a circuit card. The circuitry on the character card includes a signal level generator, comprising a transistor and a plurality of level control resistors, for each of the X and Y deflection driver circuits of the cathode ray tube. A time period distributor is arranged to index through connections to each generator on the card so as to connect one or another of the control resistors into the transistor circuit or to completely disable the level generator.

X and Y deflection drivers are provided which are common to all of the character cards, and comprise transistors connected to provide drives to the X and Y deflection circuits of the cathode ray tube in accordance with the X and Y level outputs of the character card in operation.

Means are provided to stabilize the rate of deflection eifected by each new deflection control level output. In the case of an electromagnetic deflection system, the yoke circuits of the cathode ray tube may each comprise a resistor shunting a yoke winding, which winding has inductance and distributed capacitance. Thus, the yoke circuits comprise resistance, inductance, and capacitance in parallel. The result is that, within each time unit, a reasonably uniform rate of deflection of the CRT beam is effected. However, the rate of deflect-ion is not constant from time unit to time unit. Rather, the deflection within a given time unit is a sweep to a display address determined quite arbitrarily by the value of the level generator control resistances called into play by the time period distributor during that time.

Accordingly, the apparatus enables deflection in any virtually desired amount in one time unit, and since this flexibility is available in both the X and Y directions, the resulting vectors can be not only of any arbitrary length but also of any arbitrary slope. These vectors are written one after another in rapid sequence with the start of each new vector being coincident with the end point of the previous vector, so as to enable the construction of a character having any desired configuration.

In most cases it is desired that means be provided for blanking the electron beam during portions of the character generating sequence, to avoid the creation of a trace or a retrace where none is desired. For this purpose an intensity control for the cathode ray tube is provided, activated by the decoder and operated by the time period distributor in synchronism with the activation and operation of the aforementioned deflection control level generators.

In many instances it is preferable to include the intensity control circuit for a given character on the card which mounts the deflection level generator circuits for that character. In this way characters can be added to, deleted from, or substituted in, the system by mere removal and addition of pluggable character cards on a onecard-per-character basis. However, the system is adaptable, where desired, to the provision of deflection control circuit units having the ability to generate vectors used in any of a number of characters, with a particular character being defined by blanking of certain of the vectors. In such case one deflection control card may be cooperative with any of several intensity control circuits, packaged separately.

Accordingly, it is a general object of this invention to provide an improved display system.

It is another object of this invention to provide a display system having a vector generator of improved simplicity and flexibility.

Still another object of the invention is to provide in a display system an improved vector generator as aforesaid which enables the generation of characters and symbols in a wide variety of styles and forms.

Yet another object of the invention is to provide a character generator for a display system as aforesaid having the capability of drawing a character by utilizing vectors having lengths and slopes which can be dictated with great freedom, so as to enable generation of characters of the desired style on a pre-programmed, economical basis.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.

FIG. 1 is a schematic diagram of a computer output display system embodying the invention;

FIG. 2 is a fragmentary detail of the system of FIG.

1, showing the circuit diagram of a typical character card in the analog level synthesizer, together with representations of certain associated parts of the system;

FIG. 3 is a schematic diagram of the time period distributor of the system of FIG. '1;

FIG. 4 is a diagram of a clipping circuit utilized in a control portion of the time period distributor;

FIG. 5 is a timing chart of the deflection driver and intensity signals synthesized by operation of the character card detailed in FIG. 2;

FIG. 6 is a vector diagram of a character generated by operation of the signals shown in FIG. 5, superimposed on a chart showing the basis of selection of certain control resistors for generation of that and other characters; and a FIG. 7 shows the application of the chart data of FIG. 6 to the generation of another character.

Referring more particularly to FIG. 1, a display system embodying the invention may include a digital computer or other suitable data processor 10 having an output 12 from which character selection commands issue. In the case of a character generator having the capability of drawing sixty-four different characters, these commands may be in the form of six bit binary words which are fed, one word at a time, to a six bit level decoder 14 of any conventional matrix or other desired kind.

The output of the decoder 14 in response to a given command is a significant level on a corresponding one of sixty-four lines in a cable 16, which connects the decoder to an analog level synthesizer 18 in accordance With the invention. As will be explained more fully hereinafter, the level or amplitude signal synthesizer 18 has another input, via cable 20 from a time period or timing signal distributor 22, and has X and Y deflection control level and intensity control level outputs at 24, 26 and 28, respectively.

The visual output device of the apparatus is a cathode ray tube 30, which may be of conventional design. The electron beam intensity control of the tube (i.e., the terminal of the control grid), indicated conventionally at 32, is energized via line 34 from the output of an amplifier 36 which, in turn, receives its input via line 28 from the analog level synthesizer 18. X and Y deflection yoke circuits 38, 40 for the tube 30 are responsive to main position and character

vector yoke drivers

42, 44, connected additively as shown. The main position yoke drivers 42 are driven by a conventional digital-to-analog converter 46 which receives its input via cable 48 from the computer 10, while the inputs of the character yoke drivers 44 are the

deflection level outputs

24, 26 of the analog level synthesizer 18.

FIG. 1 also shows, schematically, end of character and

intensity oiI connections

50, 52 between the analog level synthesizer '18 and the time period distributor 22, and character completed and start time period

distributor signal lines

54, 56 respectively to and from the computer 10.

As aforesaid, the circuitry of the analog level synthesizer 18 of FIG. 1 may be packaged conveniently on circuit cards, on a one-card-per-character basis. FIG. 2 shows the circuit diagram of one of those cards, 18R, in association with certain other circuit elements of the system of FIG. 1. The circuit on the card 18R includes a pair of transistors 60, 62 the collectors of which'supply, on output lines 64, 66, correponding series of current levels for execution of the X and Y deflections required for production of a particular character. Base control for the transistors 60, 62 is provided on lines 68, 70 from a particular line 16R of cable 16 from the decoder 14 of FIG. 1. As will be described more fully hereinafter card 18R also includes a third transistor 72, for intensity control, the base of which is also connected, via line 74, to line 16R.

With the particular NPN circuits shown in FIG. 2, the significant level on line 16R is ground, while the nonsignificant level on line 16R is a value sufficiently negative to maintain transistors 60, 62 and 72 in their non:conducting state. Accordingly, conditioning of the illustrated circuit card 16R for operation is effected by the establishment of a ground level on line 16R by the decoder.

The emitter circuits of transistors 60, 62 control the successive deflection current steps which are to be executed and are therefore unique to the particular character to be generated by card 18R. In this case, the emitter of transister 60 is supplied through four

resistors

76, 78, 80, 82 of different values, connected in parallel and thence to the emitter by line 84. Similarly, five resistors 86, 88, 90, 92, 94 of certain values are connected in parallel by line 96 to the emitter of transistor 62. As shown, the several emitter resistors are each connected through isolating diodes 98 to one or more output lines of the cable 20 from the time period distributor 22 of FIG. 1. For correlation, these output lines and their various branches are labeled TP-l, TP-2, etc., in accordance with the successive time periods during which they are active, that is, during which they carry the significant (in this case negative) utput level of the time period distributor 22.

The character to be generated by the illustrated circuit card 18R is drawn in nine steps; therefore only the first ten output lines of the time period distributor 22 are connected to the card, one for each of the nine steps plus one for signaling end of character.

The internal circuitry of the time period distributor 22 may be of any suitable kind having voltage level outputs which are switched in succession from their normal, nonsignificant value to the significant value required for operation of the circuits of FIG. 2. In the case of the illustrated circuitry, this significant signal is a closely controlled negative level, and the non-significant value is ground.

As shown in FIG. 3, the circuit of the time period distributor 22 may consist of an open ring counter comprising a string of interconnected flip-flops (bistable multivibrators) 100, 102, 104 driven by a pulse oscillator 106, under the control of a start flip-flop 108, an anti-slivering flip-flop 110, and a synchronizing flip-flop 112. A control pulse on any of

lines

108, and 112 is communicated via an OR circuit 114, line 115 and line 116 to set the synchronizing flip-flop 112 and clear all of the remaining flip-flops. This is the inoperative or quiescent condition of the distributor 22. For example, line 110 is provided for application of a pulse from any convenient source to assure this quiescent condition of the distributor 22 when power is brought on after having been off.

Subsequent application of a start time period distributor control pulse on line 56 from the computer 10 sets the start flip-flop 108, thus conditioning its associated gate 118. Oscillator 106 samples gate 118 with a constant succession of timing pulses on line 120. The first of these pulses to find gate 118 conditioned passes it and attempts to set the anti-slivering flip-flop 110, via line 122. If it is a complete pulse or a sufiicient sliver it succeeds, otherwise the next timing pulse, which will be complete, will set the flip-flop 110. This conditions gate 124 which then passes, on line 125, all subsequent timing pulses to the remaining

gates

126, 128, 130, 132 (until a control pulse again appears on line 116).

It will be recalled that the synchronizing flip-flop had been set by a pulse on line 116, so that its gate 126 is in a conditioned state when the first timing pulse to have passed gate 124 arrives. This pulse therefore appears on line 134 so as'to clear the synchronizing flip-flop 112 and set the next flip-flop 100. This switches the output on lineTP-l from its normal, non-significant ground level to its significant negative level, thereby initiating time period TP-l. The next timing pulse finds gate 128 conditioned and thus, via line 129, clears flip-flop 100 and sets flip-fiop 102, thereby terminating period TP-l and initiating period TP2. Unless interrupted, this sequence of events ripples through the counter until the last flip-flop 104 is set. The timing pulse thereafter passed by its gate 132 is operative via line 138 not only to clear flip-flop 104 via line 140 and thus terminate the last time period (in this case TP-24), but also via line 112 to return the time period distributor to its quiescent condition.

As the time pulse distributor imposes a negative level on successive ones of its output lines TP-l, TP2 and so on, the circuit 18R of FIG. 2, if selected for operation by a ground level on its conditioning input line 16R, is responsive to gate a succession of current levels on its X and Y deflection control output lines 64, 66. These current steps are fed, via

respective buses

148, 149 and

output lines

24, 26 of the synthesizer 18, to the emitters of corresponding X and Y

yoke driver transistors

150, 152 of the character vector yoke driver circuit 44. The bases of these

transistors

150, 152 are each connected to a positive voltage supply V1.

The

driver transistors

150, 152 act as buffers, and faithfully reproduce at their respective collectors the emitter currents fed to them. These collector outputs are connected as shown to

lines

154, 156 which feed the respective X and Y deflection or yoke circuits 38, 40 of the cathode ray tube 30. The X deflection circuit 38 consists of the X deflection yoke winding 158 shunted by a resistance 160 as well as by the distributed capacity 162 of the winding 158. Similarly, the Y deflection circuit 40 consists of the Y deflection yoke winding or coil 164 shunted by a resistance 166 and the distributed capacity 168 of the winding 164. As shown, the X and Y deflection circuits 38, 40, are terminated in a connection to a voltage supply V2. This supply is more positive than supply V1, and serves as the collector supply for the character vector

deflection driver transistors

150, 152 as well as for their counterparts (not shown) in the main position deflection driver circuit 42 (FIG. 1).

When a deflection current of a new value is imposed on yoke

driver output line

154 or 156, the initial change is absorbed primarily by the resistance and capacitance shunting the associated yoke winding 158 or 164. As the yoke winding impedance drops, more of the current change appears in the winding, with the shunting (distributed) capacity 162 or 168 of the winding being operative to linearize what would otherwise be a simple R-L exponential rate of change. Accordingly, the successive X and Y deflection current steps delivered to the X and Y deflection circuits 38, 40 by operation of a character circuit unit or card of the apparatus, such as the card 18R above described, cause the currents in the respective deflection windings 158, 164 to change at reasonably linear time rates to approximately the new level of each new step. If the electron beam of the cathode ray tube 38 is unblanked during these changes, the traces resulting are seen as interconnecting vectors on the face or screen of the cathode ray tube 30.

Means are provided to control the intensity of the electron beam of cathode ray tube in coordination with operation of the above described character deflection controls. As aforesaid, these means can be separate from the character deflection level generators so as to enable multiple use of those generators for the writing of several different characters.

However, in the illustrated embodiment of the invention, the intensity level controls for the writing of a particular character are associated on a one-for-one basis with the corresponding deflection controls and may be on the same circuit cards, so that changes in the dictionary of available characters are facilitated. Accordingly, the circuit unit 18R of FIG. 2 includes the aforementioned transistor 72, connected as a gate for activating a control network arranged to provide an intensity control signal appropriate to the function of circuit card 18R. The collector of this transistor is grounded by a connection 170, and its base is connected by line 74 to the decoder output line 16R. The emitter of transistor 72 is connected through a load resistor 172 via line 174 to a current switching network including individual diode connections 176 to certain of the time pulse distributor output lines. For generation of the particular character of circuit unit 18R, diode connections 176 are provided to the time pulse distributor outputs TP-l through TP-7 and TP, but not TP-8.

' Line 174 is connected also through an isolating diode 17 8 to a bus 180, which is connected via line 182 to the intensity output line 28 of the analog level synthesizer 18. Line 182 is connected through a resistor 184 to a negative voltage supply V3, and, via a diode 186 and line 52 to the time period distributor 22 (FIGS. 1 and 3). During character generation, the potential on line 182 and thus on output line 28 is determined by the drop across resistor 184, since the value of V3 is at all times fixed.

The intensity amplifier 36 is a video amplifier having a high input impedance, so that, ignoring for the moment the connection from line 52 through diode 186, the current passing through resistor 184 comes entirely from line 182. Assuming that transistor 72 is conditioned, that is placed in a conducting state, by the presence of a ground level on its base control line '74, current flows from the emitter of transistor 72 at a rate which is determined by the potential on line 174 and the value of the emitter resistor 172 of transistor 72. During time period TP-8, all of diodes 176 are back-biased so that all of this current passes through diode 178, bus 188, line 182 and resistor 184. Stated otherwise, at the above assumed moment, transistor 72 has an emitter load consisting of resistors 1'72 and 184 connected in series as a voltage divider, with the output on line 28 being taken at the tap between them.

The values of supply V3 and resistors 172 and 184 are such that when one of the time period distributor lines TP-1 through TP7 and TP-9 is at its negative significant level, the associated diode 176 is forward-biased, thereby clamping line 174 at that negative level. In other words, the aforementioned values are such that the potential on line 174 undergoes a negative shift.

Preferably, the value of supply V3 is still more negative, so that diode 178 continues to be forward-biased, and the full negative shift on line 174 is propagated to line 182. The intensity amplifier 36 has an odd number of inverter stages so that this negative shift on line 182, communicated to amplifier 36 by line 28, is operative to produce a positive-going shift in the voltage applied to the control grid connection 32 of the cathode ray tube 38. Conversely, when

lines

174, 182 and 28 move to their more positive value, the amplifier 36 is operative to impress a negative-going voltage shift at 32. In the illustrated embodiment of the invention the intensity control has only two operative states, unblank and blank, and therefore the amplifier 36 is constructed and adjusted to provide the desired electron beam intensifying and cut-off, relatively positive and negative, levels at the control grid terminal 32.

It will be observed that the intensity control circuit of FIG. 2 is a current switching circuit whereby a first current path is established which is operative to blank the electron beam of the cathode ray tube, and second current paths are established successively during the time periods when it is desired to unblank that electron beam. In effect, the second current paths operate by diverting current from the first path. If for any reason it is desired to provide intermediate intensifications between the extremes of blank and full intensity, this circuit lends itself easily to that refinement. Such intermediate intensification can be provided by merely interposing a resistor of appropriate value in series with the diode 176 connected to the time period distributor line corresponding to that period during which such intermediate intensification is desired.

Means are provided to fix the intensification output of amplifier 36 at a CRT beam blanking level whenever the character generator of the invention is not operating to write a character. This condition is referred to hereinafter as the intensity ofl state.

In the illustrated circuit this means is provided by the connection of line 52 through diode 186 to output line 28 of the analog level synthesizer 18. As shown in FIG. ,3, line 52 is connected to the synchronizing flip-flop 112, so as to be maintained at a negative level by the flip-flop whenever the latter is in its cleared condition.

It will be recalled that flip-flop 112 is in its cleared state during time periods TP-l through TP-24 of the operation of the distributor 22. At all other times, flipflop 112 is set and therefore maintains line 52 at ground.

Diode 186 of the intensification control circuit of FIG. 2 is back-biased by the negative level on line 52 during generation of a character and therefore this connection has no effect on the intensification control circuit during that time. When generation of a character is finished and operation of the time period distributor 22 is terminated, the ground level thereupon impressed on line 52 by flip-flop 112 clamps line 28 to ground and thereby drives the output of amplifier 36 to its intensification 1 off condition.

Means are provided to synchronize operation of the time period distributor 22 with the needs of the system. Referring again to FIG. 1, any convenient means may be provided for starting the time period distributor 22 in properly timed sequence after a character command has been issued from the data processor 10 and decoded; in other words, after one of the character circuit cards or units of analog level synthesizer 18 has been conditioned by a significant ground level on a corresponding line of output cable 16 of decoder 14. In the illustrated scheme, this is accomplished by an appropriately programmed output pulse on a command line 56, directly from the computer 10, connected as shown in FIG. 3 to set the start flip flop 103 of the time period distributor 22. Alternatively, this signal could be derived from the decoder 14, by means of conventional circuitry operable by and upon the receipt or decoding of each new character command from the computer.

Ordinarily, most of the character circuit units or'cards of the level synthesizer 18 require less than the maximum number of time periods available from the distributor 22 to generate their respective characters. To speed operation of the system, each such circuit unit has an end of character output elfective to provide a signal on line 50, FIGS. 1, 2 and 3, when generation of its character is completed.

In the circuitry of card 18R detailed in FIG. 2, this output is provided by means which overdrive the X de fiection generator of the character card. For this purpose transistor 60 of FIG. 2 has an additional emitter control resistor 190, connected as shown to time period distributor output line TP-10, and a resistor 192 is interposed in the -X deflection output line 24 to provide a voltage signal on line 50 which is a function of the X deflection current level on line 24. The value of emitter control resistor 190 of transistor 60 is such that the X deflection current passed by that transistor to line 64, bus 148, and line 24 upon the-initiation of time period TP-10 is substantially more than the maximum ever utilized in actually drawing a character. This overdrive of the X deflection system causes the potential on line 50 to fall below a predetermined value.

The illustrated system includes means responsive to this negative-going excursion of the signal on line 50 to reset the time period distributor 22 to its quiescent condition. For this purpose, the reset controls of the time period distributor shown in FIG. 3 include a clipping circuit 196 which is operative to provide a potential shift on line 198, by and upon above-described voltage excursion on line 50. This shift on line 198 is converted into a'pulse by a suitable differentiating or other pulse forming circuit 200. This pulse, on line 108, is operative as aforedescribed to reset the time period distributor 22 to its quiescent condition.

An example of a suitable configuration for the clipping circuit 196 is shown in FIG. 4. In that figure, junction 202 is normally clamped through a diode 204 to a discriminating level provided by supply V4, diode 204 being maintained normally in forward-biased condition by a more positive supply V1 to which junction 202is connected by a resistor 206. When the potential on line 50 falls below the value of supply V4, diode 208 becomes forward-biased, and junction 202 becomes clamped to the level on line 50. When the X deflection circuit of FIG. 2 is overdriven in the manner aforedescribed for signalling end of character, the potential on line 50 falls abruptly below the value of V4, whereby a potential step is provided on the output line 198 of the clipping circuit.

It will be recalled that if the time period distributor 22 is allowed to ripple through its complete operation, a pulse appears on line 112 at the end of time period TP24. Accordingly, whether the completion of a character is signalled by a pulse on line 108 in response to an end of character signal on line 50 as abovedescribed, or whether the character generated utilizes the full num ber of stages of the time period distributor through TP-24 and therefore has its completion signalled by a pulse on line 112, a pulse is passed by OR circuit 114 to line 115 at the end of generation of the character. Accordingly, line 115 is a convenient place to take an end of character signal for communicating this fact to the computer 10, and this is done in the illustrated scheme of FIGS. 1 and 3 by the connection of line 54 to line 115.

The circuit of card 18R of FIG. 2 is operative to generate an R as diagrammed in FIG; 6. For display of this character, a corresponding command, issued from the computer 10 via cable 12 and decoded at 14, is operative to place a ground level on decoder output line 16R. Initially, all of the time period output lines TP-l, etc., of the time period distributor being at their nonsignificant (ground) level, there is no emitter current through deflection control transistors 60, 62. Therefore, the X and Y deflection control current levels on

output lines

24, 26 stand at zero.

A command pulse on line 56 from the computer 10 then starts the time period distributor 22. Upon the initiation of time period TP-l, the negative level of the time period distributor is communicated through the associated diode 98 and emitter resistor 86 to turn the Y deflection control transistor 62 on,'to a degree dictated by the value of the resistor 86. This results in the generation of a Y deflection control current step on line 26, as indicated at 210 in FIG. 5. Meanwhile, there being no TP-l connection to the X deflection control transistor 60, the output current on line 24 remains at zero, as indicated at 212 in FIG. 5.

Coincident with the initiation of time period TP-l, the synchronizing flip-flop 112 (FIG. 3 is cleared, thereby dropping the potential on line 52 so as to enable the intensity control circuit of FIG. 2. At the same time, the

significant negative level appears on line TP-l (FIGS. 2

and 3) and operates the intensification control circuitry to unblank electron beam of the cathode ray tube 30, as indicated at 214 in FIG. 5. Accordingly, as shown in FIG. 6, the electron beam of the cathode ray tube is intensified and deflected in the Y direction Whileexperiencing no deflection in the X direction, so as to execute a trace or vector 216 in the vertical of Y direction on the screen of the cathode ray tube 30. The length of this trace 216 is determined by the value of the Y deflection current step 210, which, in turn, is determined .by the emitter resistor 86 (FIG. 2) which is effective during time period TP-1.

During time period TP-2, this Y control emitter resistor 86 continues to control operationof transistor 62, by reason of its connection to time period distributor output line TP-2, and the intensification control circuit continues to be active to intensify the electron beam of the cathode ray tube by reason of its connection to line TP-2. However, at the initiation of time period TP-2, the current in the X deflection control line 24 (FIG. 2) is altered from its zero condition by the fact that resistor '76 becomes connected to the negative significant level of the time period distributor, thereby turning on the X deflection control transistor 60 with a force dictated by the value of resistor 76.

This produces a step 218 (FIG. 5) in the X deflection control current, resulting in a horizontal or X direction vector 220 (FIG. 6) being written by the electron beam of a cathode ray tube. By inspection of FIGS. 5 and 6 in conjunction with FIG. 2, it will be seen that during the succeeding time periods TP3, TP-4, TP-S, TP-6, and TP7 a connecting series of

vectors

222, 224, 226, 228, 230 is written.

For producing the character form desired, the next step is to reposition the electron beam for initiating the final trace or vector 232 in the character, without producing a retrace between the end of vector 230 and the beginning of vector 232. This is accomplished by omitting connection of distributor output line TP-S to the intensification circuit of FIG. 2, and at the same time establishing the deflection control circuits through emitter resistor 82, 94 (FIG. 2) of the proper value.

Accordingly, during time period TP8 the electron beam is blanked as indicated at 234, FIG. 5, the Y deflection current is held at its previous level 236, and the X deflec tion current is fixed at the proper level 238. This results in a blanked repositioning of the electron beam system of the cathode ray tube, as indicated at 240, FIG. 6. Thus, by the end of time period TP8, the yoke winding currents of the cathode ray tube have been brought to levels appropriate for commencing the final vector 232 of the character, which is then drawn during period TP-9 by operation of the deflection control levels and intensification indicated at 242, 244, 246 in FIG. 5.

At the beginning of time period TP-10, generation of the desired character R having been completed, the end of character circuit is activated by the establishment of X deflection current through emitter resistor 190 of X deflection control transistor 60 (FIG. 2). Thus, in the manner aforedescribed, the time period distributor 22 (FIGS. 1 and 3) is reset to its quiescent condition, establishing a ground level on output line 52 of the synchronizing flip-flop 112 of the distributor so as to disable the intensity circuit of the analog level synthesizer 18, FIGS. 1 and 2. This action is indicated in FIG. 5 by the X deflection control overdrive spike 248 and the return of the intensity system to its off condition, at 250. It should be noted that the overdrive spike 248 is not operative to produce a trace; not only is the intensity control brought to its blank condition by the omission of any diode 176 branch circuit connection to line TP-10 in the intensity control circuit, but also the end of character I signal resulting from the spike 248, by resetting the time period distributor 22 to its quiescent condition, is operative to terminate the spike 248 and return the X deflection control current quickly to Zero, as indicated at 252, FIG. 5.

The character R is diagramrned in FIG. 6 on a coordinate array representative of certain resistance values suitable for use in the deflection control emitter circuits of FIG. 2. Relating this figure to FIG. 2, the emitter control resistor 86 for executing Y direction trace 216 has the value R12. The same emitter resistor value (in fact the same resistor 86) holds this Y deflection during time period TP-Z, while X deflection control emitter resistor 76 having a value of R5 comes into play, to execute the second vector 220. During time period TP-3 a sloping vector 222 is required, and this is executed by utilization of Y deflection emitter control resistor 88 having a value of R11 and X control resistor 78 having a value of R6. The same basis of selection of emitter control resist- 10 ances is continued throughout the generation of the character.

The indicated emitter control resistor value for X deflection of the first vector 216 and Y deflection of the last vector 232 is R0 which is infinite. This value is provided in circuit 18R of FIG. 2 simply by omission of a circuit connection between time period distributor output line TP1 and the emitter of transistor 60, and omission of a connection between line TP-9 and the emitter of transistor 62.

Accordingly, it will be seen that the character card designer can provide for the generation of vector traces or blanked repositionings in any direction and length desired, simply by providing the required emitter control resistors in the deflection circuits and the required control connections in the intensity circuit, for each time period utilized in generation of the character. Furthermore, the designer can utilize more or fewer time period steps in accordance with the needs of the character configuration, up to the limit of the number of time periods in the distributor provided, it being necessary only to provide the corresponding taps from the time period distributor output cable 20 to the character card. Lastly, it should be noted that the resistance steps available to the character card designer are not restricted to the thirteen shown in the coordinate diagram of FIG. 6; any degree of fineness of character design could be provided by utilization of intermediate resistance choices.

Suitable components and values for the circuits detailed in FIGS. 2 and 4 as described above are as follows:

Diodes (all) Transitron T6.

Transistors 60, 66 2N706.

Transistors

150, 152 2N697.

Resistor 76 1360 ohms (R5).

Resistor 78 970 ohms (R7).

Resistor 80 850 ohms (R8).

Resistor 82 2670 ohms (R3).

Resistor 86 565 ohms (R12).

Resistor 88 620 ohms (R11).

Resistor 90 755 ohms (R9).

Resistor 92 970 ohms (R7 Resistor 94 1130 ohms (R6).

Resistor 1000 ohm variable, ad justed f o r critical damping of associat ed yoke winding 158 and its distributor capacity 162.

Resistor 166 1000 ohm variable, ad-

justed for critical damping of associated yoke Winding 164 and its distributor capacity 168.

Resistor 172 560 ohms.

Resistor 184 1500 ohms.

Resistor 390 ohms.

Resistor 192 200 ohms Resistor 206 2000 ohms,

Voltage supply V1 Plus 9.5 volts.

Voltage supply V2 Plus 24 volts.

Voltage supply V3 Minus 15 volts.

zolltage supply V4 Plus 4 volts.

0 c winding 162 Yoke winding 164 i celco 87*2000 Decoder 14 output on lines of cable 16 (e.g. line 16R):

Significant Ground. Non-significant Minus 12 volts.

Time period distributor output on lines TP-l through Significant Minus 12 volts. Non-significant Ground. Flip-flop 112 output on line 52:

Flip-flop 112 set Ground. Flip-flop 112 cleared Minus 12 volts.

With a timing pulse repetition rate of two hundred fifty kilocycles from the oscillator 166, character vectors are swept in about 4 micro-seconds each. The flip-flops should be of a high speed type so as to resolve in a small fraction of this time, to avoid such overlap or hiatus between time period outputs TP-1, TP2, etc. as would degrade the desired heel-to-toe interconnection of the character vectors. For desired driving capability, fourtransistor flip-flops are preferred, that is, the type having two cross coupled inverters with emitter follower outputs. For pulse dodging, that is for delaying switching of the flip-flop by a pulse passed'by its conditioned gate until the end of that pulse, as well as for delaying switching of the next flip flop until the timing pulse has died, it is pre ferred that the set and clear inputs of the flip-flops be of the type which are sensitive to the trailing edge of the pulses applied to them. 7

It will be recalled that the illustrated system is organized on a one-card-per-character basis, and that, for purposes of explanation, it was assumed that the system is capable of displaying sixty-four different characters. Accordingly, in addition to the character card 18R, the analog level synthesizer 18 contains sixty-three other character cards. FIG. 2 shows the relationship of such other cards in the organization of the analog level synthesizer 18 by the schematic inclusion of a second typical character card, 18Q. In exact analogy to the

connections

16R, 64, 66 and 179 of card 18R, card 18Q is connected to line 16Q of decoder output cable 16, and has X deflection, Y deflection and intensity

control output lines

264, 266, 279 connected to

buses

148, 149 and 186 of the analog level synthesizer. The time period distributor output line connections to card 18Q, indicated'generally at 290, start with line TP-l as in the case of card 18R and every other character card in the synthesizer, but continue upwardly in time period number in accordance with the number'of vectors and blanked repositionings required for generation of the particular character of the card, plus one for an end of character signal, if any.

For example, if the character card 18Q is constructed to produce a Q as diagrammed in FIG. 7, connections 290 are made to time period distributor lines TP-l through TP-16, and deflection control transistor emitter resistors, as above defined and explained, are utilized as set forth in the following table:

Time Pe- Intensifiriod Dis- X Defiec- Y Defleccation Vector (Fig. 7) tributor tion Emittion Emit- Unblank 7 Output ter Reter Re- Connec- Line Consistor sistor tion neetion am TP-i Rn Ra N 303 TF4 R1 R11 Yes.

304 TP-4 R's R12 Yes.

307 TP-7 R8 R9 Yes.

308 TP-S R2 122 Yes.

309 TP- R7 R1 Yes.

310 TP-m R; R Yes.

311 TP-ii Ra no Yes.

an TP-t's Rn Ba Ye "End of Character 4 Signal TP16 390 ohms R0 N0.

Each of the characters diagrammed in FIGS. 6 and 7 begin at bottom left-hand corner of a uniform rectangle, blanked deflection 301 being provided in the character generation in accordance with FIG. 7 for conforming to.

From the foregoing it will be seen that the invention provides a character generating system characterized by unusual freedom in design of character form, by ease of change in the dictionary of available characters, by capability of high speed operation, and by economy in its demands upon the. command source such as the data processor digital'computer 10 of, FIG. 1. The analog level synthesizer 18 embodies in effect, itsown wired program, which may be organized as aforedescribed on a character-by-character basis. In any event, it contains X and Y deflection control level generators and intensity control level generators the operation of which is readily tailor-made to the requirements of the characters which are to be drawn.

It will be understood that various changes and modifications can be made in the system within the spirit and teaching of the invention. Thus, while the illustrated scheme of deflection control is by choice of emitter resistors and the illustrated means of intensity control is by diversion of currents through branched emitter circuits, it will be understood that either general type of control could be used for both purposes. Where the current diversion technique is to be used for generation of more than two levels of output, as it would be if it were used in the deflection circuits, control resistors can be utilized in the current diverting branches as described above.

As referred to above, if for example the deflection control and intensity control circuits are separated, it is possible to make deflection control circuits do double duty in what is generally known as the double hung window manner. Thus, if the electron beam were blanked during the final vector deflections of the above described characters R and Q, these characters would become P and 0. Therefore, the four characters R, Q, P, and 0 could be executed with only two deflection control circuit units and two intensity control circuits. Similarly, circuitry could be introduced in the illustrated system to terminate operation of the time period distributor prematurely, in response to a particular command to the decoder 14, so as to convert what would otherwise be an R into a v1, a Q into an O, and so on in character groupings wherein there may be identity of vectors.

Also, itshould be noted that the illustratedcathode ray tube 30 could be a direct view or projection type, or it could be part of a storage tube, in accordance with system requirements.

Thus, while the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.

What is claimed is:

1. In a character generating system,

a cathode ray tube,

analog signal synthesizer means comprising a plurality of circuit units for selective operation in the generation of various characters,

character designating control means connected to said synthesizer means to condition said circuit units for operation selectively, 4

each said circuit unit comprising a level generator,

said level generator comprising a level control transistor having an on-off conditioning input connected to its base and responsive to said designating control means and an emitter-collector circuit including a plurality of control branches connected in parallel to the emitter of said transistor, each said branch including an emitter load for establishing a predetermined emitter current through-said transistor by and during activation of said branch,

timing signal distributor means connected to each of said level generators for activating said control branches in succession, and

I control means for said'cathode ray tube connected to be responsive to said level generators for causing the electron beam of said cathode ray tube to execute operations in accordance with the output of said synthesizer means.

2. In a character generating system,

a cathode ray tube,

character designating control means connected to said synthesizer means to condition said circuit units for operation selectively,

each said circuit unit comprising a current gate comprising a transistor having an on-ofl conditioning input connected to its base and responsive to said designating control means and an emitter circuit comprising a plurality of branches,

each branch including an emitter load resistor of a value adapted to determine the output current level signal of the corresponding gate at a uniquely predetermined level within the range of levels of which the gate is capable,

timing control distributor means connected to each of said gates for activating said branches in succession, and

deflection means for said cathode ray tube connected to said gates, said deflection means being responsive to each successive level signal to effect a deflection of the electron beam of said cathode ray tube to an address corresponding to the amplitude of said level signal.

References Cited by the Examiner UNITED STATES PATENTS 2,679,035 5/54 Daniels et al. 340-324.1 2,931,022 3/60 Triest 340-3241 2,987,715 6/61 Jones et al. 340324.1 3,020,530 2/62 Volberg 340324.1 3,047,851 7/62 Palmiter 340-324.l 3,090,041 5/63 Dell 340324.l

NEIL C. READ, Primary Examiner.

Claims

1. IN A CHARACTER GENERATING SYSTEM, A CATHODE RAY TUBE, ANALOG SIGNAL SYNTHESIZER MEANS COMPRISING A PLURALITY OF CIRCUIT UNITS FOR SELECTIVE OPERATION IN THE GENERATION OF VARIOUS CHARACTERS, CHARACTER DESIGNATING CONTROL MEANS CONNECTED TO SAID SYNTHESIZER MEANS TO CONDITION SAID CIRCUIT UNITS FOR OPERATION SELECTIVELY, EACH SAID CIRCUIT UNIT COMPRISING A LEVEL GENERATOR, SAID LEVEL GENERATOR COMPRISING A LEVEL CONTRL TRANSISTOR HAVING AN ON-OFF CONDITIONING INPUT CONNECTED TO ITS BASE AND RESPONSIVE TO SAID DESIGNATING CONTROL MEANS AND AN EMITTER-COLLECTOR CIRCUIT INCLUDING A PLURALITY OF CONTROL BRANCHES DCONNECTED IN PARALLEL TO THE EMITTER OFSAID TRANSISTOR, EACH SAID BRANCH INCLUDING AN EMITTER LOAD FOR ESTABLISHING A PREDETERMINED EMITTER CURRENT THROUGH SAID TRANSISTOR BY AND DURING ACTIVATION OF SAID BRANCH, TIMING SIGNAL DISTRIBUTOR MEANS CONNECTED TO EACH OF SAID LEVEL GENERATORS FOR ACTIVATING SAID CONTROL BRANCHES IN SUCCESSION, AND CONTROL MEANS FOR SAID CATHODE RAY TUBE CONNE TED TO BE RESPONSIVE TO SAID LEVEL GENERATORS FOR CAUSING THE ELECTRON BEAM OF SAID CATHODE RAY TUBE TO EXECUTE OPERATIONS IN ACCORDANCE WITH THE OUTPUT OF SAID SYNTHESIZER MEANS.