US3728710A

US3728710A - Character display terminal

Info

Publication number: US3728710A
Application number: US00881105A
Authority: US
Inventors: N Berg
Original assignee: Hendrix Wire and Cable Inc
Current assignee: Hendrix Wire and Cable Inc
Priority date: 1969-12-01
Filing date: 1969-12-01
Publication date: 1973-04-17
Anticipated expiration: 1990-04-17

Abstract

A synchronous refresh memory CRT Display Terminal continuously generates the individual deflection waveforms for the complete repetoire of characters and symbols which it is desired to display. The recirculating memory provides storage for the identity code and editing tags for each character position on the CRT display and recirculation in the memory loop is synchronized with a character by character beam deflection of the CRT to provide a page format indication. Provision is made for reading into the memory loop the character identity code at a preselected position corresponding to the screen character location at which the character is to be displayed and once in memory the refresh rate will continually display the character sequence in the memory loop in the corresponding sequence of character positions on the screen format with only the code address for each character being read from memory and upon decoding selecting from the repetoire character generator each so identified character for display by the continuously generated fine waveform deflection signals. An active and dormant cursor are presented on the screen generated in the same manner as any character or symbol but controllable as to position at will to identify the screen location for insertion and deletions. Editing controls for the cursors and the insertion and deletion operations independent of memory permit a full range of editing functions to be performed on the character content of the memory and display screen.

Description

United States Patent Primary Examiner-John W. Caldwell Assistant Examiner-Marshall M. Curtis Atmmey-Frederick D. Goode MHZ MASYER CLOCK l4-| 2 STATE an TIMER i LOAD X ADDRESS 86 SWAP F REGISTER cox ADDRESS {84 *[cti'dixmoputs toonmmv ICOLUM" (.DV ADDkESS A L093 ADDRESS COMPARk Berg [451 Apr. 17, 1973 [54] CHARACTER DISPLAY TERMINAL [75] Inventor: Nephi Edward Berg, Bedford, NH. [57] ABSTRACT [73] Assignee: Hendrix Wire & Cable Corp., Mil- A syfchronous rfresh memory ,Display Termifal ford NH. continuously generates the individual deflection waveforms for the complete repetoire of characters [22] Filed: Dec. 1, 1969 and symbols which it is desired to display. The recirculatin memor rovides stora e for the identit [21] Appl' ssllos code aid editing tags for each c aracter position 01 i R l Us; Appficafion Data the CRT display and recirculation in the memory loop is synchronized with a character by character beam [63] Continuation-impart of Ser. Nos. 587,583, Oct. 18, deflection of the CRT to provide a page format indica 1966'and s3s's9ljune tion. Provision is made for reading into the memory loop the character identity code at a preselected posi- [52] Cl "340/324 340/152 340/1725 tion corresponding to the screen character location at [51] Int. Cl ..G06f 3/14 which the character is to be displayed and once in [58] Field of Search ..340/324, 152-15}, memory the f h rate will continually display the 340/1725 character sequence in the memory loop in the corresponding sequence of character positions on the References Cited screen format with only the code address for each character being read from memory and upon decoding UNITED STATES mfl-ENTS selecting from the repetoire character generator each 3,345,458 10/1967 Cole et al. ..340/324 A so identified character for p y y the Continuously 3,394,366 7/ 1968 Dye ..340/324 A generated fine waveform deflection signals. An active 3,394,367 7/1968 Dye ..340/324 A and dormant cursor are presented on the screen 3 968 S out --3 0/32 A generated in the same manner as any character or $500,332 3/1970 -340/324 A symbol but controllable as to position at will to identi- 3,505,665 4/1970 Lasofi et al ..340/153 fy the Screen location for insertion and deletions. Edit 3'555'538 H1971 Henderson "340/324 A ing controls for the cursors and the insertion and dele- 3.307.l56 2/1967 Durr ..340/324 A tion operations independent of memory permit a full range of editing functions to be performed on the character content of the memory and display screen.

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SHEET mar 14 {I SECOND sR FIRsT SR IR I I I2 BIT 7 l2 BIT 2' I t II I2 BITS INPUT 73- LOOP 912 REGISTER REGISTER DLi A l T EDITING LOGIC a CONTROL I I A JINPUT CHAR FEED- SHIFT I ASU;ASDL 55 REG.) READY BACK 6O GATE I YASRMSL To IUIIEUD LOOP INTERFACE i BIi- TRANS- ICONTRDLI \DSU-;DSD 54\HBI9 EBR FER CODE OUTPUTS LOOP DSR;DSL EXCHANGE BUFFER Eng To FIG. 18 B11- EB L81 53\HBI9 wRITE 5M2 L512 I/O CONTROL KBR KEYBOARD CONTROL LOGIC KB EAD RST 1K1.

KDN DATA IK12 sD M 5| KEYBOARD HARD l COPY RD BITs -I DRUM a DATASET HARD COPY ARD COPY zos- INTERFACE coDINs :4: 'E'DNTROI.

I /o CONTROL 1 4 Z oDATA IDATA BA BB 05 DRUM OR DIsI TELEPHONE FILE DATASET -zo6 7.07

INvENToR ATTORNEYS 0 IBM 735 1A SELECTRIC P-MENTED 3,728,710

SHEET [)2 HF 14 l2 l3 I l r =|.5 MHz MASTER CLOCK To |4- I2 STATE I6 STATE l v T n -'712 T TO-T15 BIT TIMER STROKE KHZ TIMER LOAD 1 ADDRESS FROM cOLuMN ASWASDT cuRSOR MODULE cuRSOR MODULE ASR;ASL) x Y CM 'DSU D 7 (ACTIVE) (ACTIVE) -/ADDRESS LOAD x DSmDSL ADDRESS as m 8|) 4712 FROM w FC FIG 1A SWAP xw HIGH SPEED STAIRCASE REGISTER 3g cOuNTER GENERATOR 0 .BL J CDX 4 35 'ADDRESS 84 85 L812 I FROM 7 CURSOR MODULE cuRSOR MODULE FIG.1A x Y,

(DORMANT) COEUMN (D RMANT) T To CDY ADDRESS COMPARE FIG. 1c

f" BL x STA|R Y STA|R xF|NE- FROM Y FIG. 1C

' BLANK FROM O FIG.1C

. INT |NvENTOR NEPHI' E. BERG BY FIG. 1B

, ATTORNEYS PATENTEDAPR 1 H918 3.728.710

sum on or 14;

RING CTR.

SQUARE PULSE GRAPHICS GEN.

GRAPHICS FIG.2.E

PATENTEU 1 H915 3.728.710

SHEET 08 0F 14 76 STROBE 1 s T g a ONE KEY F GEN KDN -Ke WRITE (GATE) COMPARE J H STROBE 2 7 STROBE cf COMPARE- KBR FIG. 5C

KBR'

IK2 K82 K82 IK12 K812 K812" KB WRITE COMPARE CHG CUR

, -A to SWF PATENTEDAPR17|973 3.728.710

sum 11 or 14 I FIG. 7 REM ERASE ERASE FIG. 9 x HOME cuR sg z l xcTlvE DELAY CL 63min L 35 55 CLL I57 LATCH I58 T0 FIG-8 CLR BL ERASE BEGIN LINE BEGIN FRAME BF I I36) 137 BBL 4| :42 :43 [I44 [I45 cL-s- [i) -ERASE :39 FIG 8 15 OTHER SETS ERASE LATCH OTHER CLEARS LATCH Fc -Q VERASE' 15: I52 me DORMANCTDCURSOR l6! |s2 3 D 0 SET ERASE CLL 3 LATCH 4 '65 V HG '0 CA FLCLR ERASE CURSOR ACTIVE x SWAP ib-film) T0 CA CURSOR I72 LATCH 78 I68 FIG u m TO CLEAR LINE we (TOP P 25 we sen '93 RU l'LL EL S Q SQME LATCH fi 'PX'T'E'J CAX a CAY) F "32 LINH VERT(c|nd I04) CA I (um-"ans TO LAST LINE Y CARRY (AT LEFT nus TO RU PULSE) OF FIRST LINE) 8L CA TO LAST LINE 1 R nae I87 (I88 I89 I9! 1192 D 3 cm VERT SET RD LATCH SET ERASE (FIG. 9) FROM FIG.9

HOME C; l 1

FIG. l2

PATENTEI] APR I 7 I973 sum 13 0F 14 (a) '712 (b) BF J BF =Begin Frame-6O cps (c) FC 1 FC: Frame Clock-6O cps (d) BL H n BL=Begin Line 2400 cps (40 Lines) (f) CA Home IL CA -Cursor AcIive- Can Locate on Any Line from Sfh to 54th I Char. Space AMPLITUDE 3 CHfisllgTER ADJUSTABLE (g) X Stair 52 STEPS u- MARGIN (h) Y Stair 207 20' 2 X FINE REFERENCE 204\ 208 23 FIG. |6A VQLTAGE D/A D/A I o o o 0 V f CH0 CH1 CH2 CH3 DIGITAL DIGITAL INPUTS INPUTS O REFERENCE WA A D/A r\ FINE VOLTAGE II 202 I I I I 2 IO V CH4 CH5 CH6 CH7 DIGITAL DIGITAL OI INPUTS INPUTS FIG. I68

I II

I0 FIG. I6C

CHARACTER DISPLAY TERMINAL CROSS REFERENCE TO RELATED APPLICATIONS This application is a continuation-in-part of my copending applications U. S. Ser. No. 587,583, filed Oct. 18, 1966, entitled ELECTRICAL SIGNAL GENERATOR, and U. S. Ser. No. 835,591, filed June 23, 1969, entitled CHARACTER DISPLAY SYSTEM.

BACKGROUND OF THE INVENTION This invention relates to cathode ray tubes display terminals for communication and computer control systems wherein provision is made for keyboard entry of alphanumeric and graphic character symbols with the display of characters in a page format or other form and graphic display of any desired configuration.

Prior art display terminals are known, for example, as disclosed in the U.S. Pat. to Durr, No. 3,307,156 wherein a system is disclosed which employs a' central symbol generator to which each display console has access on a time shared basis and from which it receives binary information in the form of a character identification code followed by the video information required for printing the selected character in a dot raster display. In each display console local recirculating storage is provided for the information currently displayed thereby to provide a refresh rate which maintains the alphnumeric display visible on the screen of a cathode ray tube. Systems of this type have inherent limitations due to the stylized display which is required as a result of a dot raster type video data storage and display system. For example, each character position on the screen is subdivided into a dot format and only the predetermined array of dots is capable of being displayed. Any alphanumeric or other characters which are desired to be presented must be synthesized by selecting predetermined groups of the dots in the raster. This requirement for a restricted range of visual presentation is related to the requirement of such systems to store video information in the recirculating memory. Conversely, attempts to provide a full degree of freedom in forming the visual image entails concomitant video requirements which greatly limit the capacity for any given system size.

This latter limitation (the uneconomical 'use of storage capacity for storing video information) is recognized in the patent to Durr where the suggestion is made that each console may contain its own symbol generator and therefore the memory contents can be confined to character identification codes only. Even though this suggestion increases the character capacity of a given delay line storage unit it cannot in and of itself provide the full capacity required for efficient com munication display consoles since the video generation of a character must be accommodated between the time occurrence of successive character codes. To overcome this difficulty the Durr patent suggests an interlace pattern in the memory for the character codes which permits reading each character followed by a video display interval before the next character is read with the total length of the line such that on successive revolutions of data through the delay line an adjacent character code will be read on each subsequent revoltuion thereby requiring a number of revolutions of the delay line corresponding to the subdivision of the interlace pattern. Under such circumstances the refresh rate for the cathode ray tube screen imposes a limiting factor in relation to the number of characters which can be maintained in storage since the recirculation rate of the delay line cannot drop below that which will read all the characters from the total capacity of the delay line at a rate which will assure the presentation of a visually continuous image on the screen.

It is accordingly one of the principle objects of the present invention to provide a recirculating memory refresh display system in which character identity codes only are stored in the local memory and the characters so stored are contiguous in relation to the read and write access to the storage device and the display screen. Thus in the simplest case where the character identity codes are physically contiguous in the delay line and propagate continuously around the delay loop the identity codes can be read continuously as they pass the readout station on the recirculating loop to be simultaneously displayed on the cathode ray tube screen. This is achieved by virtue of the synchronous character video generator which supplies synchronously with character time each and every character which is in the repetoire of the system for display on the cathode ray screen and without limitation as to format or raster thereby permitting substantially any character shape to be displayed. This display is accomplished in character read time so that as character identity codes are successively read from the delay loop, the corresponding selected characters are processed from the character generators to the cathode ray tube for simultaneous display with a full screen format corresponding to the capacity of the recirculating delay and the full screen display being reproduced for each recirculation of the character codes through the delay loop. The system of the present invention therefore provides a vastly increased character capacity in the screen format together with unlimited flexibility in the actual characters displayed (e. g., upper and lower case letters) and a read in and read out capability which corresponds to the unit capacity for characters and the recirculation time of the delay loop.

Various other forms of the display systems have been suggested in the prior art in which a wide range of symbols with improved definition could be presented on the screen of the cathode ray tube. The U.S. Pat. to Halsted No. 3,329,948 shows a form of symbol generator in which a plurality of positive and negative angles and a selected group of line lengths can be combined to produce any desired symbol representation on the cathode ray tube screen. These systems have generally been non-synchronous however in the sense that the time for symbol formation and presentation varies for different symbols and the selection and generation of any symbol is in response to predetermined program controls which advance character by character only as the currently written character is completed and the program is advanced as a result of the end of character signal. Systems employing this kind of character generation operate with complicated programming for the presentation of the desired information on the screen and thus are not readily adapted to the simplified display and control aspects of a synchronous display system. In addition, wide band channels are required for all character video circuits since the pulse signals are first synthesized and subsequently integratcd.

An additional object of the present invention is, accordingly, the provision of a synchronous display system having a full range of controls which are readily incorporated and compatible with the video symbol generator system while at the same time providing a maximum degree of flexibility and clarity in the symbol generation and display. For this purpose applicants novel signal generator provides a full range of alphanumeric and graphic character generation in a display operating synchronously with the aforementioned contiguous character code recirculating storage feature to provide maximum character capacity with a stable display of highly accurate and versatile configuration characters. These characters are generated and displayed with minimum bandwidth circuits since the stroke pulse generator outputs are first integrated individually and the resulting linear slope waveforms are synthesized into the desired character waveform.

The usefulness of character display systems in the prior art has been extended by the provision of certain editing functions which provide for modification or correction of the text present in memory and currently displayed. For example, the patent to Dammann et aI. U.S. Pat. No. 3,248,705 discloses a display system in which the character codes can be tagged with an additional information bit to identify that character and its position on the screen relative to certain editing operations. With adequate programming and a forwardbackward memory access sequence, this editing operation greatly increases the utility of systems of this type inasmuch as in composing any text for the first time certain errors will appear as well as omissions and for the purpose of rewriting various insertions, deletions and recomposition may be desired. If these functions can be accomplished on the display screen which is currently presenting the memory contents the final form of the text can be achieved prior to its transmission to remote points or other utilization. On the other hand, by the very nature of the editing functions which it is desired to perform the danger exists of inadvertent deletions and the consequent loss of information which, if available only in the memory of the device, may be totally lost if a deletion operation is performed relative to text which it is not desired to discard. Accordingly, the association of editing functions with the information which is circulating in memory, especially where it is accomplished by means of a relatively unsophisticated code such as a single bit, presents the possibility that a noise bit or other malfunction can be effective to lose or disarrange valuable information for which no other source exists.

It is, accordingly, an important object of the present invention to provide in a synchronous refresh character display system a full range of editing functions which are accomplished independently of the information content of the memory store and under the control of the operator by means of independent and reliable hardwire circuit elements thereby assuring that all editing functions will be accomplished as selected under the control of the operator or other control source independently of the information recirculation through memory.

, the display. This display system is controlled by a recirculating memory which in the preferred form stores a character identity code sequence which is contiguous relative to the characters displayed and from which infonnation can be read continuously and without time gaps for simultaneous display. Thus maximum character storage with minimum access time and optimum visual display characteristics are all combined in a symtem which by virtue of its independent editing system can be controlled without loss of data or further complications due to requirements for complicated programming or storage of control and editing functions in the memory. The invention therefore achieves improved operation with respect to the foregoing shortcomings of the prior art allas described herein and as will be apparent from the following detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A, B and C when assembled as indicated show an overall system block diagram of the invention.

FIG. lD shows the editing control signals derived from keyboard operation in response to control code outputs.

FIGS. 2A-E show a circuit and descriptive diagrams for the character generator employed in the invention.

FIG. 3A is a simplified block diagram of the system of the invention showing the arrangement for gross deflection signal generation for the cathode ray tube.

FIG. 3B is a waveform diagram describing gross deflection signals for positioning the cathode ray beam in character positions corresponding to a page format.

FIG. 5 is a representation of a keyboard layout for use as a terminal input for the invention.

FIG. 5A is a partial schematic diagram of the key encoding matrix used with the keyboard keys of FIG. 4 and associated logic circuits for producing the selected key code signal as well as KEY DOWN and ONE KEY signals.

FIG. 5B is a diagram representing the code for the letter A and its complment as used in the machine.

FIG. 5C shows the logic for keyboard gating used in conjunction with the logic of FIG. 5D which shows the keyboard buffer and comparator for contact bounce error elimination.

FIG. 6A and 6B are block diagrams showing the cursor counters and comparators.

FIG. 7 is a logic diagram showing the input gating.

FIG. 8 is a logic diagram for the CLEAR SCREEN operation.

FIG. 9 is a logic operation.

FIG. 10 is a logic diagram for the CLEAR MESSAGE operation.

FIGS. 11 and 12 are logic diagrams for the operations ROLL UP and ROLL DOWN respectively.

FIG. 13 is a waveform diagram of the synchronous pulses employed in the system.

diagram for the CLEAR LINE FIG. 14 is a waveform diagram of the gross deflection signals generated in the system.

FIG. 15 is an ASCII code table showing its relation to the access codes used in the system.

FIG. 16A is a representation of the subdivision of a character window for graphic stroke generation.

FIG. 16B is a block diagram of a graphic stroke generator.

FIG. 16C is a diagram useful in explaining the generation of graphic strokes.

FIG. 17 is a logic diagram for the CHANGE CUR- SORS operation.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIGS. 1A, 1B and 1C assembled as indicated to show an overall block diagram of the system, the general system will first be described. Further details of the operating elements of the system will subsequently be described with respect to more detailed showings of the representations given in FIGS. 1A, 1B and 1C, the timing waveforms of FIG. 13 and the step waveforms of FIG. 14.

The system of the present invention is synchronous in memory and display operations and for this purpose these operations are controlled by pulses derived from a stable crystal oscillator 11 operating, for example, at approximately 6mHz. The frequency of oscillator 11 is subdivided by a first division by four in a divider 12 and a division by three in a divider 13. The output of the divider 12 provides as shown in FIG. 13 a series of timing pules identified as y, 'y and 790 at approximately 1.5mHz to provide the master clock signals for the device. The 1.5 mHz master clock signal is applied to a l2-state ring counter 14 which supplies from its various stages 71 to 712 bit timer pulses at approximately 125 kHz. The divider 13 applies an approximately 2 mHz signal to a 16-state ring counter 15, the output of which provides a contiguous set of square pulses T0 to T15 which pulses are identified as the stroke timer pulses.

The output of the ring counter 15 applies the contiguous pulses to T0 and T15 to a triangular or delta D waveform generator 16 which produces as its output a series of overlapped equilaterial triangle waveforms designated D1 to D13 which are applied to a character generating system 17 and to a cursor summing and graphics unit 18. The D generator 16 produces gate signals G1 and G2 synchronized to begin with T3 and end with T and integrates them to produce the graphic stroke outputs V1 and V2.

The character system 17 contains circuits which continuously and synchronously generate the stroke waveforms for writing each character in the repetoire which the machine is designed to display. For this purpose it combines the overlapping positive and negative slope portions of the input triangle waveforms D1 to D13 to generate each character as a series of connected strokes having the desired slope as determined by the relative magnitudes with which the positive and negative overlapping slope portions of the waves D1 to D13 are combined. The particular character which is to be displayed in any given position on the screen of the cathode ray tube is determined by character board selection code bits LB4, 5 and 6 and character

selection code bits

1, 2 and 3 which determined CHO-CI-I7 applied to the character system 17. As shown in the code table while bits b5 and b6 select the column, the

bits

1, 2 and 3 determine CEO-CH7 which operate to select one of the seven rows in the top or bottom half of the code table which thus uniquely defines the character selected. As a result of this action there appears on output lines 21. and 22 of the character system 17 the summation voltages for X deflection and Y deflection to generate the particular character desired. The details of the circuit for producing the X sum and Y sum voltages on

lines

21 and 22 are explained briefly with reference to FIG. 2A, B, C, D and E hereinafter and in greater detail in applicants copending application Ser. No. 587,583, filed Oct. 18,1966, entitled ELECTRICAL SIGNAL GENERATOR.

The X sum and Y sum voltages on

lines

21 and 22 are processed in the cursor summing and graphics unit 18 to produce on

output lines

23 and 24 the deflection quantities (either voltage or current) for deflecting an electron beam in the cathode ray indicator tube in accordance with the selected character. For this purpose the unit 18 is under the control of a display control unit 25, which unit operates in response to loop bit inputs LBl to LB9 obtained from the refresh storage system hereinafter described. As a result of processing the loop bits the display control unit 25 calls up the desired character or graphic strokes for each character position on the display screen of the cathode ray tube sequentially as the information in storage recirculates including the entry of new data and the discarding of old data all as hereinafter more completely described. To perform this function the display control 25 supplies to the summing and graphics unit 18 signals CE, LBl to LBS, CHO to CH7, and CURSOR GATE. The signal CE provides for character enable control in response to bit 9 of the loop bit code being a zero and when enabled writes a character corresponding to the loop bit code as previously described with reference to FIG. 15. When bit 9 is a one the signal CE is negated and calls for a graphic stroke generation from the cursor summing and graphic generator 18 thereby writing the corresponding graphics stroke designated by the loop bit code. .Loop bit signals LBl, LBS define the beginning and end of the graphic stroke generation while CI-IO-CH7 as applied to graphics unit 18 to select predetermined graphic strokes defined by the 16 geometric points obtained by subdividing the character window into nine equal squares as shown in FIG. 16A. The approximate X and Y fine deflection signals are gated out on

lines

23 and 24 for the graphic stroke selected.

The CURSOR GATE is generated at a random rate timed in response to cursor active compare (CA; FIG. 6A) to write the cursor in predetermined alternation with the character at the active cursor location on the screen. Thus the active cursor location is identified visually by a blinking appearance of the cursor (for example underlining) displayed with any character which may be displayed. In addition the display control 25 supplies a blanking signal during T0-T2 to the cathode ray tube so that only the desired portions of the deflection of the electron beam produce a visible trace on the screen. Times T1 and T2 are used to position the beam at a suitable starting point within the character window before writing begins at T3.

In addition to supplying characters selected from the character system 17, the unit 18 supplies graphic increment strokes available upon command. For this purpose a full character interval is converted into a single pair of opposite slope triangular waveforms in generator 16 as indicated in FIG. 1C and these waves can be combined in any proportion in unit 18 to produce a stroke of any desired slope, positive, negative or zero over the character interval T3-Tl0. By calling forth a succession of graphics strokes defined by subdividing the character window into a 4 X 4 matrix any desired waveform or curve can be drawn with sufficient accuracy on the face of the cathode ray tube. These graphics strokes are selected by an identifying code obtained from LBl-LB8 and the CH to CH7 line from the display control 25 to the summing and graphics unit 18 as descirbed in detail in connection with FIGS. 16A-16C.

THE DISPLAY SYSTEM The display system shown in FIG. 18 used by the present invention is a cathode ray tube indicator generally designated 30 which is provided with two sets of deflection coils for the X and Y fine signals applied from the unit 18 and X and Y staircase signals applied from staircase generator 35. The staircase generator 35 is synchronized with the system clock by means of the 712 derived signals and operates to subdivide the viewing screen into a regular raster of character windows or positions in line and column letter positions for a page format under the control of a frame clock (FC) signal and a begin line (BL) signal timed as shown in FIG. 13. A description of the X and Y staircase generator and deflection system as it is incorporated with the X and Y fine deflection system is given in connection with FIGS. 3A and 3B hereinafter. FIG. 14 further shows the relation of the timing waveforms FC and BL to the stair waves for the X and Y deflections.

TI-IE KEYBOARD INPUT AND RECIRCULATING DELAY SYSTEM Referring now to FIG. 1A, a keyboard input device 51 is provided with a standard typewriter keyboard layout which has in addition keys for the various control functions all as shown on FIG. 4. The operation of an individual key' on the keyboard generates a fixed code representing the character of the individual key as described in connection with FIG. 5. The output provided by the keyboard diode coding matrix of FIG. is the ASCII code and its complement in which 8 bits are used to uniquely identify the character and its parity, with the remaining four bits reserved for tag information. Single key operation is assured and bounce elimination is provided by reading the key code into a register in keyboard logic 52 and subsequently comparing the register word with the keyboard word in the keyboard logic unit 52.

If a comparison exists the keyboard ready signal KBR reads the keyboard and writes the word into an exchange buffer 54. This is a parallel transfer on Bl1-BI9 with the writing control signal for the exchange buffer 54 appearing on line EBWRITE. Once a word is written in the exchange buffer 54 the internal state counters differ and exchange buffer ready (EBR) signals the loop interface 55 to produce a TRANSFER pulse to the exchange buffer 54 at the next character time 71. This produces a parallel transfer of the character code to the input register of the loop interface 55. Character codes are shifted out of the input register into the delay loop as subsequently described herein. If a control code is detected it is routed to perform the appropriate control function such as SHIFT UP, SI-IIFI DOWN, etc. for the active or dormant cursors, or editing control.

The recirculating storage loop is adapted to provide storage of the identity codes for the full capacity of the display screen of cathode ray tube 30. Using a refresh rate of 60 Hz approximately 16 milliseconds of delay is required which is subdivided as follows. The bit rate is approximately l.'5 mI-Iz and the total storage is 2,080 characters with 12 bits per character giving it a total of 24,960 bits in storage when the storage loop is full, i.e., when the screen of the cathode ray tube 30 is written in full-page format (50 chracters by 40 lines plus margin).

Since all operations are performed character by character, entry into and out of the memory loop with or without deletion of existing characters can be accomplished by providing additional storage for two characters in succession. This is achieved by means of first and second shift registers 61 and 62 and appropriate switching represented schematically by switch S1. The actual delay and storage achieved in the memory loop is provided by

magnetostrictive delay lines

63 and 64 which are serially connected through a -detector 65, a reclock unit 66 and a driver 67. Since magnetostrictive delay lines tend to become inaccurate with greater delay periods the 16 millisecond delay interval is divided equally between the two

delay lines

63 and 64 and the information is reclocked in the unit 66 so that time errors introduced by the parameters of the delay lines are held to a minimum. Delay line 63 is driven by a driver 68 and the output of delay line 64 is detected by detector 69. The output of detector 69 is a digital signal which is reclocked by unit 71 to supply the serial bit input to the first shift register 61' and is available on terminal A of switch S1 as a direct input to the driver 68. The output of the first shift register 61 supplies the serial bit input of the second shift register 62 and terminal C of switch S1, while the output of the second shift register 62 supplies terminal B of switch S1. The shift registers 61 and 62 and the

reclocking devices

66 and 71 are all synchronized to the clock pulse 7 thereby providing a synchronous closed loop refresh memory with entry and editing of the memory store available through the switch S1 as it is switched to terminals A, B or C. Original input codes to the memory are derived from an additional terminal 72 which supplies serial bit signals from the input register of editing logic unit 56.

The contents of the recirculating memory loop are utilized one character interval at a time by means of a loop register 73 which has a 12-bit parallel input from the first. shift register 61 and for each character time has a character code registered corresponding to that in the first shift register 61. This code is shifted from register 61 to register 73 in parallel at time 712. The code is shifted serially out of register 73 over lines to supply the loop bits LBl-LB12 to display control 25 and other parts of the system such as control 74 for hard copy, dataset or drum storage options.

The operation of the refresh memory loop will be briefly described. The

delay lines

63 and 64 are the ultrasonic spirally coiled wire type, for example, MSD type 505-2087 (8328;.ts delay) manufactured by Digital Devices, Syosset, N.Y. The lines are energized with non-retum to zero (NRZ) signals supplied by the

respective driver circuits

67 and 68. With approximately 8 MS delay in each line, the

respective detectors

65 and 69 convert the output signals thereof into digital pulse code signals which are reclocked by the

respective devices

66 and 71. Thus a serial pulse stream representing a keyboard code from the input register of the editing logic 56 appears on terminal 72 and with switch S1 connected thereto enters storage in the delay line loop. This process is repeated with the appropriate switching of switch S1 to maintain characters that have been entered circulating in the delay loop and entering keyboard codes as they appear up to the full capacity of the loop for 2,080 characters of 12 bits each. With switch S1 changed to terminal C the information in the loop will recirculate indefinitely without change. The information that is recirculating in the loop passes through the shift register 61 in the succession in which it recirculates through the loop. Each full 12 bit code can be read from the register 61 by parallel transfer at 712 to the loop register 73 and serially transferred out of loop register 73 by the 7 pulse for display purposes on the lines 70 as loop bits LBl to LB 12.

The provision of a character code at terminal 72 of switch 1 from the input register of the loop interface 55 as controlled by the editing logic 56 will now be described with reference to FIG. A. When a key 45 on the keyboard unit is pressed, a magnet attached to a plunger causes a reed switch 46 to close, thus grounding a string of diodes 47 used to generate the code for that particular key. The fact that some of the signal lines have zero (GND level) on them indicates that a key is down. The keyboard diode matrix generates each bit and its complement (e. g., MBl-MBI'). Using ASCII code, eight bits (MEI-M138 uniquely identify the character selected and its parity, with two bits MB9, MB being reserved for tag information.

More than oNE KEY and contact bounce errors are eliminated as described with reference to FIGS. 5C and 5D by successively reading the keyboard bits, and then several milliseconds later comparing the present bit values to the past stored values. If they compare, the keyboard ready (KBR) signal is generated.

In local mode, keyboard ready (KBR) signals the U0 control 53 circuitry to simultaneously read the keyboard and write on the exchange buffer 54 in the following manner. A keyboard read pulse (KBREAD) causes the contents of the latches in the keyboard logic board to be strobed (SKI to 8K9 are used) and a simultaneous EBWRIT E pulse causes the bits strobed out of the keyboard logic to be written into the exchange buffer 54.

Once a character is loaded into the exchange buffer 54, its internal state counters differ, producing the exchange buffer ready (EBR) signal. EBR signals the loop interface 55 which gives a transfer pulse at the next character time (71). The transfer pulse causes the contents of the exchange buffer 54 to be loaded into the input serial shift register of loop interface 55 in parallel.

With a word in the input serial shift register,

bits

6, 7 and 9 are examined. If

bits

6 and 7 are different and bit 9 is zero, the word is a character and the logic in loop interface 55 tells the editing logic 56 that a chracter is ready (CHAR READY). If

bits

6 and 7 are not different and bit 9 is a zero, the word is a control code. That code is examined and the appropriate output is pulsed and the input register is cleared. These outputs shown in FIG. ID, are used by the logic described in FIGS. 7-12 and 17 for editing in conjunction with the cursor controls of FIGS. 6A and 6B or to generate cursor shift signals, etc. If bit 9 is a one, however, the word entered is a graphic character, and it is entered into the loop in the same fashion as a character, i. e., the loop interface 55 tells the editing logic 56 that a character is ready.

Character ready (CI- AR READY) signals the editing logic 56 that the input register is to be read. When the cursor compare (CA) occurs, the editing logic opens a shift gate at T2 which closes after none -y periods causing the input register to shift its contents serially in response to -y pulses from AND 60 into the loop via switch terminal 72. At the end of the nine 7 intervals the cursor CA is stepped to the right one position by the loopinterface. Feedback generated by the editing logic causes the loop interface to drop character ready and the cycle can then repeat. Bit by bit the contents of the input register are presented to the delay line driver 68 input which is connected by switch S1 to terminal 72. At the completion of the shift gate, the editing logic again recloses the loop (S1=C), dropping the character that would have gone into the loop had not the character entry been made (override mode). In insert mode, the editing logic switches to the output of the second shift register (S1=B) rather than the first, thus inserting the character from terminal 72 without deletion. In insert mode, the editing logic switches back to S1=C, the output of the first shift register, when the display reaches the margin spaces at the beginning of the next line.

The loop memory and keyboard entry systems described with reference to FIG. 1A are able to control the character generation and display elements of FIG. 1C by the operation of the cursor counter and control system shown primarily in connection with FIG. 18. During the steady state display of a page format on the screen of the cathode ray tube 30 the contents of the memory loop are read character by character from the first shift register 61 into the loop register 73 upon the occurrence of 712 and this same 'y pulse is used to step the staircase generator 35 character by character and line by line through the page format subdivisions of the cathode ray tube screen. The character identity word read from the loop register 73 is applied to the display control 25 which selects the identified character either as a character, cursor or graphic to determine the X and Y fine deflection control signals which will be applied during that particular character window.

The components shown in FIG. 1B provide the timing controls for the editing logic which controls location and movement of the active and dormant cursors. The units shown in FIG. 18 comprise a high speed counter 81 which has both an X and Y counter running in response to 712 in synchronism with the staircase generator 35 thereby providing a unique count for each

Claims

1. A refresh display terminal comprising: a. display means operative to produce a visual display in direct response to externally supplied character defining digital signals applied thereto; b. recirculating storage means operative to sequentially store a plurality of character defining codes corresponding to an array of characters to be displayed on said display means; c. means responsive to said codes for generating character forming signals to control generation of characters on said display means; d. means for synchronously operating said display means and said storage means whereby the location of said character defining code in said storage means corresponds to a display position on said display means thus providing a cyclic refresh of the characters visible on said display means from the character defining codes carried in said recirculating storage means; e. synchronous register means operating synchronously with said display and storage means for providing a signal representing a relative time identification in each refresh cycle for each said character position; f. non-synchronous register means selectively operable to be set corresponding to said character position for producing control function signals upon correspondence between said character positions selected and said time identification; and g. means responsive to said control function signals for altering the sequence of character defining codes whereby the array of characters appearing on said visual display are selectively modified.

2. Apparatus according to claim 1 in which said control function signals modify the sequential code store in said recirculating storage means for modifying said visual display.

3. Apparatus according to claim 1 in which said visual display is a page format comprising a plurality of lines each of which is subdivided into a plurality of character positions, means for setting said non-synchronous register to select any line and any subdivision thereof and means for visually indicating on said display the character position selected.

4. Apparatus according to claim 3 and including means for entering codes in said storage means character by character and means for advancing said non-synchronous register one character position for each character code entered.

5. Apparatus according to claim 3 and including means for setting said non-synchronous register to correspond to a predetermined character at the left end of the top line of said page format.

6. Apparatus according to claim 3 and including a keyboard operated switch means within the refresh memory for opening the circuit therein to clear said storage means of selected character defining codes and sequentially permit the insertion of new character defining codes whereby to allow various editing operations on said page forMat.

7. Apparatus according to claim 5 and including means operable upon setting said non-synchronous register for clearing said storage means of all of said codes.

8. Apparatus according to claim 3 and including a second non-synchronous register, means for setting said second non-synchronous register to select any line and any subdivision thereof, and means for visually indicating on said display the character position selected by said second non-synchronous register.

9. Apparatus according to claim 8 and including a keyboard operated switch means within the refresh memory for opening the circuit therein to clear said storage means of selected character defining codes corresponding to characters displayed between the character positions selected by both of said non-synchronous registers.

10. Apparatus according to claim 9 and including a keyboard controlled multi-vibrator operatively connected to the second non-synchronous register for stepping said second non-synchronous register one character position at a time as said codes are cleared from said storage means.

11. Apparatus according to claim 10 and including a buffer means operably connecting the refresh memory directly to an output device for reading said codes transferred from said storage means as outputs to said buffer means.

12. Apparatus according to claim 8 and including logic gates operable for transferring the count in one of said non-synchronous counters to the other said non-synchronous counter.

13. Apparatus according to claim 5 and including a buffer register, means operable for transferring the count in one of said non-synchronous counters to said buffer register, and means operable for transferring the count in said buffer register to the other of said non-synchronous counters.

14. Apparatus according to claim 13 and including a swap register operable in conjunction with said buffer register for transferring the count in said other counter to said one counter after the count in said one counter has been transferred to said buffer register but before the count in said buffer register has been transferred to said other counter.

15. A cathode ray tube display terminal comprising: a. a cathode ray tube having orthogonal deflection means for positioning the electron beam to produce a visible trace on the screen of said tube; b. first deflection signal means comprising means coupled to said deflection means for regularly positioning said beam at a plurality of ordered positions on said screen with a predetermined dwell time at each said position to subdivide said screen into a character page format; c. recirculating storage means operative synchronously with said first deflection signal means for providing sequential storage of a plurality of character defining codes corresponding to an array of characters for each of said ordered positions whereby to read in or out of storage each of the character defining codes in timed relation of each said dwell time; d. character waveform generator means operative synchronously with said first deflection signal means for generating character waveforms during each of said dwell times corresponding to each stored character defining code to be displayed; e. second deflection signal means coupled to said deflection means and operative in response to said character waveform generator means for tracing selected character waveforms on said screen during said dwell times; f. refresh signal means for synchronously decoding from said storage means the character defining code for each of said ordered positions and applying the character waveform identified by said code to said second deflection signal means for displaying an image thereof on said screen; g. non-synchronous means selectively operable for identifying any of said ordered positions on said screen; h. means for comparing the position identified by said non-synchronous Means with that determined by said first deflection signal means and producing a control function signal when said positions compare; and i. means responsive to said control function signal for altering the sequence of character defining codes whereby the array of characters appearing on said visual display are selectively modified.

16. Apparatus according to claim 15 and including graphic stroke selection means operative to enter graphics codes into said storage means; and graphic waveform generator means operative synchronously with said first deflection signal means comprising: means operating synchronously with said first deflection signal means for generating a set of time overlap opposite slope waveforms during each of said dwell times; means responsive to detection of a graphics code stored in said storage means for selectively combining said time overlap waveforms in predetermined proportion to produce resultant graphics deflection waveforms as determined by the information content of said graphics code; and means responsive to said detection of a graphics code for disabling the application of character waveforms to said second deflection signal means by said refresh signal means and applying instead said resultant graphics deflection waveforms.

17. Apparatus according to claim 15 and including means for visually indicating on said screen the position identified by said non-synchronous means.

18. Apparatus according to claim 17 and including switch means within the refresh memory for opening the circuit therein and operatively connected to the keyboard and selectively operable therefrom for clearing said storage means of character defining codes corresponding to characters displayed on said page format subsequent to said position identified.

19. Apparatus according to claim 18 and including means for altering the relation between the remaining stored character identity codes and said ordered positions in accordance with said predetermined portion of said page format.

20. Apparatus according to claim 17 and including: a. a second non-synchronous means selectively operable for identifying any of said ordered positions on said screen; b. means for comparing the position identified by said second non-synchronous means with that determined by the said first deflection signal means and producing a second control function signal when said positions compare; and c. means responsive to said second control function signal for altering the sequence of character defining codes whereby the array of characters appearing on said visual display are selectively modified.

21. Apparatus according to claim 20 and including means selectively operable for transferring one of said visual indications to the position occupied by the other said visual indication.

22. Apparatus according to claim 20 and including means selectively operable for interchanging the positions occupied by said visual indication.