GB1341843A - Logic tutor - Google Patents
Logic tutorInfo
- Publication number
- GB1341843A GB1341843A GB1341843DA GB1341843A GB 1341843 A GB1341843 A GB 1341843A GB 1341843D A GB1341843D A GB 1341843DA GB 1341843 A GB1341843 A GB 1341843A
- Authority
- GB
- United Kingdom
- Prior art keywords
- storage
- elements
- storage elements
- tutor
- logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09B—EDUCATIONAL OR DEMONSTRATION APPLIANCES; APPLIANCES FOR TEACHING, OR COMMUNICATING WITH, THE BLIND, DEAF OR MUTE; MODELS; PLANETARIA; GLOBES; MAPS; DIAGRAMS
- G09B23/00—Models for scientific, medical, or mathematical purposes, e.g. full-sized devices for demonstration purposes
- G09B23/06—Models for scientific, medical, or mathematical purposes, e.g. full-sized devices for demonstration purposes for physics
- G09B23/18—Models for scientific, medical, or mathematical purposes, e.g. full-sized devices for demonstration purposes for physics for electricity or magnetism
- G09B23/183—Models for scientific, medical, or mathematical purposes, e.g. full-sized devices for demonstration purposes for physics for electricity or magnetism for circuits
- G09B23/186—Models for scientific, medical, or mathematical purposes, e.g. full-sized devices for demonstration purposes for physics for electricity or magnetism for circuits for digital electronics; for computers, e.g. microprocessors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Optimization (AREA)
- Algebra (AREA)
- Computational Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Analysis (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Pure & Applied Mathematics (AREA)
- Business, Economics & Management (AREA)
- Educational Administration (AREA)
- Educational Technology (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
1341843 Logic tutor apparatus NATIONAL RESEARCH DEVELOPMENT CORP 19 April 1971 [19 Jan 1970] 2440/70 Headings G4C and G5G Logic tutor apparatus includes a bit-addressed storage circuit comprising a plurality of binary storage elements which may be changed to a predetermined state by the application of a predetermined bit-write signal and of coded address signals to appropriate terminals, selection means for selecting any of the storage elements of the storage circuit and changing the state of the selected element to the predetermined state, and display means for indicating at least which of the storage elements are set to one of the states. As shown (Fig. 2), the storage circuit comprises four units 47-50 each of 16 storage elements. A counter 63, clock 64 and decoder 52 enable each of the storage elements to be addressed in turn; outputs corresponding to the states of the elements appear sequentially at an OR-gate 61 for controlling the intensity of the beam of a cathode-ray rube 70, which beam is deflected by digital to analogue converter 65 so as to present a truth table, e.g. a Karnaugh Map of the elements of the storage circuit. The state of a storage element for which an address exists on lines 41-46 may be changed by holding a light pen 72 over the appropriate dot on the screen 70 and depressing a key 60. The apparatus can function with either 4 or 6 variables at input terminals 41-46. Delay circuits may be connected between input and output terminals of the circuit to facilitate study of sequential behaviour and feed back loops in logical expressions and, e.g. NAND gates may be provided for connection by a patch board as required. The display on the screen 70 may comprise dots, or alpha-numeric characters. A number of OR-gates may be provided each having the output terminals of different or different combinations of, storage circuits connected to their input terminals and switching means may also be provided to allow for signals on variable numbers of inputs to the apparatus.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB244070 | 1971-04-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1341843A true GB1341843A (en) | 1973-12-25 |
Family
ID=9739626
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB1341843D Expired GB1341843A (en) | 1971-04-19 | 1971-04-19 | Logic tutor |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB1341843A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2257816A (en) * | 1991-07-12 | 1993-01-20 | Inova Enterprises Limited | Teaching apparatus. |
FR2706212A1 (en) * | 1993-06-07 | 1994-12-16 | Zabeti Esmail | System for visually displaying and, in a concrete way, studying the logical and analogue operation of a microcomputer when running |
-
1971
- 1971-04-19 GB GB1341843D patent/GB1341843A/en not_active Expired
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2257816A (en) * | 1991-07-12 | 1993-01-20 | Inova Enterprises Limited | Teaching apparatus. |
GB2257816B (en) * | 1991-07-12 | 1994-02-09 | Inova Enterprises Limited | Teaching apparatus |
FR2706212A1 (en) * | 1993-06-07 | 1994-12-16 | Zabeti Esmail | System for visually displaying and, in a concrete way, studying the logical and analogue operation of a microcomputer when running |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |