GB1335302A - Monitoring and display apparatus - Google Patents

Abstract

1335302 Selective signalling INTERNATIONAL COMPUTERS Ltd 17 Feb 1971 4804/71 Heading G4H Signal monitoring and display apparatus scans input signals using AND gates and supplies them and timing signals to display means. In Fig. 3, each module such as 102 has an 8-stage shift register with input I and output O driven by shift pulses at S, each stage gating (by means of a respective AND gate) a respective one of 8 inputs M1-M8 to a serial output V. In Fig. 3, 16 Î 32 bit states in a data processor are serialized into a bit train for display as a 16- line frame on a TV monitor 110, by 16 groups G1-G16 (only 3 shown) each of 4 modules in series (only 2 shown), the bits being applied to the M1-M8 inputs. 16 trains, each of 32 bits, on lines CV1-CV16 respectively, are converted into a single serial train on line 109 by modules 102, 103. The bit train also contains line sync. and frame sync. signals from line LB and the O output of module 103 respectively. This O output can also be connected to the I input of module 102. Modules 105, 106 together form a divide-by-32 arrangement since "zero" inputs are connected to M1 and M5 of 105 and to M1 of 106, "one" inputs being connected to the other M inputs of 105 and 106. The divide-by-32 arrangement, given the fact that line sync. signals appear on line LB, ensures that successive lines of data are displayed 32 scan lines apart. The significance of the spots of light displayed on the TV monitor can be indicated by fixed grid-reference lines and co-ordinates marked on a system logic diagram, fixed or interchangeable film masks, or back projection systems form asks or logic diagrams, or further video signals may be multiplexed in. Several arrays as in Fig. 3 may be provided, feeding a channel selector. The module referred to above could alternatively gate the inputs M1-M8 simultaneously into the shift register and then shift them out serially. In this case the four shift registers in each group G1-G16 can be connected in a loop for continuous display. One or more lines could be displayed selectively, or the order in which the lines are displayed may be alterable. Each shift register in the first type of module may be replaced by a counter feeding a decoder the outputs of which enable respective ones of the AND gates, or the gates may also perform the decoding function. Alternatively, each decoder may control 32 AND gates (for a line) and be controlled by the five least significant stages of a single counter, more significant stages of which select one of several sets of 32 AND gates through logic. The TV monitor may be replaced by panels of discrete lamps, with serial-toparallel conversion.