GB1398506A - Data display system suitable for radar and having a multilevel video storage device - Google Patents

Abstract

1398506 Pulse radar; cathode-ray tube displays BENDIX CORP 24 July 1973 [21 Sept 1972] 35272/73 Headings H4D and H4T A display device for a radar system for providing a flicker-free bright display comprises an analogue to digital converter for converting radar returns into at least two parallel binary words, input means, a main memory, first gate means for gating the binary words into the input means at a first rate during a first period and for gating the data stored in the input means into the main memory during a second period, and second gate means for transferring the data stored in the main memory to output storage means and for transferring the data stored in the output means to a utilization means at a second rate faster than said first rate. The described embodiment relates to a weather radar in which radar returns are digitized to give four possible output levels, each of these levels being defined by two parallel digital words (see lines (30), (32), Fig. 1, not shown, carrying the digital words). The two parallel digital words are passed via lines 30, 32 to input buffers 34, 36. The system is based on that described in Specification 1,361,156, but is modified to cope with two parallel words instead of only one word. The buffers are capable of storing two words each, each word corresponding to a particular range sweep. The words are entered at a rate determined by divider 40 which determines the display range. Counter 50 allows only one word to be stored at a time. Two words are stored consecutively in each of the buffers, the words corresponding to consecutive range sweeps and are then transferred at frequency f 0 to memories 55, 65 under control of the remaining logic circuitry. Once the memories have been updated access to them from the buffers is disabled and the data stored therein is continually recirculated. The stored data is passed to an integrator (Figs. 4, 5, not shown), which tends to eliminate extraneous signals. An azimuth circuit (Fig. 4, not shown) positions the radar antenna according to the display system control signals. In another embodiment the antenna is not positioned by the control signals (see Fig. 15, not shown, illustrating alternative circuit elements for such an embodiment). The integrated data is fed to a main memory (Fig. 9, not shown), which is split into two parts for each binary word, necessary for updating purposes. An output buffer circuit connected to the main memory comprises two shift registers (200b, 202b and 200a, 202a, Fig. 10, not shown) for each binary word. One shift register, for each word, stores a word from the main memory while the other shift register reads out a previously stored word at a higher rate, the registers alternating from storing to reading from word to word. In the embodiment a word is read out twice to a digital to analogue converter (208) (Fig. 10, not shown). The converter receives the two parallel binary words, produces an analogue output having one of four possible levels and feeds the resultant signal to a CRT (210). The higher read out rate enables the production of a bright flicker-free display from radar operating at low P.R.F.s.