US3806884A - Logic circuit arrangement for the generation of coded signals of characters - Google Patents

Logic circuit arrangement for the generation of coded signals of characters Download PDF

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Publication number
US3806884A
US3806884A US00316462A US31646272A US3806884A US 3806884 A US3806884 A US 3806884A US 00316462 A US00316462 A US 00316462A US 31646272 A US31646272 A US 31646272A US 3806884 A US3806884 A US 3806884A
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memory
external
signals
address
characters
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US00316462A
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English (en)
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G Glay
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Sagem SA
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Sagem SA
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M11/00—Coding in connection with keyboards or like devices, i.e. coding of the position of operated keys
    • H03M11/20—Dynamic coding, i.e. by key scanning
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/02—Digital function generators
    • G06F1/03—Digital function generators working, at least partly, by table look-up

Definitions

  • the present invention provides an assembly logic cir cuits arrangement intended to generate coded signals of characters or functions, capable of being associated with external circuits controlled for example by a character keyboard.
  • Such circuits may therefore be associated with a character keyboard not only to generate coded character signals, but also to generate functions referring to these characters which, in practice, are not realisable with known electro-mechanical devices.
  • the present invention therefore provides logic circuits permitting the generating of coded signals of characters as well as functions associated with these characters which will be given hereinafter.
  • FIG. 1 shows a plurality of elementary logic circuits used in the arrangement of the invention
  • FIG. 2 shows diagrammatically in the form of a block, the circuit according to the invention and a plurality of input and output signals;
  • FIGS. 30 and 31 show the logic diagram, in the form of blocks, of the arrangement according to the invention.
  • FIGS. 40, 4b and 5a, 5b show diagrams of signals useful for understanding the operation ofthe arrangement of the invention.
  • FIG. I shows, in binary logic, a certain number ofdiagrams each corresponding to a logic function. From top to bottom are shown the function of inversion, the function AND, the function OR, the function counting and the function "comparison.
  • the corresponding circuits are therefore an inverter circuit (noted by a small circle), an AND gate, an OR gate, a counter and a comparator.
  • the counter shown a shifting registcr having a plurality of flip-flops mounted in series. The diagram of a single flip-flop is similar but the corre' sponding rectangle has a lesser area.
  • the comparator compares in general two binary numbers and generates an output signal when these two numbers are equal or become equal.
  • the thick connection of FIG. 1 represents a line transmitting several binary figures or bits" in parallel whilst the thin connection line of FIG. 1 represents a line transmitting a single bit.
  • FIG, 2 represents, in the symbolic form of a rectangle, the logic circuit LGCl according to the invention and all the signals capable of entering into this circuit or leaving it. These signals have a mnemonic form. All the signals beginning with the letter N (which corresponds to NO") are exchanged with the circuit in the form of their complement.
  • the signal N (EA7) for example is identical with the signal EA7 which in usual notation is the complement or the reverse of EA7.
  • the signals N (EAO) to N (EAIO) are addresses input signals coming from an external memory (exterior to the circuit) the signals N (SAO) to N(SA7) are the output signals providing the addresses of the external memory,
  • the signals N(SDO) to N(SD7) are output signals or results and, in particular, the coded signals of selected characters.
  • the other signals are the following:
  • NI I Selecuon ol the levels of the internal memory N (NI 2) N (AT) Waiting N (AN) Cancellation N (RE) Repetition N (SE) Sequence b) Outgoing signals:
  • FIGS. 30 and 3b represent the circuits arrangement according to the invention, on the inside of the rectangle in broken lines.
  • the number of characters provided is 3X88.
  • the arrangement is controlled by a pulse generator or external clock which generates the signal HO (see FIGS. 50 and Sb) and the different base times.
  • This clock is associated with an external memory Me of 88 binary bits which may be. for example, a read-only memory and which provides the addresses of the 88 characters which are themselves recorded in a read-only internal memory Mi comprising 3 sections or levels Mi], Mi Mi;,, each compartment recording the 88 character codes, each character code comprising 10 binary figures or bits.
  • This arrangement comprises essentially the readonly memory Mi of 3X88 characters, counters or shift regis ters CNI, CSEA, CDEA, CSSA, CDSA, RD88, a logic selection" circuit LS, flip-flops MC, BSE, BSC, MBSEL, BAT, CAI, CA2, compartors and OR and AND gates.
  • These circuits have the following organisation and functions:
  • CNI Level counter
  • CSEA Static counter address input
  • Dynamic counter address input It has 1 flip-flops and it provides the first part of the address of the character to be selected, according to the position of a dynamic register;
  • CSSA Static counter address output
  • Dynamic counter address output It has 8 flip-flops and it provides the second part of the address of the character to be selected, according to the position of a dynamic register;
  • Logic of selection" block It selects a bit of the word generated by the external memory according to the contents of the counter CDEA;
  • Register (R088) This is a dynamic shift register of 88 bits.
  • logic comparison circuits detecting the coincidence of the static and dynamic counters.
  • the dynamic counters are timed by the clock and scan permanently the external memory.
  • the static counters (taken together) store the ad- I 1 Selected level Level Level I Level 2 Level 2 NI 2 N 0.
  • Signal Waiting AT This signal, when it is present, prevents any character generation, (1.
  • Signal Cancellation" AN This signal, when it is present, which corresponds to AN 1, controls the initiation of the arrangement and prevents any output of information. 2.
  • This signal is taken into account if it is applied to the arrangement a short time before the disappearance of the signal PC.
  • Signal Sequence SE The presence of this signal after the disappearance of the signal PC controls the generation of the character contained in the following address of the internal memoryv This signal is taken into account if it is present a short time before the disappearance of the signal PC.
  • EAO to EAltl are signals coming from the external memory Me, this memory being addressed by the signals 8A0 to SA7.
  • the dynamic counter CDSA deter mine the address of one of the 8 numbers of I 1 bits of the external memory, and this number is then transferred into the logic selection circuit in the form of one of the signals EAO to EAlO.
  • the signals EAO to EAHI are transferred into the logic selection circuit only when the signals SAD to SA7 correspond to the number (one number among eight) which it is desired to select in the external memory and which corresponds in its turn to the address of the character which it is desired to select in the internal memory of characters.
  • Said arrangement comprises individual mode which are the following: Initiating (or starting), rest, generation of a character, generation of a character by repetition, generation of a sequence of characters, waiting.
  • each mode the operation is determined by a sequence of phases p (see above) each composed of four time bases t to 1, corresponding to:
  • a state 0 is introduced in RD88
  • a state 1 is introduced in CDEA, CSEA, CDSA and CSSA.
  • the flip-flops MC, BSE and BSC are in the state 0.
  • next character will only be able to be generated when the counters CDEA and CSEA as well as CDSA and CSSA are in coincidence (88th phase after the initial character generation phase).
  • Character generation step Resetting of MC at the time of the disappearance of HC 3. Passing to a different method of operation.
  • This mode of operation is effective when the signal SE is present at the time of the ending of a character generation. It has a priority with regard to the mode of generation of a character in repetition according to the following table:
  • next character will only be able to be generated when the counters CDEA and CSEA as well as CDSA and CSSA are in coincidence during a phase.
  • the flip-flops MC, BSE and BSC are maintained in their state 2.
  • the dynamic counters are incremented at the time of the end of each phase 3.
  • the static counters CSEA and CSSA are incremented at the time of the end of each phase if MC 4.
  • the dynamic register is closed (introduction of SR to each phase in the register)
  • the generation of another mode of operation is effective at the time of the end of the phase following the disappearance of the signal AT.
  • a logic circuit for generating coded signals con trolled by a pulse synchronization generator and by external signals comprising an external read-only matrix memory having p lines and q columns and storing pq addresses, p and q being integer numbers, a control circuit controlled by said external signals and connected to said memory which introduces a determined binary digit in the position of the address of said memory to be selected, an internal read-only matrix memory having at least p multiple lines and q multiple columns and storing pq characters, two address registers comprising respectively p and q binary positions controlling respectively the p lines and q columns of said internal memory, and two dynamic counters having the structure of shift registers connected to said external memory which scan cylically in a total period P said external memory for transferring at a determined instant of said period P each part pi and qt of the selected address (pi, qi) in said address registers which control the transfer of the selected character of the internal memory to an output line when the contents of said address registers are equal to the contents of said
  • a logic circuit for generating coded signals controlled by a pulse synchronization generator and by external signals comprising an external read-only matrix memory having p lines and q columns and storing pq addresses, p and q being integer numbers, a control circuit controlled by said external signals and connected to said memory which introduces a determined binary digit in the position of the address of said memory to be selected, an internal readonly matrix memory having at least p multiple lines and q multiple columns and storing pq characters, two address registers comprising respectively p and q binary positions controlling respectively the p lines and the q columns of said internal memory.
  • two dynamic counters having the structure of shift registers connected to said external memory which scan cyclically in a total period P said external memory for transferring at a determined instant of said period P each part pi and qi of the selected address (pi, qi) in said address registers, and comparator circuits which compare the contents of the dynamic counters and of the corresponding address registers, the output signals of these comparators controlling the generation of a character presence signal when the said contents are equal and consequently when the character signals are transferred to the outside of said arrangement.
  • a logic circuit for generating coded signals controlled by a pulse synchronization generator and by external signals comprising an external read-only matrix memory having p lines and q columns and storing pq addresses, p and q being integer numbers, a control circuit controlled by said external signals and connected to said memory which introduces a determined binary digit in the position of the address of said memory to be selected, an internal read-only matrix memory storing characters and having supplementary binary positions storing a sequence of determined characters, two address registers comprising respectively p and q binary positions controlling respectively the p lines and q columns of said internal memory, and two dynamic counters having the structure of shift registers connected to said external memory which scan cyclically in a total period P said external memory for transferring at a determined instant of said period P each part pi and qi of the selected address (pi, qi) in said address registers, an external signal controlling the successive transfers of the characters of said sequence outside of said arrangement, each character of this sequence being transferred during one period P.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Storage Device Security (AREA)
  • Logic Circuits (AREA)
  • Read Only Memory (AREA)
US00316462A 1972-01-06 1972-12-19 Logic circuit arrangement for the generation of coded signals of characters Expired - Lifetime US3806884A (en)

Applications Claiming Priority (1)

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FR7200326A FR2166733A5 (enrdf_load_stackoverflow) 1972-01-06 1972-01-06

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US3806884A true US3806884A (en) 1974-04-23

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US (1) US3806884A (enrdf_load_stackoverflow)
DE (1) DE2259887C3 (enrdf_load_stackoverflow)
FR (1) FR2166733A5 (enrdf_load_stackoverflow)
GB (1) GB1423170A (enrdf_load_stackoverflow)
IT (1) IT971829B (enrdf_load_stackoverflow)
NL (1) NL7216847A (enrdf_load_stackoverflow)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2121224A (en) * 1982-06-01 1983-12-14 Univ Edingburgh The University Function keyboard for a microprocessor system

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3341817A (en) * 1964-06-12 1967-09-12 Bunker Ramo Memory transfer apparatus
US3344403A (en) * 1964-06-26 1967-09-26 Ibm File selection system
US3434112A (en) * 1966-08-01 1969-03-18 Rca Corp Computer system employing elementary operation memory
US3541518A (en) * 1967-09-27 1970-11-17 Ibm Data handling apparatus employing an active storage device with plural selective read and write paths
US3570006A (en) * 1968-01-02 1971-03-09 Honeywell Inc Multiple branch technique

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3341817A (en) * 1964-06-12 1967-09-12 Bunker Ramo Memory transfer apparatus
US3344403A (en) * 1964-06-26 1967-09-26 Ibm File selection system
US3434112A (en) * 1966-08-01 1969-03-18 Rca Corp Computer system employing elementary operation memory
US3541518A (en) * 1967-09-27 1970-11-17 Ibm Data handling apparatus employing an active storage device with plural selective read and write paths
US3570006A (en) * 1968-01-02 1971-03-09 Honeywell Inc Multiple branch technique

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Publication number Publication date
GB1423170A (en) 1976-01-28
FR2166733A5 (enrdf_load_stackoverflow) 1973-08-17
DE2259887B2 (de) 1974-04-25
DE2259887C3 (de) 1974-11-21
NL7216847A (enrdf_load_stackoverflow) 1973-07-10
DE2259887A1 (de) 1973-07-12
IT971829B (it) 1974-05-10

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