US3802180A - Pulses generating system - Google Patents

Pulses generating system Download PDF

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Publication number
US3802180A
US3802180A US00267056A US26705672A US3802180A US 3802180 A US3802180 A US 3802180A US 00267056 A US00267056 A US 00267056A US 26705672 A US26705672 A US 26705672A US 3802180 A US3802180 A US 3802180A
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Prior art keywords
logical
pulses
output
gate
control
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Expired - Lifetime
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US00267056A
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English (en)
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J Boudry
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Societe Europeenne de Semi Conducteurs de Microelectronique SA SESCOSEM
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Societe Europeenne de Semi Conducteurs de Microelectronique SA SESCOSEM
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04C—ELECTROMECHANICAL CLOCKS OR WATCHES
    • G04C3/00—Electromechanical clocks or watches independent of other time-pieces and in which the movement is maintained by electric means
    • G04C3/14—Electromechanical clocks or watches independent of other time-pieces and in which the movement is maintained by electric means incorporating a stepping motor

Definitions

  • Th pulses generating system comprises two logical l l Field Search 53/23 23 23 23 storage means, eg two toggles in a master-slave 58/23 23 4; 85, 696; 328/ 6, arrangement, synchronised by sync. signals derived 161 from a medium order divider stage and controlled by signals derived from lower order divider stage Reference-S Cited imposing the repetition frequency to said generated UNITED'STATES PATENTS control pulses.
  • the present invention relates to pulse generating systems provided for drive control of the electromechanical part of an electronic watch, the latter comprising in particular a master oscillator, an electronic frequency divider, a D.C. power supply, an electric stepping motor and a display system eg hands driven by said motor.
  • pulses of finite duration are required, for example in the order of milliseconds, which will control the drive of a stepping motor with a repetition frequency in the order of /2 Hz to 2 Hz.
  • two trains of control pulses M and M having the same duration and same repetition frequency are required, the pulses in one train being time shifted with respect to those in the other by an interval equal to half a repetition rate. It is usual to refer to two such pulse trains as being interlaced.
  • the invention overcomes these drawbacks.
  • recurrence signals R constituted by pulses whose duration is equal to halfthe repetition rate of the control pulses it is desired to produce.
  • These signals H and R are applied to predetermined inputs of a logic circuit arrangement comprising two synchronisable toggle circuits connected in a masterslave arrangement.
  • the signals H are applied to the clock (or sync.) input of the first toggle circuit, whilst the complementary signals H are applied to. the clock input of the second toggle circuit.
  • the signals R control the operation of the toggles and are applied to the control input of the first toggle.
  • the pulse trains M, and M are obtained by decoding predetermined outputs of these two toggle circuits, the decoding being effected by a first and second logic gate, e.g. AND" gate, the first gate producing the pulses M, and the second the pulses M
  • a first and second logic gate e.g. AND
  • FIG. I is a block diagram illustrating the principle of the invention.
  • FIG. 2 is one of the possible diagrams of the coupled toggle circuits constituting part of the invention.
  • FIGS. 3 and 4 are diagrams illustrating the functioning of the system
  • FIG. 5 is a circuit diagram in accordance with the invention, including the addition of a system controlling the toggles operation and usable to modify the display system indication, for example for resetting the time.
  • FIG. 1 part of the electronic circuitry of a watch has been illustrated, comprising:
  • frequency divider stages numbered N, N-l, n, nl, 2, I connected in series between the output 0 ofa master oscillator 10 providing a high frequency signal, e.g. 32 kHz, and a terminal S furnishing signals whose frequency has been reduced for example to l Hz.v
  • Each stage divides the frequency which it receives from the input of the preceding stage (or the oscillator in the case of stage N) by a constant factor, for example 2;
  • a pulse generating system for providing eontrol'pulses M, and M hereinbefore defined.
  • This system comprises two synchronisable toggle circuits B, and B with two stable states, and two AND-gates 21 and 22.
  • the system arrangement is as follows:
  • stage n of the frequency divider is connected to an input T of the toggle B, and, across an inverter 23 to a complemented input T of the toggle B This input T is complementary to that T.
  • the toggle B changes state when its input signal is the complement of the input signal to toggle B,.
  • the output of a low-frequency divider stage for example the stage 1, is connected to a control input I of the toggle 8,.
  • the toggle B has two complementary outputs X and X, and the toggle B has two complementary outputs Y and Y.
  • the inputs of the logic AND circuit 21, which produce at their output the pulses M, are connected to the outputs X and T; the inputs of the logic AND circuit 22 producing th e pulses M at its output, are connected to the outputs X and Y.
  • toggle circuits comprise combinations of logic gates and inverters, the gates being opened or closed by the sync. signals, marked by H in FIGS. 1 and 2, coming from the output of a stage n.
  • the AND gates 31 and 32 control the inputs to NAND-gates constituted by two AND-gates 33 and 34 whose outputs are taken to inverters 35 and 36.
  • the assembly of circuits 33, 34, 35 and 36 constitutes a toggle circuit thanks to the loop connections effected between the output of the inverter 35 and an input of the NAND-gate 34, and between the output of the inverter 36 and an input of the NAND-gate 33.
  • the same arrangements are encountered in toggle 8,, where the logic circuits 41 to 46 are similar to those of the circuits 31 and 36.
  • the sync. signals H, via the terminal T, are supplied to the sync. inputs 311 and 321 of t he AND- gates 31 and 32.
  • the complementary signals T are supplied to the corresponding inputs 411 and 421 of the AND-gates 41 and 42.
  • Each toggle which has two stable states, constitutes a store capa ble of holding a piece of binary data.
  • the inputs T and T enable a new binary data value to be fed into each of the respective stores.
  • the repetition frequency signals R coming from the output S at the lowest frequency of the divider shown in FIG. 1, arefed into the toggle B, through a control input J connected to an input 312 of the AND-gate 31,
  • W represents the high potential (I state) and W the low potential (0 state).
  • E the potentials are plotted on the ordinates (EW axis) and the times on the abscissa (Et axis).
  • the lines a, b, c, d, parallel to the axis EW, represent the characteristic instants at which the gates change state.
  • the pulse R at the terminal I is only transmitted to the output X at the instant b, that is to say after a delay at least equal to (b-a).
  • the pulse R is only transmitted. at the output Y at the instant d, that is to say after a delay at least equal to (d-a) 3. Consequently, the leading edges of the pulses X and Y are offset by a time period (d-b) which is in the order of magnitude of the duration of the sync. pulses H.
  • FIG. 4 shows a diagram similar to that of FIG. 3, this time however covering the full period of the signals R. If D marks this period and I marks the duration of the pulses R, then using dividers which effect division by a factor of 2 and with rectangular signals, we have:
  • the response pulses of the synchronisable toggles have the same duration I and the same period D. However, the pulses X and Y are offset by an interval i which is substantially equal to half the period of the pulses H.
  • the decoding effected by the AND-gates 21 and 22 (FIG. I) in effect means the performance of the following logic functions:
  • the frequency-divider could be equipped with a supplementary frequency-divider stage connected at the output S of stage 1, in which case it would be at the output of this supplementary stage that the signal R would be picked up;
  • FIG. 5 Another advantage of the invention resides in the possibility which it affords for adding a simple operation control system for resetting the time.
  • elements 51 to 57 have been illustrated in FIG. 5, which are intended to carry out this function.
  • Two AND-gates 51 and 52 are connected in the manner indicated in FIG. 5, between the stages 1 and 3, an inverter being arranged between two respective inputs 512 and 522 of the AND-gates 51 and 52, the inputs 511 and 521 being connected to the respective outputs of the stages 3 and l.
  • the input 512 is connected by a switch at terminal 56, either to a potential W, or to earth potential W
  • the outputs of the AND-gates 51 and 52 are connected to the two inputs of an OR-gate 53 whose output is connected to an input of an AND- gate 54.
  • To a second input of the AND-gate 54 either the potential W or earth potential W is applied by a switch 57, and the output of the AND-gate 54 is connected to the control input terminal J of the first toggle B Thanks to these complementary arrangements, it is possible to reset the time by modifying the operation of the toggles.
  • the operation is broken into the following stages:
  • the motor is halted by inhibiting the AND-gate 54 (switch 57 set to earth potential W b.
  • the motor is advanced at high speed by opening the AND-gate 51 (switch 56 to W,) an d the AND-gate 54 (switch 57 to W,);
  • the invention is likewise applicable to an electronic watch which, either instead of the stepping motor or in addition to it, comprises a pulse counter which, by the emission of currents at predetermined intervals, actuates luminescent elements, for example electroluminescent diodes.
  • a pulse generating system provided for the drive control of the electromagnetic part of an electric watch, said watch comprising a master oscillator, an electronic frequency divider connected to said oscillator-and including a plurality of dividing stages of higher order, of medium order, and lower order, an electric motor of the stepping operation type controlled by pulses having a finite duration and repetition frequency and a DC.
  • said pulse generating system comprises at least two logical system means for storing binary data, the first of said means comprising a control input terminal connected to the output of a frequency divider stage of said lower order for determining the repetition frequency of said pulses, a clock input terminal of said first means connected to an output of said medium order divider stage by a connecting means which allows the modification of the connection of one of said medium order stage for determining the duration of said pulse, said first means having at least two outputs, one of said first means outputs being a logical signal X output terminal and the other of said output terminals being a logical complementary signal X output terminal, and said second logical system means comprising at least first and sec ond control inputs connected respectively to X and X of said first means output terminals, a clock input terminal connected directly through an inverter means to said first means clock input terminal connection and said second means having two outputs, one logical signal Y output and one logical complementary signal Y; and wherein said pulse generating system in addition comprises decoding
  • connecting means is a busbar connected by soldering means to an output terminal of said medium order divider stage and to said first and second clock inputs of the two logical system means.
  • system comprises, connected to the control input terminal of said first logical system means, an operation control system comprising an AND gate for inhibiting control pulse transmission and actuated by switching means and an arrangement of a second AND gate connected to the upper stages of the lower frequency divider stages and a third AND gate connected to the lower stages of the low frequency divider stages, said both last mentioned gates being actuated by another switching means, said last mentioned gates being connected to the first gate by means of and OR gate thereby enabling modification of the repetition rate of said control pulses.
  • an operation control system comprising an AND gate for inhibiting control pulse transmission and actuated by switching means and an arrangement of a second AND gate connected to the upper stages of the lower frequency divider stages and a third AND gate connected to the lower stages of the low frequency divider stages, said both last mentioned gates being actuated by another switching means, said last mentioned gates being connected to the first gate by means of and OR gate thereby enabling modification of the repetition rate of said control pulses.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Electromechanical Clocks (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
US00267056A 1971-07-09 1972-06-28 Pulses generating system Expired - Lifetime US3802180A (en)

Applications Claiming Priority (1)

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FR7125179A FR2145356B1 (enrdf_load_stackoverflow) 1971-07-09 1971-07-09

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US3802180A true US3802180A (en) 1974-04-09

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US (1) US3802180A (enrdf_load_stackoverflow)
CH (2) CH586421B5 (enrdf_load_stackoverflow)
DE (1) DE2233556A1 (enrdf_load_stackoverflow)
FR (1) FR2145356B1 (enrdf_load_stackoverflow)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3972178A (en) * 1972-10-13 1976-08-03 Societe Suisse Pour L'industrie Horlogere Management Services S.A. Electrically powered timepiece
US3998044A (en) * 1973-12-19 1976-12-21 Citizen Watch Co., Ltd. Electronic timepiece
US4092604A (en) * 1976-12-17 1978-05-30 Berney Jean Claude Apparatus for adjusting the output frequency of a frequency divider

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3363410A (en) * 1966-01-25 1968-01-16 Suwa Seikosha Kk Apparatus for adjusting electric timepieces
US3416057A (en) * 1966-04-06 1968-12-10 Gaylord Rives Company A.c. motor speed control system using selected voltage levels inverted at selected frequencies and method
US3671841A (en) * 1970-05-01 1972-06-20 Tri Tech Stepper motor with stator biasing magnets

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3363410A (en) * 1966-01-25 1968-01-16 Suwa Seikosha Kk Apparatus for adjusting electric timepieces
US3416057A (en) * 1966-04-06 1968-12-10 Gaylord Rives Company A.c. motor speed control system using selected voltage levels inverted at selected frequencies and method
US3671841A (en) * 1970-05-01 1972-06-20 Tri Tech Stepper motor with stator biasing magnets

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3972178A (en) * 1972-10-13 1976-08-03 Societe Suisse Pour L'industrie Horlogere Management Services S.A. Electrically powered timepiece
US3998044A (en) * 1973-12-19 1976-12-21 Citizen Watch Co., Ltd. Electronic timepiece
US4092604A (en) * 1976-12-17 1978-05-30 Berney Jean Claude Apparatus for adjusting the output frequency of a frequency divider

Also Published As

Publication number Publication date
FR2145356A1 (enrdf_load_stackoverflow) 1973-02-23
CH586421B5 (enrdf_load_stackoverflow) 1977-03-31
CH1025572A4 (enrdf_load_stackoverflow) 1976-09-15
DE2233556A1 (de) 1973-01-25
FR2145356B1 (enrdf_load_stackoverflow) 1974-03-29

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