US3761766A - Electronic indicia display system - Google Patents

Electronic indicia display system Download PDF

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Publication number
US3761766A
US3761766A US00202474A US3761766DA US3761766A US 3761766 A US3761766 A US 3761766A US 00202474 A US00202474 A US 00202474A US 3761766D A US3761766D A US 3761766DA US 3761766 A US3761766 A US 3761766A
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signal
tubes
indicating
clock pulse
grids
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US00202474A
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English (en)
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I Hatano
A Nagano
K Urasaki
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Omron Corp
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Omron Tateisi Electronics Co
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/04—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions
    • G09G3/06—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions using controlled light sources
    • G09G3/10—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions using controlled light sources using gas tubes

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  • ABSTRACT An electronic indicia display system having a plurality of figure indicating discharge tubes wherein an improvement is made to eliminate unnecessary luminance of one or more anode segments which results from the pulse deformation. To this end, the generation and termination of either the input signal to the anodes or the input signal to the grid of the tube is delayed and accelerated, respectively, with respect to the other input signal.
  • the present invention relates to an improved indicating system and, more particularly, to an improved indicia display device having a plurality of figure indicating discharge tubes wherein the provision has been made for eliminating the luminance interference in which condition two figures to be successively illuminated by means of adjacently located different discharge tubes are illuminated in a superimposed manner.
  • luminance interference as hereinabove and hereinafter employed will be defined.
  • a figure indicating discharge tube largely employed in an indicia display device of, for example, an electronic desktop calculator or the like is generally in the form of a triode having a filament or cathode C, a plurality of anode segments P,, P and P, arranged to display predetermined indicia and a grid G for controlling the flow of electrons from the cathode C to the anode segments P,, P P,, such as shown in FIGS. 1 and 2. All of these elements of the discharge tube are enclosed within an inert gas filled envelope (not shown) with a necessary number of lead wires (not shown) extending from these elements to the outside of the envelope.
  • a suitable voltage is applied to the cathode C to cause it to emit electrons toward the anode segments.
  • the electrons thus emitted are accelerated and caused to diverge by the grid G and upon energizing one or more of the anode segments the electrons uniformly bombard the energized anode segments and cause them to luminesce.
  • This operation of a figure indicating discharge tube is well known in the art and, therefore, the details thereof are herein omitted for the sake of brevity.
  • a potential used to energize one or more of the anode segments and a high potential applied to the grid G relative to the cathode potential are hereinafter referred to as digit signal" and positional signal," respectively.
  • the indicia display device for example, in an electronic desk-top calculator, is generally provided with a plurality of figure indicating discharge tubes of the above construction, each of these discharge tubes having its own position with respect to a number of digits constituting a decimal number. For example, if a decimal number having up to three digits is to be represented through the indicia display device, a corresponding number of figure indicating discharge tubes is sufficient, as indicated by V,, V, and V in FIG. 1.
  • a digit signal corresponding to any one of the digits of the decimal number for example, a digit signal corresponding to the most significant digit 1" is first applied to each of the discharge tubes V,, V, and V to energize the anode segments P, and P, shaped to represent the digit 1" as shown in FIG. 2, during a time period 0, as shown in FIG. 3, while a positional signal T1 is applied only to the grid G of one of the tubes which is located so as to display the most significant digit. In this condition, even though the digit signal is applied in common to the discharge tubes V,, V, and V only one of the tubes can be illuminated to represent the digit 1" upon application of the positional signal T] to the grid G thereof.
  • a digit signal corresponding to the next most significant digit 2 is applied to each of the discharge tubes V,, V and V to energize the anode segments P P P P and P while a positional signal T2 is applied only to the grid G of the tube V located so as to display the next most significant digit.
  • a positional signal T3 is applied to the grid G of the tube V.
  • each of the discharge tubes V,, V and V, as hereinbefore described is repeated many times per second in different time periods and in a rapid sequence, the human eyes have a tendency to perceive the decimal number 123 displayed by the indicia display device.
  • FIG. 3 shows ideal waveforms of the digit signals and positional signals with respect to various periods of time, wherein none of these waveforms is deformed.
  • the digit signal generated during the time period 0, or 0, exists in the region of the time period 0 or 0,, respectively, such as shown in FIG. 4.
  • the tube V by which the decimal digit 2 is to be displayed through the anode segments P P P P and P displays the digit 2 superimposed with the digit 1 in which condition the anode segment P, is unnecessarily caused to luminisce.
  • luminance interference stands for the occurrence in which a certain figure indicating discharge tube displays a digit superimposed with a different digit which is to be displayed through another figure indicating discharge tube located right or left to the discharge tube which has displayed the superimposed digits.
  • elimination the luminance interference can be accomplished by cutting off one-fourth of a cycle, as indicated by portion ta, of the positional signal in each time period at the beginning of the duration of the positional signal or cutting one-fourth of a cycle, as indicated by portion tb, of the digit signal in each time period at the termination of the duration of the digit signal.
  • FIG. 4(a) the positional signal has been shown in the form of an ideal waveform
  • the luminance interference will be brought about substantially in the same way as brought about by the deformed digit signal at the end of the duration of said digit signal, if the waveform of the positional signal is deformed as indicated by the dotted lines in FIG. 4(a).
  • portions of the waveform of the deformed positional signal should be preferably cut off in a similar manner as hereinbefore described and such as shown in FIG. 4(b).
  • the digit signal or the positional signal has been cut off at the leading or trailing edge thereof in such a way that the cut-off portion of the signal corresponds with one cycle of the clock pulse.
  • the extent of displacement between the digit signal and the positional signal and the direction of such displacement vary depending upon the time constants or other factors of the circuit elements, which cannot be easily predicted at the time of design.
  • the manner in which the both signals are displaced with respect to each other varies even though two circuit components are manufactured according to the same design.
  • the luminance interference cannot be eliminated unless the manner of displacement is otherwise predicted.
  • one essential object of the present invention is to provide an improved indicia display system including a plurality of figure indiciating discharge tubes wherein means for eliminating the luminance interference is provided.
  • Another object of the present invention is to provide an improved indicia display system of the type above referred to wherein the clock pulse employed in synchronizing the operations of circuit components of an electronic calculator is utilized to cut off each portion of the waveform of the digit or positional signal at the beginning and termination of the duration of the signal, each cut-off portion corresponding with a half cycle of the clock pulse.
  • FIG. 1 is a schematic circuit diagram showing the prior art arrangement of an indicia display device of similar character
  • FIG. 2 is a schematic diagram showing an arrangement of anode segments used in a figure indicating tube shaped to represent any one of decimal digits zero through nine;
  • FIG. 3 is a schematic diagram showing various waveforms of the digit signal and the positional signal
  • FIG. 4 is a schematic diagram showing the deformed waveforms of the digit signal and the positional signal
  • FIG. 5 is a schematic diagram showing waveforms of the digit signal and the positional signal achieved by the present invention.
  • FIG. 6 is a circuit diagram of one preferred embodiment of the present invention.
  • FIG. 7 is a schematic diagram showing waveforms of various signals employed in an essential portion of FIG. 6, and
  • FIG. 8 is a circuit diagram of another preferred embodiment of the present invention.
  • each of the digit signals is generated at an interval of four cycles of the first clock pulse CPI.
  • each of the positional signals T1, T2, T3 and so on is generated at an interval of three cycles of a second clock pulse CP2 of which the duration is substantially equal to that of said first clock pulse CPI, but displaced in phase a half cycle with respect to the latter.
  • the positional signals T1, T2, T3 and so on are generated a half cycle of the first clock pulse CPl after the digit signals have been generated. Namely, during a certain time period, the positional signal is generated in response to a first cycle of the clock pulse CP2 and ceases in response to the end of the third cycle of the clock pulse CP2.
  • the waveform of the positional signal represents each portion of the waveform thereof corresponding with a half cycle of the clock pulse CPI substantially cut off, as indicated by 0, and 0,, at the beginning and termination of the duration of said positional signal, respectively.
  • the period in which the figure indicating discharge tube is prevented from being illuminated is substantially equal to the duration of the bit timing pulse and no reduction in the intensity of light transmitted from the discharge takes place as compared with the conventional tube.
  • each portion of the positional signal is cut off at the leading and trailing edges of the waveform thereof, elimination of the luminance interference can be ensured regardless of the direction of displacement of the waveform of the positional signal with respect to the digit signal, vice versa.
  • each portion ofthe digit signal may be cut off at the leading and trailing edges of the waveform thereof.
  • FIG. 6 shows a circuit diagram in which the signal thus processed as hereinbefore described are utilized. However, it is to be noted that, for the sake of brevity, description will be made in connection with the display device having three figure indicating discharge tubes V,, V, and V the cathode potential of each of which is maintained at -50 volt.
  • reference character S indicates a digit signal generator capable of generating a digit signal having a square waveform during each time period in synchronism with the clock pulse CPl upon receipt of an output signal from a decoder (not shown) of an electronic calculator, said output signal being indicative of a converted decimal number.
  • This digit signal generator S is provided with a plurality of output terminals e,, e,, and e, individually connected with the gates of MOS transistors Q Q and Q each serving as an inverter, through different MOS transistor Q Q and Q respectively, the gate of each of said transistors 0 Q and Q11 being adapted to receive the clock pulse CPI.
  • each of the transistors Q,,, Q and Q is grounded while the drain thereof is connected with the base of each of tube driving transistors TRl, TR2, and TR3 of PNP type, each of said driving transistors being adapted to control the voltage to be supplied to the anode segments P P and P, of the discharge tubes V V or V
  • the collector of each of said tube driving transistors TRI, TR2, and TR7 is connected with the anode sigments of each discharge tube and on the other hand with, for example, a volt power source XI through resistor R
  • the emitter of each transistor TRI, TR2, and TR7 is grounded while the base thereof is connected with, for example, a 25 volt power source X2 through resistor R
  • Reference character U indicates a positional signal generator capable of generating in succession positional signals T1, T2 and T3 during respective time periods 0,, 0 and 0 in synchronism with the clock pulse CPI.
  • This positional signal generator is provided with a plurality of output terminals U U and U connected with first input terminals of AND gates A,, A and A respectively.
  • These AND gates A A and A; have other second input terminals, respectively, to which a timing pulse t can be commonly applied from a suitable source of the timing pulse, output terminals of which are respectively connected with the gates of MOS transistors O Q and Q through MOS transistors 0 Q and Q
  • the gate of each transistor Q Q and Q is adapted to receive the clock pulse CP2 from a suitable source.
  • the timing pulse t has a duration substantially equal to the sum of the durations of bit timing pulses t t and as shown in FIG. 7, the bit timing pulses t,, t t and t being generated in synchronism with the clock pulses CP2.
  • each of the MOS transistors Q Q, and Q is grounded while the drain thereof is connected with the base of each PNP transistor TRll, TRI2 and TR13 having respective emitters connected with the ground.
  • the base of each transistor Q Q and Q is connected with the power source X2 through resistors R
  • the collectors of the transistors TRIl, TRI2 and TR13 are connected with respective grids of the discharge tubes V V and V and, on the other hand, with the power source X1 through they resistors R respectively.
  • the transistor Q can be switched on, upon receipt of the clock pulse CPI and, as a result thereof, the voltage at the gate of the transistor Q 1 becomes zero. Accordingly, the transistor 0,, can be switched off by the output of the transistor 0,, applied to the gate of said transistor 0,, and the transistor TRl can be brought into the conductive state. Therefore, the anode segment P, of each discharge tube receives zero volts.
  • the positional signals T1, T2 and T3 can be successively generated from the output terminals U,, U, and U, of the positional signal generator U, respectively, which are, in turn, applied to the first input terminals of the AND gates Al, A2 and A3. Since these AND gates are adapted to receive the timing pulse t through their second input terminals, they can be triggered on during different time periods 0,, 6, and 0 to thereby generate an output signal.
  • the output signal from each AND gate, as indicated by T1, T2 and T3 in FIG. 7, is in the form of'pulse synchronized with the clock pulse Cp2, but delayed half a cycle of the clock pulse after the potential at the anode segment P1 has become zero.
  • this pulse T1, T2 or T3 has a duration substantially equal to the sum of the durations of three bit timing pulses, such as shown in FIG. 7. From FIG. 7, it is also clear that, as compared with the digit signal corresponding to one decimal digit, the duration of each of the output pulses T1, T2 and T3 or the positional signals that have passed through the respective AND gates A1, A2 and A3 begins at a time delayed cycle of the clock pulse and ends at the time one-half cycle earlier than the clock pulse diminishes.
  • the discharge tubes V, and V can be respectively illuminated without accompanying the luminance interference.
  • FIG. 8 another embodiment of the present invention is shown as having three figure indicating discharge tubes V,, V, and V, in an arrangement similar to FIG. 6.
  • Reference character S indicates a digit signal generator capable of generating a digit signal having a square waveform during each time period in synchronism with the clock pulse CPl upon receipt of an output signal from a decoder (not shown) of an electronic calculator, said output signal being indicative ofa converted decimal number.
  • Reference characters g, through g indicate MOS transistors inserted between the output terminals of the generator S and the anode segments of each of the discharge tubes V,, V, and V
  • the first clock pulse CPl is adapted to be impressed through an inverter In, upon each MOS transistor g, through g
  • Each transistor g, through g is to conduct during each pulse interval of the clock pulse CPl.
  • one or more outputs of the generator S are applied to the corresponding anode segments of each tube.
  • Reference character U indicates a positional signal generator, the operation of which is synchronized with the second clock pulse CP2 and outputs therefrom are generated every four pulses of the clock pulses CP2 through respective terminals U,, U, and U to thereby impress a positive voltage, at different time periods, upon the grids of the tubes V,, V, and V Inhibit gates A A and A, are disposed between the positional signal generator U and the grid of each of the discharge tubes.
  • the output of a four-scale counter K in which the clock pulses CP2 are counted and the output is produced every four pulses, is connected with the input terminals of each inhibit gate A A, and A so that these gates can generate respective outputs, unless the counter K otherwise completes its counting operation' up to the number four.
  • MOS transistors G1, G2 and G3, each serving as a gating element, are inserted between the output of each inhibit gate A A and A and each grid of the discharge tubes V,, V, and V,,.
  • the gate of each of the MOS transistor G1, G2 and G3 is connected with another inverter In, capable of inverting the clock pulse CP2 so that, as long as the clock pulse CP2 is not applied to the inverter In,, the output of said inverter will be [1] thereby to trigger the transistors G1, G2 and G3 on during different time periods.
  • digit signals can be generated from-the generator S through its output terminals e, and e, which are, in turn, applied to the anode segments P, and P, of each of the figure indicating discharge tubes V,, V, and V
  • a positional signal Tl can be generated from the output terminal U, of the positional signal generator U, which is, in turn, applied to the inhibit gate A
  • this signal from the generator U is delayed /5 cycle of the clock pulse CPl with respect to the digit signal, as mentioned above.
  • the counter K upon receipt of the clock pulse CP2 commences to count the number of pulses. However, no output signal is generated from the counter K unless the number of pulses counted thereby exceeds three during the time period 0, and, accordingly, no signal is applied to the inhibit gate A,. Under this condition, the gate A, is in theconductive state so that the positional signal Tl from the output terminal U, of the positional signal generator U can be applied to the source of the MOS transistor G1. This transistor G1 can be brought into conductive state by the signal from the inverter In, which is generated during a period in which no clock pulse CP2 is applied to the inverter In,.
  • the positional signal can be applied to the grid G of the discharge tube V,.
  • the tube V upon receipt of this positional signal, the tube V, can be illuminated to display a number 1.
  • the counter K upon computation up to four pulses during the same time period 0,, the counter K generates an output signal to the input terminal of the gate A.,.
  • the gate A Upon receipt of the output signal from the counter K, the gate A can be brought into the conductive state which can be maintained until the counter K is reset, During this period, application of the positional signal T1 to the grid G of the discharge tube V, can be prohibited and, therefore, this discharge tube V, can be brought into an inoperative condition.
  • the discharge tube V can be brought into the operative condition 1% cycle of the clock pulse delayed at the beginning of the time period 0,, canbe maintained in the operative condition during three cycles of the clock pulse and finally, can be brought into the inoperative condition cycle earlier than the end of the time period 0,.
  • the generator S generates digit signals indicative of a decimal number 2" through its output terminals e,, e,,, e,, e, and e,,, which are, in turn, applied to the anode segments P P P,, P, and P of each of the figure indicating discharge tubes V,, V, and V,,.
  • the positional signal generator U generates the positional signal T2 in response to the clock pulse CP2 during time period 0,, which is, in turn, applied to the grid G of the discharge tube'V, in a similar manner as afforded during the time period 0,.
  • the figure indicating discharge tube V can be operated substantially in the same way as the tube V, during the time period 02.
  • the number 123 can be displayed and perceived by the human eyes without any difficulty in identifying the number 123.
  • An indicating system for displaying indicia comprising:
  • indicating tubes each having a filament, a plurality of anode segments shaped to display predetermined indicia and a grid for controlling the flow of electrons from the filament to the anodes;
  • circuit means interconnected with the anode segments of each indicating tube, for applying a high potential to select anode segments of said tubes in response to a first input signal fed to said circuit means; and means, connected with the grids of said indicating tubes, for operating selected tubes, by applying a high potential to the grids of the selected tubes and a low potential to the grids of the other tubes in response to a second input signal fed to said lastmentioned means, whereby portions of the waveforms of either one of said first and second input signals respectively applied to said circuit means and said last -mentioned means are cut off at the beginning and termination of time periods allocated to said indicating tubes for a predetermined period of time substantially equal to one-half cycle of a clock pulse used to determine said time periods to thereby reduce the pulse width of said cut-off input signals.
  • circuit means interconnected with the anode segments for each indicating tube for applying a high potential to selected anode segments of said indicating tubes in response to a first input signal fed to said circuit means;
  • first generator means for supplying a digit signal in the form of pules to be coupled to said anode segments of the indicating tubes, each of said pulses being generated therefrom in synchronism with a clock pulse used to determine the duration of time periods allocated to said indicating tubes and having a duration substantially equal to the sum of a number of said clock pulses first gating means for transmitting said digit signal to said circuit means;
  • second gating means for transmitting a signal to said second generator means, said last-mentioned signal being generated upon receipt of said positional signal during each time interval from said second generator means one-half cycle of said clock pulse delayed from the beginning of one time interval and capable of terminating one-half cycle of a clock pulse earlier than the end of said time interval.
  • each of said first gating means comprises a first clock pulse, to thereby pass therethrough said digit signal and a second gating element capable of applying the output of said first gating element to said circuit means.
  • each of said second gating means comprises an AND gate having one input terminal adapted to receive the positional signal from the positional signal generator means and another input terminal adapted to receive a signal generated during three cycles of the clock pulse in one time period and another AND gating element adapted to be triggered on by another clock pulse displaced half a cycle relative to the firstmentioned clock pulse for applying the positional signal to the grid of a tube.
  • An indicating system for displaying indicia comprising:
  • indicating tubes each having a filament, a plurality of anode segments shaped to display predetermined indicia and a grid for controlling the flow of electrons from the filament to the anodes;
  • first generator means for generating a digit signal in the form of pulses to said anode segments of said indicating tubes, each of said pulses being generated therefrom in synchronism with a clock pulse used to determine the duration of time intervals allocated to said indicating tubes and having a duration substantially equal to the sum of a number of said clock pulses;
  • gating elements each capable of being triggered by a signal in the form of an inverted clock pulse to thereby apply said digit signal to the anode segments of each of the indicating tubes;
  • a second generator means for supplying a positional signal to the grids of the indicating tubes during different time intervals in response to a second clock pulse which is b cycle displaced relative to said first-mentioned clock pulse, said positional signal having a duration substantially equal to that of each time interval;
  • a counter capable of generating an output signal for every four of said second clock pulses
  • inhibit gating elements each having one input terminal adapted to receive the positional signal from said second generator means and another input terminal adapted to receive the output signal from said counter;
  • An indicating system for displaying indicia comprising:
  • indicating tubes each having a filament, a plurality of anode segments shaped to display predetermined indicia, and a grid for controllint the flow of electrons from the filament to the anodes;
  • second means responsive to a first indicia signal having a prescribed duration, for supplying a high potential to selected anode segments of said tubes;
  • third means coupled to the grids of said tubes, for
  • said third means including control means, responsive to successive indicia signals, for supplying successive energizing signals to the control grids of said plurality of tubes, said energizing signals being supplied to said grids a predetermined period of time delayed by a delay circuit after the initiation of the duration of the signal to be applied to the anode segments, and terminating a second predetermined period of time corresponding to one bit timing earlier than the termination of the duration of said signal to be applied to the anode segments the length of time between said start and termination of the supply of an energizing signal being sufficient to be integrated by the human eye.
  • said third means further includes first gate means, responsive to a first series of clock pulses and said first indicia signal, for gating said indicia signal to the grids of said tubes during the receipt of a predetermined number of clock pulses.
  • said prescribed duration of said first indicia signal corresponds to an integral number of said clock pulses and said predetermined number of clock pulses is less than said integral number of clock pulses.
  • said first gating means comprises a plurality of field effect transistors coupled between the grids of said tubes and a set of terminals receiving said clock pulses.
  • said second means comprises second gate means, responsive to a second series of clock pulses and a series of digital signals for gating said digital signals to said selective anodes.
  • each of said first and second gate means comprises a plurality of field effect transistors coupled between terminals receiving said first and second respective series of clock pulses and the grids and anodes of said tubes.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
US00202474A 1970-11-25 1971-11-26 Electronic indicia display system Expired - Lifetime US3761766A (en)

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CA (1) CA954206A (de)
DE (1) DE2158012C3 (de)
FR (1) FR2116024A5 (de)
GB (1) GB1368815A (de)
IT (1) IT942943B (de)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4204209A (en) * 1977-11-07 1980-05-20 Nippon Electric Kagoshima, Ltd. Fluorescent display device comprising a pair of anode connection groups
US4453128A (en) * 1981-04-30 1984-06-05 Pitney Bowes Inc. Digital display testing circuit
US20030230987A1 (en) * 2002-06-12 2003-12-18 Bernd Raunig Driver circuit for a vacuum fluorescence display

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4869434A (de) * 1971-12-22 1973-09-20
NL169380C (nl) * 1975-05-09 1982-07-01 Philips Nv Tekenweergeefinrichting.
DE2826737C2 (de) * 1978-06-19 1982-08-12 Kienzle Apparate Gmbh, 7730 Villingen-Schwenningen Schaltungsanordnung zum Betrieb einer mehrstelligen Fluoreszenz-Anzeigeeinrichtung
JPS58162988A (ja) * 1982-03-23 1983-09-27 日本電気株式会社 表示装置

Citations (2)

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Publication number Priority date Publication date Assignee Title
US3509420A (en) * 1968-05-02 1970-04-28 Burroughs Corp Driver circuits for display devices with spurious glow eliminating circuit
US3679933A (en) * 1968-12-23 1972-07-25 Sony Corp Display system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3509420A (en) * 1968-05-02 1970-04-28 Burroughs Corp Driver circuits for display devices with spurious glow eliminating circuit
US3679933A (en) * 1968-12-23 1972-07-25 Sony Corp Display system

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4204209A (en) * 1977-11-07 1980-05-20 Nippon Electric Kagoshima, Ltd. Fluorescent display device comprising a pair of anode connection groups
US4453128A (en) * 1981-04-30 1984-06-05 Pitney Bowes Inc. Digital display testing circuit
US20030230987A1 (en) * 2002-06-12 2003-12-18 Bernd Raunig Driver circuit for a vacuum fluorescence display
US6933676B2 (en) 2002-06-12 2005-08-23 Diehl Ako Stiftung & Co. Kg Driver circuit for a vacuum fluorescence display
DE10225996B4 (de) * 2002-06-12 2006-01-12 Diehl Ako Stiftung & Co. Kg Ansteuerschaltung für eine Vakuumfluoreszenz-Anzeige

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CA954206A (en) 1974-09-03
GB1368815A (en) 1974-10-02
FR2116024A5 (de) 1972-07-07
IT942943B (it) 1973-04-02
DE2158012A1 (de) 1972-05-31
DE2158012C3 (de) 1974-05-09

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