US3686661A

US3686661A - Glow discharge matrix display with improved addressing means

Info

Publication number: US3686661A
Application number: US52441A
Authority: US
Inventors: Graham Trevor Sharpless
Original assignee: US Philips Corp
Current assignee: US Philips Corp
Priority date: 1969-07-04
Filing date: 1970-07-06
Publication date: 1972-08-22
Anticipated expiration: 1989-08-22
Also published as: DE2033035B2; FR2054037A5; DE2033035A1; NL7009686A; GB1280875A; US3793629A

Abstract

A display system comprising glow discharge cells located in a rectangular two dimensional matrix at the crossover points formed by a coordinate array of row and column conductors. The cells have an ignition voltage VS that is higher than its ''''hold'''' voltage VM. A voltage VR is applied in sequence to the row conductors for a given dwell time. A column register selectively applies a voltage VC to given ones of the column conductors in accordance with the symbol to be displayed. The column voltages VC are applied for only a fraction of the row dwell time, the remainder of the dwell time being used to fill the column register with column addressing data for the next row to be energized. The ignited cells are held on during the remainder of the dwell time by a bias voltage VB which, in combination with the row voltage VR, exceeds the hold voltage of the cell. Constant cell illumination is maintained by reducing the value of a current limiting resistor in series with each cell upon termination of the column voltage VC.

Description

United States Patent Sharpless [54] GLOW DISCHARGE MATRIX DISPLAY WITH IMPROVED ADDRESSING MEANS [72] Inventor: Graham Trevor Sharpless, Burgess Hill, England [73] Assignee: U.S. Philips Corporation [22] Filed: July 6, 1970 [21] Appl. No.: 52,441

[30] Foreign Application Priority Data July 4, 1969 Great Britain ..'.33,771 [69 [52] us. Cl ..340/324 R, 315/169TV 51 Int. Cl ..H05b 41/24 [58] Field of Search.....340/324 R, 343; 315/169 TV, 315/122, 126, 100, DIG. 5, DIG. 7

[56] References Cited UNITED STATES PATENTS 3,499,167 3/1970 Baker et a]. ..315/169 TV ADA RSR

ROW PULSES CLOCK 815 kHz PULSES MHZ 875 kHz Unblanking 12 u'S every H4115 15 3,686,661 1 51 Aug. 22, 1972 3,356,898 l2/l967 Dano ..315/169 TV Primary Examiner-Thomas B. l-labecker Assistant Examiner-Marshall M. Curtis Attorney-F rank R. Trifari [57] ABSTRACT A display system comprising glow discharge cells located in a rectangular two dimensional matrix at the crossover points formed by a coordinate array of row and column conductors. The cells have an ignition voltage V that is higher than its hold" voltage V A voltage V is applied in sequence to the row conductors for a given dwell time. A column register selectively applies a voltage V to given ones of the column conductors in accordance with the symbol to be displayed. The column voltages V are applied for only a fraction of the row dwell time, the remainder of the dwell time being used to fill the columnregister with column addressing data for the next row to be energized. The ignited cells are held on during the remainder of the dwell time by a bias voltage V which, in combination with the row voltage V exceeds the hold voltage of the cell. Constant cell illumination is maintained by reducing the value of a current limiting resistor in series with each cell upon termination of the column voltage V 16 Claims, 8 Drawing Figures CSR 28 MHz CLOCK PULS ES Patented Aug. 22, 1972 6 Sheets-Sheet l 25 LINES OF 32 CHARACTERS o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o rial:

Fig.1

INVEXTOR. GRAHAM T. SHARPL ESS AGENT Patented Aug. 22, 1972 3,686,661

6 Sheets-Sheet 2 ADA RSR

ROW PU LSES CLOCK 8-75 kHz PULSES 2-8 MHz GA 875 kHz Unbtanking 12 u's every 114,us.

2-8 MHz CLOCK PULS ES Fig.2

INVEXTOR.

GRAHAM T- SHARPL ESS AGE T Patented Aug. 22, 1972 3,686,661

6 Sheets-Sheet 3 v [max] V [min] h V [min] q Fig. 3

INVENTOR. GRAHAM T- SHARPLESS AGE Patented Aug. 22, 1972 3,686,661

6 Sheets-Sheet 4 RSR Fig.4

IXVEXTOR. GRAHAM T. SHAR PLESS AGE NT Patented Aug. 22, 1972 3,686,661

6 Sheets-Sheet 5 Cathode address period Register fill period c IR 1 VOLTAGE AT IR I 1 CATHODE I delay time INVENTOR.

GRAHAM T- SHAR PLE 58 BY 324 ILLfi;

AGEN

Patented Aug. 22, 1972 3,686,661

6 Sheets-Sheet 6 VON VOFF

I mA I Fig. 7 b

INVENTOR. GRAHAM T. SHARPLESS AGENT GLOW DISCHARGE MATRIX DISPLAY WITH IMPROVED ADDRESSING MEANS This invention relates to electrical display devices of the kind comprising a two dimensional matrix of lightemitting elements, for example, glow discharge cells or light-emitting diodes, which are connected at respective cross-points formed by two groups of co-ordinate conductors and each of which can be illuminated selectively by suitable energizing signals applied contemporaneously to the two conductors, one in each group, between which the element is connected, by an addressing circuit arrangement of the device.

Two-dimensional matrices of glow discharge cells for electrical display devices of the above kind are described in US. 'Pat. No. 3,553,458 and in co-pending US. Pat. application Ser. No. 108,695, filed Jan. 22, 1971. The two-dimensional matrix described in the above-identified patent Application is a small 5 X 7 cell matrix of glow discharge cells and is suitable for displaying one alpha-numeric character. A plurality of similar small cell matrices can be used to form a composite panel of larger size suitable for displaying a relatively large number of alpha-numeric characters simultaneously. A typical large size panel may comprise a 200 (row) X 200 (column) two-dimensional matrix of glow discharge cells. Assuming that each character region of this larger size panel comprises 6 X 8 =48 cells, of which 5 X 7 35 are active cells for character formation and the remaining cells provide guard bands for spacing apart adjacent characters and adjacent lines of characters, then lines of 33 alpha-numeric characters (825 characters in all) can be displayed on the panel simultaneously.

The words row and column are used, and will be so used hereinafter, solely to distinguish between the co-ordinate lines of light-emitting elements which form the two-dimensional matrix of an electrical display device of the kind referred to. Thus, either of the two groups of co-ordinate lines of elements can be termed row elements with the elements of the other group being termed column elements. The two groups of co-ordinate conductors which form the cross-points will be referred to, correspondingly, as row conductors and column conductors.

The addressing circuit arrangement of an electrical display device of the kind referred to is required to address the two-dimensional matrix of the device with energizing signals appropriate for illuminating selectively the light-emitting elements of the matrix to provide a visual display of alpha-numeric characters or other information. The selective energization of the light-emitting elements to produce the visual display can be effected by addressing each row of elements in turn with energizing signals applied to the row conductors in a recurrent scanning cycle and by arranging that during the period that each row is being addressed, the columns of elements are addressed selectively with energizing signals applied to selected column conduc tors which pertain to those elements in the row that are to form discrete parts of the characters or other information to be displayed. This addressing of the columns is determined by coded electrical signals that represent the characters or other information to be displayed. Thus, those elements, and only those elements, are addressed with coincident energizing signals and are therefore illuminated. Assuming that a plurality of lines of characters, with each line containing a plurality of characters, are to be displayed, and assuming that each line of characters extends over several rows (e.g. seven) of light-emitting elements, then it will be appreciated that as the rows are addressed in turn in the scanning cycle, the characters in each line are built up row-by-row as a whole, and the lines of characters are built-up line-by-line in succession. Thus, with a sufficiently fast scanning rate, the effect will be the visual display of the plurality of lines of characters simultaneously.

For a satisfactory display using this recurrent scanning cycle mode of operation (which will be referred to hereinafter as the line-dumping mode"), a field rate of 50 Hz is desirable in order to prevent flicker, that is, the matrix is scanned row-by-row 50 times per second. Thus for a 200 X 200 element matrix a row rate of 50 X 200 10 KHz (8.75 KHz) is necessary. This means that the row dwell time is p5 (1 l4 ,u.S) during which time each element which is to be energized in a row should be held energized for as long a time as possible during the 100 p5 in order to achieve maximum brightness. However, in the case of a glow discharge cell, at least 10 p8 of the row dwell time is taken up by an inherent delay which occurs before the discharge of an energized cell will ignite and of the remaining 90 8 during which the cell could be held energized, some of this 90 ,uS is required for filling a column register in dependence on the coded electrical signals for the selective addressing of the cell columns. In order to keep the column addressing time at a maximum, the column register fill time may be, say, 10 S (11.4 p8) so that the actual column addressing time is 90 S; which means that the on time of the cells is 80 [1S due to their inherent ignition delay. This means that if the column register is filled serially with coded electrical signals for column addressing in the 10 us which is allocated for this purpose a stepping or clock rate of 10 X 200 20 MHz is necessary. In practice, this clock rate can be reduced slightly because there may be only active cell columns and active cell rows for character formation, the remaining row and column cells forming the guard bands, as aforesaid. The alternative values given in brackets in the preceding part of this paragraph relate to this lesser number of active row and column cells.

A reduction in the clock rate can be obtained by using two column registers alternately so that each whole row dwell time is available for filling one column register in respect of the selective addressing of the cell columns during the next row dwell time, while the other column register is effecting the selective addressing of the cell columns during the current row dwell time, the latter register having been filled during the preceding row dwell time. This use of two column registers at a slower clock rate permits their realization and the realization of the addressing circuit arrangement using cheap logic circuits, for instance MOS logic instead of more expansive bipolar logic circuits (e.g. 'ITLs), which would be needed in the case of a single column register operating at the higher clock rate. However, the use of two column registers in this way means that the number of register bit positions required is twice the actual number used for column addressing. In a cognate co-pending US. application, Ser. No.

81,008, filed Oct. 15, 1970, there is described an electrical display device of the kind referred to having an addressing circuit arrangement which uses the linedumping mode" of operation, and which fulfils the object of column addressing using column register means which require only the same number of register bit positions as a single column register but which enable a significantly slower clock rate to be used, for a given column addressing time, than would be required for filling serially a single column register. In this addressing circuit arrangement the column register means is adapted to receive groups of coded electrical signals, the signals in successive groups pertaining to respective different pluralities of n columns to be addressed and the signals in each group being applied to the column register means in parallel, the column register means being adapted to be stepped by clock pulses of the addressing circuit arrangement in such manner that the signals in each group are transferred along the column register means in parallel to column addressing positions for the columns to which they pertain. In this way, the column register means can be filled using a clock rate of only l/n the clock rate that would be required for filling the column register means serially with coded electrical signals.

The present invention provides an electrical display device of the kind referred to having an addressing circuit arrangement which fulfils the same object but in a different manner. The present invention has the advantage that it can also be embodied in the addressing circuit arrangement of the electrical display device described in the above-identified US. application to provide a further reduction in the clock rate in ac cordance with its own merits.

According to the present invention there is provided an electrical display device of the kind referred to having an addressing circuit arrangement which uses the line-dumping mode of operation (as hereinbefore defined), wherein the light-emitting elements of the matrix have a bistable characteristic such that they can be held illuminated, following energization, by a lesser voltage potential than that required for their initial energization, and wherein column addressing means for supplying energizing signals for addressing the columns are so arranged that these signals are present in each row dwell time at least for the time required to energize the light-emitting elements in conjunction with the row energizing signal but not for the entire row dwell time, said column addressing means being further arranged to replace the column energizing signals for the remainder of the row dwell time by bias signals of lesser magnitude which in conjunction with the row energizing signal maintains the energized elements of the row concerned illuminated for the remainder of the row dwell time.

The present invention thus provides, in effect, temporary row storage in that the on condition of energized light-emitting elements is maintained for the remainder of each row dwell time without the need for the column energizing signals being present for the entire period of each row dwell time. This enables the remainder of each row dwell time following the termination of the column energizing signals to be used to fill the column register in readiness for addressing the columns in respect of the next row to be addressed. As

an example, if the column energizing signals are present for 50 percent of the row dwell time, there will be 50 percent of the row dwell time left in which to fill the column register. Comparing this with the previous 10 percent of the row dwell time which was available for filling the column register in the case where the column addressing time was percent of the row dwell time, the clock rate of the addressing circuit arrangement can be reduced to one-fifth of the previous rate. Furthermore, if the present invention is used in conjunction with the invention of the aforementioned cognate co-pending application, then the clock rate can be reduced overall by a factor of 25 as compared with the clock rate required for filling a single column register serially and without temporary row storage.

Gas discharge diodes in the form of glow discharge cells have a bistable characteristic which is suitable for the purposes of the present invention, and so have semiconductor GaAs diodes for infra-red displays and semiconductor GaAsP diodes for visible red light displays.

In an electrical display device of the kind referred to having an addressing circuit arrangement which uses the line'dumping mode of operation, a limiting resistor would be connected in series with each column conductor to limit the current through each lightemitting element connected to the conductor when the element is in the on condition. In the performance of the present invention as so far described, a decrease in current through an energized light-emitting element due to the replacement of the energizing signal by a bias signal of lesser magnitude would reduce the illumination of the element, which may be undesirable. In order to prevent such a reduction in the illumination of the element, said column addressing means preferably includes, in respect of each column conductor, means responsive at the termination of the column energizing signal applied to the column conductor to reduce the value of a limiting resistor connected thereto suffrciently for the current through the energized lightemitting element concerned to be maintained at substantially the same value as it was when the column energizing signal was present, so that the illumination of the light-emitting element remains substantially unchanged.

In order that the invention may be more fully understood reference will now be made by way in example to the accompanying drawings of which:

FIG. 1 is a fragmentary diagrammatic front view of a two-dimensional matrix of light-emitting elements of an electrical display device of the kind referred to;

FIG. 2 is a block schematic diagram of an electrical display device of the kind referred to;

FIG. 3 shows row and column energizing pulses for the line-dumping mode of operation, 0

FIG. 4 shows typical row and column drive circuits for line-dumping addressing;

FIG. 5 shows a drive circuit, for line-dumping addressing, with means for reducing the value of a limiting resistor;

FIG. 6 shows row and column pulses for FIG. 5; and

FIGS. 7a and 717 show voltage/current characteristics for two types of light-emitting element which are suitable for the purposes of the present invention.

Referring to the drawings, the two-dimensional matrix shown in FIG. 1 is representative of a 200 X 200 two-dimensional matrix of light-emitting elements such as glow discharge cells or light-emitting diodes. Assuming that each character region of this matrix comprises 6 X 8 48 elements of which 5 X 7 35 are active elements for character formation and the remaining elements provide guard bands for spacing apart adjacent characters and adjacent lines of characters, then this matrix can provide 25 lines of 32 alpha-numeric characters (800 characters in all).

In FIG. 2, the 200 X 200 matrix of, say, glow discharge cells is represented at M. Each of the cells (40,000 in all) has an anode and a cathode by which it is connected between one row conductor R and one column conductor C. Two hundred row conductors R are provided as one co-ordinate array for the matrix, and 200 column conductors C are provided as the other ordinate array of matrix. Any one of the cells of the matrix can be illuminated by energizing (i.e. addressing) contemporaneously the particular row conductor and the particular column conductor between which it is connected. For example, of the three cells c1, c2 and c3 exemplifying the matrix M, the cell (:1 will be illuminated by energizing signals applied to row conductor 199 and column conductor 3. It should be mentioned that because certain of the cells in each character region form guard bands, as aforesaid, certain row and column conductors do not have to be addressed. Thus, as shown in FIG. 2, there are only 175 effective row conductors of which conductor 199 is the last, and only 160 effective column conductors of which conductor 191 is the last. This number of efiective row and column conductors also takes into account the fact that in the present instance it is assumed that the display provides 32 characters per line, and not 33 which is in fact the maximum number possible.

Energizing signals for addressing the row conductors R are supplied in turn in a recurrent scanning cycle by a row shift register RSR which is stepped cyclically by 8.75 KHz ROW PULSES applied to its input. The energizing signals are applied to the row conductors R through anode drive circuits ADA. The cycling rate at each row conductor R is thus 50 Hz which is sufficient to avoid brightness flicker of the cells, and the row dwell time is 1 14 pS.

Energizing signals for addressing the column conductors C are supplied by a column shift register CSR through cathode drive circuits CDA. It is the function of the column shift register CSR to address particular column conductors C in dependence on the particular characters that are to be formed for display. To fulfil this function the column shift register CSR is filled with data pertaining to each row of cells in turn, and this data is then fed out from the column shift register CSR in parallel as the addressing signals for those column conductors that pertain to the particular cells of the row that are to be energized. These cells then become energized when their row is addressed by the row shift register RSR.

The column shift register CSR is filled by data applied to it from a character generator CG which is fed from a recirculating store RS with coded electrical signals pertaining to the characters to be displayed. The coded electrical signals constitute input data received from a keyboard K (or a tape reader or computer), this input data being in the form of a seven-bit word per character. This input data per character is received in parallel by the store RS and is read out therefrom in parallel to the character generator CG. The recirculating store RS is driven by 2.8 MHz CLOCK PULSES which are also used to step the column shift register CSR. The data output from the character generator CG to the column shift register CSR is controlled by a row scan register SR which is stepped in synchronism with the row shift register RSR by the 8.75 KHz ROW PUL- SES.

The row scan register SR causes successive groups of coded electrical signals, for energizing one row of cells pertaining to successive characters in turn of a line of characters, to be read out to the column shift register CSR as the character generator CG receives input data for each of these characters in turn from the recirculating store RS. The coded electrical signals in each group are applied to the column shift register CSR in parallel and are stepped along the latter in parallel to the relevant colunm positions under the control of the 2.8 MHz CLOCK PULSES. The filling of the column shift register CSR for one row of 32 characters takes 12 S, the clock pulses being applied to the column shift register CSR for this period in each 114 p8 row dwell time through a gating amplifier GA which is unblanked l2 8 every 114 p.S. The'column addressing signals from the relevant column positions of the column shift register CSR are applied to the cathode drive circuits CDA which are unblanked for lOO p5 in each row dwell time, when the clock pulses are blanked, to cause energizing signals to be applied to the relevant column conductors C. This is repeated seven times per line of characters to build-up the characters row-by-row and, thereafter, lines of characters line-by-line, at a 50 Hz refresh rate to give a visual display of the characters selected.

The foregoing description given with reference to FIGS. 1 and 2 serves merely as an example of an electrical display device of the character referred to having an addressing circuit arrangement which uses the line dumping mode of operation. A fuller description of this device is given in the specification filed in pursuance of the cognate co-pending application which was identified previously. The present invention can be used in this device and also in similar devices which use the line-dumping mode of operation, but in which the column register is filled serially with coded electrical signals rather than in paralleled groups.

Consider now in more detail the energizing of the glow discharge cells of the two-dimensional matrix (M). Any of these cells can become energized (i.e. can have its glow-discharge struck) by energizing (i.e. addressing) simultaneously the particular row conductor and the particular column conductor between which it is connected with respective voltages which together exceed the strike voltage of the cell. Once a cell is struck a maintain (hold) voltage which is less than the strike voltage will maintain the glow-discharge on. The glow-discharge will turn off when the voltage between the anode and cathode of the cell falls below the maintain voltage for a period that is longer than the deionization time of the cell. There is a spread between maximum and minimum strike voltages and between maximum and minimum maintain voltages for a glowdischarge cell and these spreads have to be taken into account in the determination of the voltage magnitudes for the row and column energizing pulses (signals) for the matrix.

FIG. 3 shows the magnitudes of suitable row and column energizing pulses with respect to the strike and maintain voltages V and V for the glow-discharge cells of the matrix. To strike or ignite a glow-discharge cell it is necessary to apply energizing pulses to both appropriate row and column conductors. Assuming that V is a bias voltage present between the anode and cathode of the cell, V is a row pulse applied to the anode, V a column pulse applied to the cathode, and V and V are the strike and maintain voltages with maximum and minimum values) of the cell respectivel tl len B' n c s Ma:) and VB R smia) c StMaar] StMin) V is an enable pulse used for row scanning in the linedumping operation and V the data pulse used for addressing the columns, so that removal of V alone should be sufficient to turn off the glow-discharge. 1.6.

VR SIMa-r) mmn) Equations 3 and 5 show that the pulses should be unsymmetrical. The voltage V unlike V is necessary only to strike the glow discharge. Its removal will only reduce the current through the appropriate glowdischarge cell which will remain on so long as the applied voltage does not drop below the V for that glow discharge cell.

The temporary row storage facility which is proposed by the present invention relies on this last mentioned point. Since V is required only to strike the glowdischarge, it can therefore be removed once the glowdischarge has struck. The rest of the row time can therefore be used to fill a column register in preparation for the addressing of the next row.

However, when V is removed there is an inherent decrease in current through the glow-discharge. The current through each glow-discharge is limited by a resistor in series with each column conductor. The current through such a resistor, R is:

When V is removed the current will decrease to a lower value I unless the limiting resistor R is reduced to a value R so that:

The decrease in current through the glow-discharge would reduce the illumination of the cell which may be undesirable, this being the result if the typical column drive circuit included in FIG. 4 is used. In FIG. 4, transistors Tc are column drive circuit transistors which are controlled by the column shift register CSR, and transistors Tr are row drive circuit transistors which are controlled by the row shift register RSR.

Consider the glow-discharge cell c which is connected across row conductor (199) and column conductor 1(1). When the relevant row and column transistors Tr and To are non-conductive a bias voltage V is present between the anode and cathode of this glowdischarge cell. When transistor Tr is rendered conductive by a pulse applied to its base from the row shift register RSR a row pulse V is applied to row conductor 199. Similarly, when transistor To is rendered conductive by a pulse applied to its base from the column shift register CSR a column pulse V is applied to the column conductor 1. The simultaneous presence of these two pulses causes the strike voltage V of the glow-discharge cell to be exceeded so that its glowdischarge is struck. Once the cell is struck a maintain voltage V which is less than the strike voltage V will maintain the glow-discharge on. The glow-discharge will tum-off when the voltage between the anodeand cathode of the cell falls below the maintain voltage V for a duration longer than the deionization time of the cell. A diode D is included in the column drive circuit to by-pass transients which occur when the glowdischarge is switched off.

In accordance with the present invention the voltage across the cell can be reduced to the maintain voltage V simply by rendering transistor Tc non-conductive to terminate the column pulse on the column conductor 1, while maintaining the row pulse on the row conductor 199 for the remainder of the row dwell time. However, when the transistor Tc is conductive, current through the glow-discharge and through a limiting resistor R which is connected in series with the column conductor is greater by a value V /R than when the transistor To is cut-off. Therefore, there, will be reduced illumination of the glow-discharge if the column (cathode) pulse is of shorter duration than the row (anode) pulse.

This reduced illumination of the glow-discharge, which may be unacceptable, can be overcome by modifying the column drive circuit as shown in FIG. 5. In this modified column drive circuit the limiting resistor R is divided into two resistors R and R so that R R R The relative values of the two resistors R, and R are chosen such that the diode D is just forward biassed when the glow-discharge is struck and the transistor Tc is conductive. As a result, switching off the transistor Tc will cause the diode D to by-pass the glow-discharge current to the bias terminal V so that the resistance in series with the column conductor is now only the resistor R The effect of this is that the magnitude of current through the glow-discharge cell remains substantially unchanged so that there is no reduced illumination of the glow-discharge. When the transistor Tc is switched off and the glow-discharge is extinguished (on removal of the row pulse V,;), the diode I) becomes reverse biassed.

FIG. 6 shows the row and column pulses for the modified column drive circuit of FIG. 5. As can be seen in FIG. 6 the column pulse V is now of shorter duration than the row pulse V the difference in these durations now being available for increasing the register fill period for the column shift register (CSR). FIG. 6 also shows the voltage pulse present at the cathode side of the limiting resistor. After the inherent delay in the striking of the glow-discharge; this voltage rises above V to a value IR and is held there by the clamping action of the diode D (i.e. at a corresponding value 1R When the row pulse V is terminated the cathode voltage returns to V The inherent delay in the striking of the glow-discharge will determine the minimum possible duration for the column pulse V It has been convenient in the foregoing description to exemplify the invention as applied to an electrical display device having a two-dimensional matrix of glowdischarge cells. However, as mentioned previously, it is envisaged that the invention can also be applied to devices having two-dimensional matrices composed of other types of light-emitting elements provided that these elements exhibit the bistable characteristic which is essential for the performance of the invention. This can readily be appreciated from a consideration of FIG. 7 in which (a) is the voltage/current characteristic of a typical gas discharge diode and (b) is the voltage/current characteristic of a light-emitting diode (e.g. a GaAs diode). The bistable behavior of these two types of element can be seen to be very similar and is due to the negative resistance region of their curves between the strike (ON) and maintain (OFF) values of voltage. In the case of the gas discharge diode a typical strike voltage V would be 180 volts, and a typical maintain voltage V would be 130 volts with a maintain current of approximately lmA. In the case of the light-emitting diode typical ON and OFF voltages may be 30 volts and 4 volts, respectively.

It is mentioned in connection with the line-dumping mode of operation referred to herein that the linedumping may be sequential in that successive rows of a matrix are addressed in turn with row pulses. As an alternative, the line-dumping may be performed in a pseudo-random fashion in which the rows are addressed in turn in a predetermined recurrent pattern.

What is claimed is:

1. An electrical display device comprising a coordinate array of row and column conductors, a plurality of light-emitting elements in a matrix connected to said row and column conductors, a row addressing circuit arrangement for said elements which uses the linedumping node of operation, wherein the lightemitting elements of the matrix have a given ignition voltage and a lower hold voltage so as to exhibit a bistable characteristic such that they can be held illuminated, following energization, by a lower voltage than that required for their initial energization, and column addressing means for supplying energizing signals for addressing the columns so that these signals are present during each row dwell time at least for the time required to ignite the light-emitting elements in conjunction with the row energizing signals but not for the entire row dwell time, said column addressing means further including circuit means independent of the light elements for replacing the column energizing signals for the remainder of the row dwell time by bias signals of lesser magnitude which in conjunction with the row energizing signal maintains the energized elements of the row concerned illuminated for the remainder of the row dwell time.

2. A device as claimed in claim 1, wherein said column addressing means includes, for each column conductor, a limiting resistor and means responsive at the termination of the column energizing signal applied to the column conductor for reducing the value of the limiting resistor connected thereto to a value sufficient to maintain the current through the corresponding energized light-emitting element at substantially the same value as it was when the column energizing signal was present, so that the illumination of the lightemitting element remains substantially unchanged.

3. A device as claimed in claim 2, wherein the column addressing means includes, for each column conductor, a drive circuit having a transistor with its emitter-collector path connected in series with two series-connected limiting resistors to the column conductor, the drive circuit also including a diode connected between the junction of said two limiting resistors and a bias voltage terminal and the relative values of the two limiting resistors being chosen so that, when the transistor is conductive, current through a lightemitting element which is energized as a consequence of the transistor being conductive is limited to a certain value by the two series-connected limiting resistors, whereas when the transistor is non-conductive the current through said energized light-emitting element passes to the bias voltage terminal through said diode and thus through only one of said limiting resistors so as to maintain the current at said certain value.

4. An electrical display device according to claim 1 wherein said matrix of light-emitting elements comprises a two-dimensional matrix of glow discharge cells.

5. An electrical display device according to claim 1 wherein said matrix of light-emitting elements comprises a two-dimensional matrix of light-emitting diodes exhibiting said bistable characteristic.

6. A device as claimed in claim 5, wherein the lightemitting diodes are selected from the group consisting of GaAs diodes and GaAs? diodes.

7. An electrical display system comprising, a matrix array of row and column electrodes, a plurality of lightemitting elements arranged in a matrix and having first and second electrodes connected to given ones of said row and column electrodes, respectively, said lightemitting elements exhibiting a given light emission threshold voltage and a lower hold voltage that is sufficient to maintain a current flow therein to maintain light emission in the element, a row drive circuit coupled to said row electrodes for sequentially applying row voltage signals V thereto for a given row dwell period per row electrode, a column drive circuit with means for selectively coupling column addressing voltage signals V, to the column electrodes as a function of the information to be displayed and simultaneously with said row voltage signals for a period sufficient to ignite given ones of the light-emitting elements but substantially less than said given row dwell period, the magnitude of each of said row and column voltage signals being lower than said threshold voltage but together exceeding the threshold voltage, and said row voltage signal is of a magnitude greater than the hold voltage so as to maintain emission in said given ones of the ignited light-emitting elements for the remainder of the row dwell period subsequent to the removal of the column drive signals.

8. A display system as claimed in claim 7 wherein said column drive circuit includes means for changing the column addressing signals during said remainder of the row dwell period.

9. A display system as claimed in claim 7 wherein said row drive circuit comprises a plurality of switching devices for selectively coupling said row electrodes to a source of DC voltage to provide said row voltage signals V 10. A display system as claimed in claim 9 wherein said column drive circuit comprises a second plurality of switching devices for selectively coupling said column electrodes to a second source of DC voltage to provide said column voltage signals V 11. A display system as claimed in claim 7 wherein the magnitude of the row voltage signal is lower than the hold voltage of said light-emitting elements, said system further comprising, a source of DC bias voltage V of a magnitude less than said hold voltage but sufficient, in combination with the row voltage V to exceed said hold voltage, and means for coupling said bias voltage to a terminal of said light-emitting elements during the remainder of the row dwell period to maintain emission in said given ones of the lightemitting elements.

12. A display system as claimed in claim 11 wherein said column drive circuit includes means for changing the column addressing signals during said remainder of the row dwell period.

13. A display system as claimed in claim 7 wherein the magnitude of the row voltage signal is lower than the hold voltage of said light-emitting elements, said system further comprising, a source of DC bias voltage V of a magnitude less than said hold voltage but sufficient, in combination with the row voltage V to exceed said hold voltage, and means for coupling said bias voltage across the terminals of said light-emitting elements, the voltages being chosen to satisfy the following relationships: V V V, V V V V n s mimi whel'efol' c Slmaz-Y' smun); and B c lmmin); Wherefor R S(ma1) mmm); wherein V and V represent the maximum and minimum expected values, respectively, of the elements threshold voltage, and V and V represent the maximum and minimum expected values, respectively, of the element's hold voltage.

14. A display system as claimed in claim 7 further comprising a plurality of current limiting resistors individually connected to the column electrodes and in series with the light-emitting elements, and a plurality of diodes individually connected to said resistors and poled so as to effectively bypass a part of said resistors upon termination of the column voltage signals thereby to maintain a substantially constant current in the ignited elements for substantially the entire row dwell period.

15. A display system as claimed in claim 14 further comprising a second plurality of resistors individually connected in series with said first plurality of resistors and said light-emitting elements, said diodes being connected between the junction of the series resistors and a temiinal of a source of bias voltage so that the element current flows through both of the series resistors during the time the colurrm voltage signals are applied to the column electrodes and said element current flows to the bras voltage terminal via said diodes during the remainder of the row dwell period when the column voltage signals are terminated thereby to bypass one each of said series resistors to maintain said element constant current.

16. A display system as claimed in claim'8 wherein said light-emitting elements comprise gas discharge cells or light-emitting semiconductor diodes exhibiting and equivalent negative resistance characteristic.

Claims

1. An electrical display device comprising a coordinate array of row and column conductors, a plurality of light-emitting elements in a matrix connected to said row and column conductors, a row addressing circuit arrangement for said elements which uses the ''''line-dumping'''' mode of operation, wherein the light-emitting elements of the matrix have a given ignition voltage and a lower hold voltage so as to exhibit a bistable characteristic such that they can be held illuminated, following energization, by a lower voltage than that required for their initial energization, and column addressing means for supplying energizing signals for addressing the column conductors so that these signals are present during each row dwell time at least for the time required to ignite the light-emitting elements in conjunction with the row energizing signals but not for the entire row dwell time, said column addressing means further including circuit means independent of the light elements for replacing the column energizing signals for the remainder of the row dwell time by bias signals of lesser magnitude which in conjunction with the row energizing signal maintains the energized elements of the row concerned illuminated for the remainder of the row dwell time.

2. A device as claimed in claim 1, wherein said column addressing means includes, for each column conductor, a limiting resistor and means responsive at the termination of the column energizing signal applied to the column conductor for reducing the value of the limiting resistor connected thereto to a value sufficient to maintain the current through the corresponding energized light-emitting element at substantially the same value as it was when the column energizing signal was present so that the illumination of the light-emitting element remains substantially unchanged.

3. A device as claimed in claim 2, wherein the column addressing means includes, for each column conductor, a drive circuit having a transistor with its emitter-collector path connected in series with two series-connected limiting resistors to the column conductor, the drive circuit also including a diode connected between the junction of said two limiting resistors and a bias voltage terminal and the relative values of the two limiting resistors being chosen so that, when the transistor is conductive, current through a light-emitting element which is energized as a consequence of the transistor being conductive is limited to a certain value by the two series-connected limiting resistors, whereas when the transistor is non-conductive the current through said energized light-emitting element passes to the bias voltage terminal through said diode and thus through only one of said limiting resistors so as to maintain the current at said certain value.

4. An electrical display device as claimed in claim 1 wherein said matrix of light-emitting elements comprises a two-dimensional matrix of glow discharge cells.

5. An electrical display device as claimed in claim 1 wherein said matrix of light-emitting elements comprises a two-dimensional matrix of light-emitting diodes exhibiting said bistable characteristic.

6. A device as claimed in claim 5, wherein the light-emitting diodes are selected from the group consisting of GaAs diodes and GaAsP diodes.

7. An electrical display system comprising, a matrix array of row and column electrodes, a plurality of light-emitting elements arranged in a matrix and having first and second electrodes connected to given ones of said row and column electrodes, respectively, said light-emitting elements exhibiting a given light emission threshold voltage and a lower hold voltage that is sufficient to maintain a current flow therein to maintain light eMission in the element, a row drive circuit coupled to said row electrodes for sequentially applying row voltage signals VR thereto for a given row dwell period per row electrode, a column drive circuit with means for selectively coupling column addressing voltage signals Vc to the column electrodes as a function of the information to be displayed and simultaneously with said row voltage signals for a period sufficient to ignite given ones of the light-emitting elements but substantially less than said given row dwell period, the magnitude of each of said row and column voltage signals being lower than said threshold voltage but together exceeding the threshold voltage, and said row voltage signal is of a magnitude greater than the hold voltage so as to maintain emission in said given ones of the ignited light-emitting elements for the remainder of the row dwell period subsequent to the removal of the column drive signals.

9. A display system as claimed in claim 7 wherein said row drive circuit comprises a plurality of switching devices for selectively coupling said row electrodes to a source of DC voltage to provide said row voltage signals VR.

10. A display system as claimed in claim 9 wherein said column drive circuit comprises a second plurality of switching devices for selectively coupling said column electrodes to a second source of DC voltage to provide said column voltage signals VC.

11. A display system as claimed in claim 7 wherein the magnitude of the row voltage signal is lower than the hold voltage of said light-emitting elements, said system further comprising, a source of DC bias voltage VB of a magnitude less than said hold voltage but sufficient, in combination with the row voltage VR, to exceed said hold voltage, and means for coupling said bias voltage to a terminal of said light-emitting elements during the remainder of the row dwell period to maintain emission in said given ones of the light-emitting elements.

13. A display system as claimed in claim 7 wherein the magnitude of the row voltage signal is lower than the hold voltage of said light-emitting elements, said system further comprising, a source of DC bias voltage VB of a magnitude less than said hold voltage but sufficient, in combination with the row voltage VR, to exceed said hold voltage, and means for coupling said bias voltage across the terminals of said light-emitting elements, the voltages being chosen to satisfy the following relationships: VR>VC; VB + VR + VC>VS(max); VB + VR<VS(min); wherefor VC>VS(max) - VS(min); and VB + VC<VM(min); wherefor VR> VS(max) - VM(min); wherein VS(max) and VS(min) represent the maximum and minimum expected values, respectively, of the element''s threshold voltage, and VM(max) and VM(min) represent the maximum and minimum expected values, respectively, of the element''s hold voltage.

15. A display system as claimed in claim 14 further comprising a second plurality of resistors individually connected in series with said first plurality of resistors and said light-emitting elements, said diodes being connected between the junction of the series resistors and a terminal of a source of bias voltage so that the element current flows through both of the series resistors during the time the column voltage signals are applied to the column electrodes and said element current flows to the bias voltage terminal via said diodes during the remainder of the row dwell period when the column voltage signals are terminated thereby to bypass one each of said series resistors to maintain said element constant current.

16. A display system as claimed in claim 8 wherein said light-emitting elements comprise gas discharge cells or light-emitting semiconductor diodes exhibiting an equivalent negative resistance characteristic.