US3745562A - Digital transmission system with frequency weighted noise reduction - Google Patents

Digital transmission system with frequency weighted noise reduction Download PDF

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US3745562A
US3745562A US00214051A US3745562DA US3745562A US 3745562 A US3745562 A US 3745562A US 00214051 A US00214051 A US 00214051A US 3745562D A US3745562D A US 3745562DA US 3745562 A US3745562 A US 3745562A
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A Rosenbaum
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AT&T Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/04—Differential modulation with several bits, e.g. differential pulse code modulation [DPCM]
    • H03M3/042—Differential modulation with several bits, e.g. differential pulse code modulation [DPCM] with adaptable step size, e.g. adaptive differential pulse code modulation [ADPCM]

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  • No.: 214,051 developed in N summing circuits.
  • the first summing circuit has the present sample of the analog signal as an input and the other summing circuits have one of (5 IIIIIIII 340/347 ;52:333; (N-l) future samples applied to their inputs, respec- [58] Fie'm T 325/38 tively.
  • a local decoder at the output of the quantizer "5 333/18 generates a reconstruction or approximation of the analog signal and applies it to each of the summing circuits.
  • PCM pulse code modulation
  • an input analog signal is sampled at or above the Nyquist rate. These samples are then applied to a quantizer which typically has the input signal range divided into an arbitrary number of quantizing intervals.
  • the output generated by the quantizer is the digital representation of the quantizing level that most closely approximates the sample.
  • the digital signal generated depends not on the absolute value of the input signal but on the difference between the present sample and some predicted value. Since in either case there is rarely a quantizing level or predicted value which is exactly the same as the input analog signal, there will be a difference between the input analog signal and the signal recon structed from its digital representation. This difference is called the quantizing noise.
  • information about past and future samples of the input signal can be used to code the present sample in such a way as to reduce the quantizing noise.
  • future samples give the coder information about any change of direction-in the input signal which is about to occur.
  • past samples show the direction in which the signal was going previously.
  • quantizing errors are calculated by subtracting the output of a local decoder from the input signal. These quantizing errors are then stored and used to vary the quantizing levels in the quantizer or to aid in predicting what the next sample will be. If these quantizing errors are properly weighted they can be used in a way which will cause a reduction in the quantizing noise in a particular frequency band with the sacrifice of increased noise in other parts of the frequency spec rum.
  • the present invention is directed to reduction of the frequency weighted quantizing noise in a digital transmission system by selecting the output code; according to the past, present and future samples of the input signal along with the possible decoder reconstructions; that minimizes this noise.
  • This has the advantage of greater efficiency since all the available information about the signal and the possible coding choices is used to reduce the noise in the band of interest without regard to the remaining frequency spectrum.
  • This invention also provides for the simultaneous generation of groups of output bits.
  • a Delta modulator is arranged to make use of the present and one future sample and three past errors.
  • this Delta modulator an input analog signal is applied to a sampling circuit which samples it at several times the Nyquist rate.
  • the output of the sampling circuit is passed through a first delay line which delays the signal for one sampling period. If the output of this first delay line is defined as the present sample, then the output of the sampling circuit will represent a sample which is one sampling time in the future.
  • the present sample and the future sample are then applied to first and second summing means, respectively. These summing means algebraically combine all the signals applied to their inputs and perform the same function as the summing circuit in a conventional Delta modulator.
  • the outputs of the first and second summing means are applied to the two inputs of a two-dimensional quantizer, respectively.
  • This quantizer simultaneously generates two output digits in joint response to the inputs from the two summing means.
  • the decision boundaries in the quantizer are particularly chosen so that a code is generated which minimizes the frequency weighted quantizing noise when used in conjunction with a feedback signal, to be described later.
  • the two outputs of the quantizer are then sequentially applied to a local decoder whose output will be an analog equivalent of the digital representation of the input signal. As in a conventional Delta modulator, this signal is applied to the first and second summing means in order to generate a difference signal for the quantizer.
  • the output of the integrator is also subtracted from the present sample in a third summing means. This will generate a signal equivalent to the present quantizing error.
  • This quantizing error is applied to the inputs of a second, third and fourth delay lines.
  • the second delay line delays this present error signal for one sampling period; the third delay line delays the error signal for two sampling periods; and the fourth delay line delays the error signal for three sampling periods.
  • the output of the second delay line is passed through a first multiplier, which effectively multiplies it by a factor b(l).
  • the output of the third delay line passes through a second multiplier, which multiplies it by a factor b(2).
  • the output of the fourth delay line passes through a third multiplier, which multiplies it by a factor b(3).
  • the outputs of these multipliers are summed and applied to a combining circuit.
  • the outputs of the second, third and fourth delay lines are also passed through fourth, fifth and sixth multipliers, respectively.
  • the fourth, fifth and sixth multipliers multiply the outputs of the delay lines by factors b(Z), b(3) and b(4), respectively.
  • the outputs of the fourth, fifth and sixth multipliers are also summed and applied to the combining circuit.
  • this combination of delay lines and multipliers generates information about the past error terms in the encoder. These past error terms are then multiplied by the b coefficients which tend to weight their effect. These b coefficients are determined by the Fourier coefficients of the noise penalty function desired.
  • the combining circuit generates first and second feedback signals which are applied to the first and second summing means, respectively. These feedback signals are used to alter the difference signal from the first and second summing means.
  • This corrected output of -the summing means in conjunction with the specially selected coding boundaries in the two-dimensional quantizer, in effect generates coding combinations, depending on the past, present and future samples and selects the one which gives the minimum quantizing noise in the band of interest.
  • FIG. 1 is a schematic of an illustrative embodiment of the invention
  • FIG. 2 is a graph of the boundaries in the quantizer of FIG. 1;
  • FIG. 3A is a graph of a typical frequency spectrum of the quantizing noise of a standard Delta modulator with a sine wave input
  • FIG. 3B is the graph of a typical noise penalty function
  • FIG. 3C is a graph of the b coefficients corresponding to the penalty function of FIG. 38;
  • FIG. 3D is a graph of a typical frequency spectrum of the quantizing noise using the encoder of FIG. 1',
  • FIG. 4 is an alternative arrangement for the circuit of FIG. 1;
  • FIG. 5 is a schematic of an illustrative embodiment of the invention for large block sizes.
  • any technique employed in a digital transmission system which uses the available coding combinations to reduce the overall noise will be relatively inefficient. Instead, these coding combinations should be used to reduce the noise only in the frequency band where the information is contained, since the other noise will be eliminated by the system filters.
  • the prior art has disclosed methods for reducing some of the in-band noise using past error terms
  • the present invention utilizes both past and future samples of the input signal to greatly reduce the in-band noise. This is accomplished by minimizing at each block encoding an estimate of the weighted noise power, D This estimate is derived from M past errors in conjunction with the N future. errors produced by the next block-N encoding, where block-N refers to the simultaneous encoding of Nsamples of the input signal, one being the present sample and the rest being future samples.
  • D In order to arrive at the minimum weighted noise power, D the system must in effect compute all the kK error patterns, and then generate the digital sequence that results in the error pattern, which gives rise to the least amount of noise in the frequency range of interest.
  • the factors lil and 1b, in FIG. 2 represent the translation of the coordinates in response to the past errors.
  • the minimization of D is achieved by partitioning this new N-dimensional space into K regions, each being identified with an optimum choice of the coding sequence. For the block-2 encoder these regions are indicated by the areas I, II, III, and IV in FIG. 2.
  • the noise is to be reduced only in a particular frequency band, the effect of the various inputs will have to be taken together. This, in part, explains the unusual shape of the boundaries in FIG. 2. Encoding, therefore, reduces to translating the coordinates in the N- dimensional space in response to the past error terms;
  • FIG. 1 is a practical example of the use of this encoding technique.
  • FIG. 1 is an illustrative embodiment of the invention created by modifying a Delta modulator to use a present and one future sample together with three past errors.
  • the input analog signal is applied to sampling circuit 100.
  • This circuit samples the input signal under the control of the local timing clock 160.
  • the output samples, S, of this circuit are applied to a delay circuit 105.
  • This circuit delays the output of the sampler by one sampling time. Therefore, if the output of the delay circuit, S is considered to be the present sample, then the output of the sampler, S is a future sample, one sampling time in the future.
  • the sample, S is applied to one of the positive inputs of combiner circuit and the sample, 8,, is applied to one of the positive inputs of combiner circuit 110.
  • These combiner circuits perform the same function as the difference circuits in a conventional Delta modulator. Therefore, the previously reconstructed signal, 5- from the local decoder is applied to the MINUS inputs of both combiner circuits.
  • feedback signals
  • the output of the quantizer representing the code for the present sample is stored in the next-to-last stage of the shift register and the output code representing the future sample is stored in the last stage.
  • the contents of the next-to-last stage of the shift register are applied to local decoder 130. ln effect, local decoder 130 converts the output digital code stored in the shift register into an analog signal which is a reconstruction of that code, S This reconstruction signal is applied to the negative inputs of combiners 110 and 115 as described above. However, it is also subtracted from the present sample, S in summing circuit 135. This causes the generation of the present quantizing error term, q,,.
  • This error term is applied to delay circuits 141, 142 and 143 of bias computer 140, which delay it for one, two and three timing periods, respectively.
  • the outputs of these delay circuits are applied to multiplier circuits 144, 145 and 146, respectively. These circuits, in effect, multiply the outputs of the delay circuits by the coefficients b(l), b(2) and [1(3), respectively.
  • the outputs of multiplier circuits 144, 145 and 146 are summed in summing circuits 150 and 151 and are applied to input 156 of combiner circuit 155.
  • the outputs of delay circuits 141, 142 and 143 are applied to multipliers 147, 148 and 149, respectively.
  • a present and future sampl are generated and applied to combiner circuits 110 and 115.
  • the analog reconstruction signal from the local decoder is subtracted from the input signals in order to generate difference signals for the quantizer 120.
  • feedback signals U1, and 41 are added to these difference signals. If the b coefficients are given proper values and if the quantiz ing regions in circuits 120 are appropriately chosen, the resulting output code, C, will have minimum quantizing noise for a particular frequency band.
  • the quantizing regions for quantizer 120 are shown in FIG. 2.
  • a determination of the boundaries for the coding regions is made by considering the N- dimensional space mentioned previously.
  • Each of the K possible output codes is associated with an optimum combination of input samples that results in the least amount of weighted quantizing noise.
  • These o timum combinations of source samples are represented by K points in the encoding space.
  • a given point in this encoding space, represented by an actual set of inputs, will then be in a particular region if it is closer to the optimum point of that region than to any other optimum point.
  • these optimum points are denoted by A, B, C and D. Therefore, the boundaries of the various regions are determined by the loci of points which are equidistant from given pairs of optimum points.
  • S is defined as an M-vector of the past inputs and S, is defined as an N-vector of the future inputs, then where the positive subscripts indicate sample periods in the future and the negative ones indicate sample periods in the past.
  • '5, and S can similarly be defined as the local decoder reconstructions of the digital output of the quantizer. Therefore, the past and future error vectors are, respectively,
  • Equation (2) indicates a transpose matrix and B is a transformation matrix which describes the anisotropic na ture of the space.
  • Equation (7) can be used to find the loci of points equidistant from adjacent reconstruction points 3'; and 3]; that is, (PST?) (PS3?) will indicate the equation for the boundary. Equations (2) and (7) then yield E.S.) BNST+ (El-swap All that remains in order to completely define the quantizer of FIG.
  • the matrix B which specifies the anisotropic nature of the space that will result in reduced quantizing noise according to the given noise frequency weighting criterion.
  • All of the error terms both pastand future, represent a finite length record which can be represented by the L dimensional vector 6, where L M N. The components of this vector can then be indexed as iq q
  • the weighted noise power, D To determine the matrix B, the weighted noise power, D must be estimated. This can be accomplished by relying on the Weiner-Khintchine theory which states that the autocorrelation function and the power spectral density are Fourier transforms of each other.
  • the modified spectral density estimate is produced. This can be expressed in matrix form as s, (w) l/L (i x6 2) where the elements of the X matrixare X cos (i-j) tor.
  • the weighted noise power estimate, D,,.,, can be determined by integrating the product of the spectral density and the noise penalty function W(a)).
  • Equation 8 the encoding region boundaries will be determined by Equation (8 and the numerical valuesfor the elements of B by Equation (15).
  • the B matrix will be b 0 1) 1) 1) (2 1) (a 1) (4) B b l) b b b m 1) 2) 1) (1) 1) 0) 1) 1) 1) 2) 1) (a) 1) 2) 1) 1) 1) 1) 1) o) 1) 1) '1) 4) 1) a) 1) 2 1) 1 1) (0 (Hi)
  • the values of the elements of this matrix are determined from Equation (15), depending on the noise penalty function W(w).
  • a typical noise penalty function is shown in FIG. 3B. In this case a reduction of the noise only in the information band (0 to 5 ke) is desired, and so a rectangular function is chosen. However, this function could be any arbitrary non-negative function and does not have to be restricted to a particular frequency range. In fact, it could be used to penalize the noise throughout the entire frequency spectrum.
  • FIG. 3C shows the Fourier coefficients of the function of FIG. 3B which are essentially the elements of the B matrix.
  • the waveform shown in FIG. 3A is a representation of the quantizing noise spectrum of a conventional Delta modulator with a sine wave input.
  • its quantizing noise spectrum can be represented by a curve somewhat like that in FIG. 3D.
  • FIGS. 3A and 3D show that the in-band noise has been decreased at the expense of the out-of-ba'nd noise by using the present invention. However, this out-of-band noise can be removed by the system filters.
  • the decoding rule for the delta modulator is To find the boundary between pattern 0,1 and 1,1 assign 5, to 0,1 and S, to 1,1. Then which is the equation for the boundary.
  • the other boundaries can be determined by using the same procedure on the other possible combination of outputs.
  • Equation (20) the b coefficients always appear normalized with respect to b(0). This is because only the shape of W(w) is important, not its absolute amplitude scale. Since b(0) is the total area under the W(m) function as shown by Equation (15), it may conveniently be scaled such that b(0) 1. In the expressions which follow, this normalization has already been done.
  • FIG. 4 is an illustrative embodiment of a reorganized quantizer which can be expanded to handle the greater number of inputs in larger block length encoders.
  • FIG. 4 is similar to FIG. 1 except that the delay lines have been replaced with analog shift registers and the quantizer has been divided into two circuits 410 and 420, which also include the combiners 110, 115, and 155 of FIG. 1.
  • the input samples are applied to analog shift register 400.
  • This shift register is under the control of the output signal, T, of the local clock.
  • the analog signals are stored in the shift register and translated in response to the timing pulses.
  • the contents of the shift register are applied to the first bit quantizer 410 along with the partial feedback signals 2,, and 2, from summing circuits 441 and 442, respectively.
  • the output of the local decoder 425 is applied to the first bit quantizer.
  • This two-dimensional quantizer merely decides whether the first bit of the code for the two samples should be a 1 or a 0. This is done by determining on which side of the boundary between the 1 regions (land ll of FIG. 2) and the 0 regions (III and IV) the input combination lies. This boundary is indicated by the line drawn inside quantizer 410.
  • the output of this quantizer is fed through switch 415 to the input of local decoder 425 and to the circuit output. This switch 415 is also under the control of the local clock.
  • shift register 400 contents of shift register 400 are shifted one stage, whereby a new input sample, 5,, is loaded into the first stage, and the signal, 8,, (now in the last stage of shift register 400) is applied to the input of the second bit quantizer 420 along with partial feedback signal 2 and the new output of local decoder 425.
  • This one-dimensional quantizer generates the second bit of the code, after switch 415 has changed position so that the output of quantizer 420 can be applied to the input of the local decoder and to the circuit output.
  • This quantizer makes a simple threshold decision based in part on the output of the first bit quantizer through the signal 2 After the second bit is determined switch 415 returns to the output of quantizer 410, which generates the first bit of the code for the block of samples 8, and S, which by then will be stored in shift register 400. With this arrangement, the output code is generated sequentially and each of the quantizers determines only one of the two bits of the output code block.
  • the present sample is subtracted from the output of the local decoder in a summing circuit, 430, in order to generate the error terms, q.
  • These terms are applied to analog shift register 435, which is under the control of the local clock. At each timing pulse the error terms are shifted right one space. Therefore, the contents of the shift register represent the past error terms.
  • the outputs of various stages of shift register 435 are multiplied by the b coefficients and are summed in combiner circuit 440. The output of this circuit is delayed one sampling time by delay circuit 443 before it is summed with the product of the present error term and theb( l) coefficient.
  • This summing operation takes place in summing circuit 441, whose output is the partial feedback signal
  • This signal can be used in the formation of the signals th and 111, in the quantizer. However, as will be shown later, it may not be necessary to form the signals i11 and #1,. With an appropriate arrangement of the quantizer it ispossible to use the partial feedback signals 2, 2,, and ,2, directly.
  • a 0 prefix subscript is used with one of these signals it indicates that it is used in the determination of the first bit of the block of the code and a 1 indicates use in the determination of the sec- 0nd bit in the block.
  • the post-subscripts differentiate between the various partial feedback signals used to determine a code bit.
  • the output of the combiner 440 is also summed with the contents of the last stage of shift register 435 multiplied by the coefficient b(M+l) in summing circuit 442, whose output is partial feedback term
  • This arrangement allows for the simultaneous generation of feedback terms 2,, and 2, with the use of one multistage shift register.
  • the product of b(M+l) and the contents of the last stage of shift register 435 are delayed one sampling period by delay circuit 444.
  • the output of delay circuit 444 is then summed in summing circuit 445 with the output of summing circuit 441, 2 to form the partial feedback signal,
  • the sequentially operating block encoder of FIG. 4 can be implemented using the arrangement in the Oliver patent with two groups of photodiodes forquantizer 410, and a simple threshold detecting circuit for quantizer 420.
  • a different arrangement for the quantizer must be used.
  • This new arrangement will allow this circuit to be expanded to become a block-N encoder, as shown in FIG. 5.
  • the initial step in such an expanded encoder is to make only the first digit decision in a block-N encoding, using M past errors as before. This decision is then used to update the analog reconstruction 5:, to S thereby determining an additional error term, Now the M+l errors can be used to make a first digit decision in the remaining block (N-l) encoding.
  • the analog shift register 500 is the same as the shift register 400 of FIG. 4 except that additional stages have been added to handle the increased number of future input samples.
  • the quantizer has been divided into N separate units.
  • the first digit encoder, 512 is an N dimensional quantizer with inputs from each of the N stages of the analog shift register 500. It generates the first bit of the output code for the block of input samples contained in shift register 500.
  • the second digit encoder, 520 is an (N-l) dimensional quantizer with inputs from all except the first stage of the shift register.
  • the last digit encoder is a one-dimensional quantizer with an input from only the last stage of the shift register.
  • each of the quantizers or digit encoders has partial feedback terms 2 supplied to it, so that the updated effect of past quantizing errors is thereby included in the sequential block decision making process.
  • the outputs of the various quantizing units are collected by commutating switch 515, which applies them to both the circuit output and the input of local decoder 525.
  • This local decoder generates an analog equivalent of the digital code appearing at the output.
  • Difference circuit 530 is used to subtract this analog equivalent signal from the input samples. As with the other circuit arrangements, this creates quantizing error terms which are used in bias computer 540 to generate the partial feedback signals for the various units of the quantizer.
  • the First Digit Encoder has N inputs and circuitry which will differentiate between 2 different coding regions; but generates only the first bit of the code. These regions are divided into two classes, those which have a 0" for the first bit and those which have a 1.
  • the quantizer determines in which of the two classes the combination of input signals belongs. This is done by making all possible comparisons of the relative distance of the source sample combination to pairs of code points where one point is in the 0 class and the other is in the 1 class. The results of these comparisons are logically combined to determine in which class the closest code point lies.
  • Each comparison of code points can be implemented with a different threshold detecting circuit through the use of Equation (8).
  • the code points will be in opposite classes.
  • the threshold circuit determines if the sense of the inequality in Equation (24) is correct or not. If it is, this shows that the input combination is closer to code point than to point 37, and the value of an internal digital bit is set to 1121f it is not, the input combination is closer to point 25 and the internal bit is set to 0. Then the internal digital bits from the comparisons using the other pairs of code points from opposite classes are combined in logic circuits to generate the digit encoder output bit.
  • the code points of FIG. 2 are divided into the 0" class containing codes 0,0 and 0,1, and the 1" class containing 1,] and 1,0. Then four separate circuits are arranged according to Equation (24) to determine if the input is closer to code points A or B than it is to code points C or D. These four circuits will generate internal digital bits, depending on the comparison, according to the following conditions:
  • the quantizer can be expanded to handle any number of future inputs with the only practical limitation being the complexity of the circuitry required for this determination.
  • an encoder for converting an input analog signal into an output digital code comprising:
  • a digital encoder for converting an input analog signal into a digital code comprising:
  • I means for obtaining a present and (N-l future samples of said input analog signal'at a particular sampling rate; a plurality of summing means for combining each sample with a separate feedback signal;
  • quantizing means responsive to the outputs of said plurality of summing means for simultaneously generating the combination of bits of the'digital code, representing the present and (N-l) future samples of the input analog signal;
  • the quantizing means responsive to the present and previously generated quantizing error terms for generating the separate feedback signals, the feedback signals being generated in such a way asto allow the quantizing means to generate the digital code which produces a reduced frequency weighted quantizing error'according to a noise penalty function when taken together with thevpresent and previously generated quantizing error terms.
  • An encoder as claimed 'in claim 2 wherein said means for obtaining a present and ('N--1) future samples of said input analog signal comprises:
  • said quantizing means comprises means for determining in which of a plurality of encoding regions the combination of outputs from said summing means belongs and generating digital bits for the output code whichrepresent that region.
  • An encoder as claimed in claim 7 wherein said means for storing and shifting comprises an'an'a
  • said means for generating an analog equivalent signal comprises:
  • a digital encoder for converting an input analog signal into a digital code comprising:
  • N quantizing means for sequentially generating the output code, the first quantizing means generating the first bit of the code in response to a first partial feedback signal, the presentsample, and the (N-l future samples, the succeeding quantizing means each generating a succeeding bit of the code in response to succeeding separate partial feedback signals and one less sample than the preceding quantizing means, the one less sample being the one least in the future, the N' of said quantizing means generating the last bit of the code in response to a nals being those analog equivalent signals of digital codes having a 1 as the first bit, said zero analog equivalent signals being those analog equivalent signals of digital codes having a as the first bit;
  • a digital encoder as claimed in claim 13 wherein said comparison means comprises circuit means for determining if the input combination is closer to the one Hated quantizing error terms for generating the analo e uivalent si nals than to the zero anal e uivseparate partial feedback signals, the partial feedq 0g q alent signals according to the expression:

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US4059800A (en) * 1976-06-30 1977-11-22 International Business Machines Corporation Digital multi-line companded delta modulator
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US4353060A (en) * 1979-07-13 1982-10-05 Tokyo Shibaura Denki Kabushiki Kaisha Analog to digital converter system with an output stabilizing circuit
US4463343A (en) * 1980-10-16 1984-07-31 Mecilec Method of and device for incremental analogue-to-digital conversion
US4700362A (en) * 1983-10-07 1987-10-13 Dolby Laboratories Licensing Corporation A-D encoder and D-A decoder system
US5150120A (en) * 1991-01-03 1992-09-22 Harris Corp. Multiplexed sigma-delta A/D converter
US5708511A (en) * 1995-03-24 1998-01-13 Eastman Kodak Company Method for adaptively compressing residual digital image data in a DPCM compression system
US6664913B1 (en) * 1995-05-15 2003-12-16 Dolby Laboratories Licensing Corporation Lossless coding method for waveform data
US20090299499A1 (en) * 2001-06-05 2009-12-03 Florentin Woergoetter Correction Signals

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WO2017033962A1 (ja) 2015-08-27 2017-03-02 国立大学法人大阪大学 ゆらぎ発振器、信号検知装置、及び表示装置

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US3631520A (en) * 1968-08-19 1971-12-28 Bell Telephone Labor Inc Predictive coding of speech signals
US3628148A (en) * 1969-12-23 1971-12-14 Bell Telephone Labor Inc Adaptive delta modulation system
US3621396A (en) * 1970-05-08 1971-11-16 Bell Telephone Labor Inc Delta modulation information transmission system
US3742138A (en) * 1971-08-30 1973-06-26 Bell Telephone Labor Inc Predictive delayed encoders

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DE2263757A1 (de) 1973-07-05
IT976174B (it) 1974-08-20
CA991311A (en) 1976-06-15
DE2263757C2 (de) 1982-11-18
GB1370710A (en) 1974-10-16
BE793564A (fr) 1973-04-16
JPS5639577B2 (enrdf_load_stackoverflow) 1981-09-14
JPS4875161A (enrdf_load_stackoverflow) 1973-10-09
SE387796B (sv) 1976-09-13
FR2166220A1 (enrdf_load_stackoverflow) 1973-08-10
NL7217828A (enrdf_load_stackoverflow) 1973-07-03

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