GB1370710A - Digital transmission systems - Google Patents

Abstract

1370710 A/D conversion WESTERN ELECTRIC CO Inc 28 Dec 1972 [30 Dec 1971] 59754/72 Heading G4H An A/D converter comprises means for obtaining a present sample and (N-1) future samples of an input analogue signal, quantizing means for generating a digital output code from the samples, means for deriving an analogue signal from the code, means for generating a quantizing error signal from the difference between the derived analogue signal and the present input signal sample, means for storing M successive, immediately previous, quantizing error signals and means for correcting the quantization of the signal samples in the quantizing means in response to the quantizing error signals so as to produce a reduced frequency-weighted quantizing error in the digital output code. In Fig. 1, a sampler 100 and a delay 105 give a present sample S 0 and a future sample S 1 which are passed through respective combiners 115, 110 (see below) to a quantizer 120 which produces two bits in parallel to an output shift register 125 from which a local decoder 130 produces an analogue signal which is subtracted in the combiners 110, 115 to give #-modulation operation. The decoder 130 output is also subtracted from the present sample S 0 at 135 to give the quantizing error signal q 0 . Weighted sum and difference combinations of progressively delayed (at 141, 142, 143) versions of this are obtained in a bias computer 140 (see Specification for details of 155) to provide additive bias inputs # 0 , # 1 to the combiners 115, 110. The biasing and the quantizing are arranged to reduce quantizing error in a lowfrequency range (at the expense of increased error at higher frequencies but this is eliminated by system filters anyway). The quantizer 120 may use a C.R.T., the outputs of the two combiners 110, 115 being applied to the horizontal and vertical plates respectively, the screen being covered with four groups of photo-diodes corresponding to the four possible 2-bit outputs. In Fig. 4, the present and future samples S 0 , S 1 are supplied from an analogue shift register 400 to a first quantizer 410 to produce a first output bit, then register 400 is shifted by one position and the new present sample (previous future sample) is used by a second quantizer 420 to produce a second output bit. Then there is another shift and the third bit is produced from the first quantizer 410, and so on. A local decoder 425 produces an analogue signal from the digital output and supplies it to the two quantizers 410, 420. This analogue signal is also subtracted from the present sample S 0 at 430 to produce bias signals 1 # 0 , 0 # 0 , 0 # 1 for the quantizers 410, 420 from the circuitry shown, using an analogue shift register 435, weighting (in blocks b), adding (at 440, 441, 442, 445) and delays 443, 444. 444 can be omitted to a good approximation. Fig. 5 (not shown) extends the principle of Fig. 4 to more than two quantizers producing a bit each in turn. If there are N quantizers, the first responds to N input samples, the next to N-1, and so on.