US3710936A - Apparatus for classifying and counting sheets - Google Patents

Apparatus for classifying and counting sheets Download PDF

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Publication number
US3710936A
US3710936A US00196895A US3710936DA US3710936A US 3710936 A US3710936 A US 3710936A US 00196895 A US00196895 A US 00196895A US 3710936D A US3710936D A US 3710936DA US 3710936 A US3710936 A US 3710936A
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Prior art keywords
output
sheets
signal
circuit
classification
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US00196895A
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English (en)
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Y Mizunuma
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Toshiba Corp
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Tokyo Shibaura Electric Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06M—COUNTING MECHANISMS; COUNTING OF OBJECTS NOT OTHERWISE PROVIDED FOR
    • G06M7/00—Counting of objects carried by a conveyor
    • G06M7/02—Counting of objects carried by a conveyor wherein objects ahead of the sensing element are separated to produce a distinct gap between successive objects
    • G06M7/06—Counting of flat articles, e.g. of sheets of paper
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B07—SEPARATING SOLIDS FROM SOLIDS; SORTING
    • B07C—POSTAL SORTING; SORTING INDIVIDUAL ARTICLES, OR BULK MATERIAL FIT TO BE SORTED PIECE-MEAL, e.g. BY PICKING
    • B07C3/00—Sorting according to destination
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
    • B65H—HANDLING THIN OR FILAMENTARY MATERIAL, e.g. SHEETS, WEBS, CABLES
    • B65H29/00—Delivering or advancing articles from machines; Advancing articles to or into piles
    • B65H29/58—Article switches or diverters
    • B65H29/60—Article switches or diverters diverting the stream into alternative paths
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/06—Arrangements for sorting, selecting, merging, or comparing data on individual record carriers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S209/00—Classifying, separating, and assorting solids
    • Y10S209/933—Accumulation receiving separated items

Definitions

  • ABSTRACT Apparatus for classifying and counting sheets, post cards for examples comprises a conveyor for conveying the sheets; a gate associated with the conveyor for deflecting the sheets away from the conveyor; sheet detecting means associated with the conveyor for generating a signal when it detects the sheet; a plurality of receivers for receiving sheets of different classes; check means for determining the classes of the sheets and for generating classification signals; gate driving means responsive to the classification signals and to the signal generated by the sheet detecting means; a first counter associated with the receivers for counting the number of sheets collected in respective receivers; a second counter which adds the number of sheets collected in respective receivers; a comparator for comparing the sum of the numbers of the sheets counted by the second counter with a preset number for determining whether the sum and the preset number coincide with other or not; a third counter for counting the number of wheets counted by the first counter and collected in respective receivers when the comparat
  • This invention relates to apparatus for classifying and counting articles in the form of sheets such as post cards, paper movies, securities and the like and more particularly to such apparatus which classifies a lot of sheets of different types, counts the number of classified sheets for each type and then send them to individual receivers.
  • sheet is used to mean not only a sheet shaped article but also an article of any configuration that can be processed by the apparatus of this invention.
  • the classifying and counting apparatus of the type referred to above is generally constructed to successively check the sheets supplied by from a magazine or reservoir for generating classification signals corresponding to the types of the sheets, classify and counts the sheets and then send the classified sheets to respective receivers in accordance with the classification signals.
  • classification signals corresponding to the types of the sheets
  • onlyone sheet is checked so that two sheets are sent to the same receiver and the not checked sheet will be classified inadvertently.
  • the sheets are divided into several lots and the sheets of each lot is classified, upon occurence of the erroneous classification, it is impossible to know which one of the lots was classified inadvertently by merely checking the cheets in individual receivers so that the result of classification and counting is not reliable.
  • Another object of this invention is to provide an efficient classififying counting apparatus capable of classifying and counting sheets at high accuracies and can indicate the number of sheets classified and received in respective receivers when all sheets of several lots are completely classified and counted.
  • apparatus for classifying and counting sheets comprising, (1) conveyor means for conveying the sheets in a predetermine direction, (2) a gate positioned at an intermediate point of the conveyor means for deflecting the sheets away from the predetermined direction, (3) sheet detecting means positioned at an intermediate point of the conveyor means for generating a signal when it detects the sheet, (4) a plurality of classification receivers adapted to receive sheets of different classes conveyed by the conveyor means, (5) check means for determining the classes of the sheets which are to be received in the corresponding classification receivers, the check means generating classification signals corresponding to the classes, (6) gate driving means responsive to the classification signals and to the signal generated by the sheet detecting means, (7) first counting means associated with the classification receivers for counting the number of sheets collected in the respective classification receivers, (8) second counting means for adding the numbers of the sheets collected in the respective classification receivers, (9) a comparator for comparing the sum of the numbers of the sheets counted by the second counting means with a preset number of sheets for determining
  • FIGS. 1A, 1B and 1C when combined together, show a block diagram of one embodiment of this invention
  • FIGS. 1D, 15 and IF show detailed constructions of various circuit elements shown in FIGS. 1A, 1B and 1C;
  • FIGS. 2 and 3 show waveforms for explaining the operation of the apparatus shown in FIGS. 1A, 1B and 1C; 1
  • FIG. 4A shows a block connection diagram of a sheet bundle classification control circuit shown in FIG. 1A;
  • FIGS. 48 and 4C show detailed connection diagrams of the circuit elements employed in the circuit shown in FIG. 4A;
  • FIG. 5 shows a detailed block connection diagram of the coincidence confirmation display means shown in FIG. 18;
  • FIG. 6A shows a detailed block connection diagram of the fraction processing member shown in FIG. 1A;
  • FIGS. 68, 6C and 6D show block diagrams of circuit element employed in the fraction processing member shown in FIG. 6A.
  • FIG. 6E shows a truth table for explaining the operation of the full adder sustractor shown in FIG. 6D.
  • FIG. 1A of the accompanying drawing there is provided a magazine or reservoir 1 from which sheets 2 such as post cards are sequentially supplied into conveyor belts 3.
  • a suction chamber 4 is provided in front of reservoir 1 to sequentially attract successive sheets at a predetermined intervel.
  • the attracted sheets are clamped between conveyor belts 3 and conveyed in a direction indicated by an arrow 5.
  • a check circuit 6 for checking characteristic items used to determine the features of the sheets 2 such as the length, width, thickness codes, masks, numerals and pattern printed thereon.
  • the check circuit 6 applies a predetermined classification signal corresponding to the first class to a classification signal conductor 7a, whereas applies a classification signal corresponding to the second class to a classification signal conductor 90 when the sheets belonging to the second class are classified into a second class receiver. Further, when the sheets belonging to the third class are classified into a third class receiver 11 the check circuit 6 applies a corresponding classification signal to a classification signal conductor 11a.
  • a first detector 14 including an electric lamp l2 and a photoelectric covering element l3on the side of the conveyor belts 3 opposite the lamp 12 is located on the downstream side of the check circuit 6.
  • First detector 14 produces a negative detection signal which becomes zero when the light from lamp 12 is intercepted by the sheet.
  • the detection signal is applied to a differential NOT circuit 16 through an amplifier 15.
  • Behind the first detector 14 is provided a tiltable first gate 17.
  • When the gate 17 is positioned in the solid line position the sheets are conveyed straight forwardly whereas when the gate is positioned in the dotted line position, the sheets are conveyed in the direction of arrow 20 by the action of a first branching belt 19 thus correcting the sheets of the glass in the receiver 7.
  • a second detector 23 comprising an electric lamp 21 and a photoelectric converting element 22 for detecting the sheets of the first class deflected towards receiver 7.
  • the signal generated by the second detector 23 is applied to counter via an amplifier 24 to count the number of sheets deflected to receiver 7.
  • Elements 23, 24 and 25 constitute first counting means.
  • a third detector comprising a lamp 26 and a photoelectric converting element 27 for providing a signal to a differential NOT circuit 30 and a NOT circuit 31 through an amplifier 29.
  • a tiltable second gate 32 On the output side of the third detector 28 is located a tiltable second gate 32.
  • this gate When this gate is positioned in the solid line position the sheets are conveyed straight forwardly as shown by arrow 5, whereas in the dotted line position, the sheets of the second class are conveyed in the direction of arrwo 34 towards receiver 9 by the action ofa second branching belt 33.
  • a fourth detector 37 comprising a lamp 35 and a photoelectric converting element 36 is associated with the second branching belt 33 for detecting the sheets of the second class.
  • the signal generated by the forth detectro 37 is applied to a counter 39 via an amplifier 38 for counting the number of sheets deflected to receiver 9.
  • the sheets 2 of the third class that have passed straight forwardly over the second gate 32 are collected in a receiver 11.
  • The' sheets directed to receiver 11 are detected by a fifth detector 42 comprising a lamp 40 and a'photoelectric converting element 41 and the output signal from the fifth detector 42 is supplied to a counter 44 for counting the number of sheets of the third class directed. to receiver 1 l.
  • the classification signal applied to conductor 9a is supplied to a J terminal of the J K flip-flop circuit 50 (hereinafter designated as J KFF) of a gate driving circuit and also to the K terminal of the J KFF via a NOT circuit 51.
  • the classification signal on conductor 7a is supplied to the J terminal of another J KFF 52 of the gate driving circuit and to the K terminal of the same J KFF through a NOT circuit 53.
  • the I terminals ofJ KFFs 50 and 52 are supplied with the output signal from the first detector 14 through the differential NOT circuit 16.
  • Each of the J KFFs is constructed such that when a l signal is applied to T terminal concurrently with the application of a l signal upon J terminal it will produce a l signal on the output terminal 1, whereas when a 1" signal is applied to T terminal concurrently with the application of a 1 signal upon K terminal it will produce a 0 signal on the output terminal 0.
  • the signal appearing at the output terminal 1 ofJ KFF 50 is supplied to a switching circuit 55 through amplifier 54.
  • switching circuit 55 Upon receiving a 1" signal switching circuit 55 operates to supply a current from a DC source 56 to a first gate driving relay 57.
  • the first gate 17 is held in the solid line position by means of a spring, not shown, in the absence of any input to the gate driving circuit. However, when the first gate driving relay 57 is energized gate 17 is tilted to the dotted line position to collect the sheets of the first class in receiver 7. Signals produce at the terminals 1 and 0 ofJ KFF 52 are applied to terminals J and K ofJ KFF 58 while the output signal from the third detector 28 is supplied to the terminal K ofJ KFF 52 via amplifier 29, NOT- circuit 31 and differential NOT circuit 59. The output from the third detector 28 is also applied to the terminal T of J KFF 58 via amplifier 29 and differential NOT circuit 30.
  • check circuit 6 and detector 28 When the sheets of the second group are conveyed, check circuit 6 and detector 28 successively produce output signals and the output produced on output terminal 1 of J KFF 58 in response to these output signals is supplied to a switching circuit 60 via an amplifier 59. Like the switching circuit 55, when supplied with a l signal, switching circuit 60 passes a current from DC source 56 through a relay 6] for dri'ving the second gate 32. Like the first gate 17, the second gate 32 is normally held in the solid line posi tion but is moved to the dotted line position when relay 61 is energized to collect the sheets of the second class in receiver 9. The sheets of the third class are conveyed into receiver 11.
  • Circuit elements described above operate to take out the sheets 2 from the reservoir, or magazine check, classify them into respective receivers and count the number of sheets collected in respective receivers.
  • FIG. 1C shows a block connection diagram of a circuit constructed to check whether the predetermined number of the sheets of one lot coincides or not with the number of sheets actually detectected as they are classified into respective receivers when the classification of the sheets of the lot has been completed, and
  • the circuit operates to cummulatively counts the number of sheets collected in each receiver when the classification of the sheets of the lo is completed.
  • comparators 80, 81 and 82 are supplied to comparators 80, 81 and 82, respectively, shown in FIG. 1C. Outputs from these comparators are supplied to NOT circuits 83, 84 and 85 respectively. Further, the output from comparator is applied to the input terminal a of a two input NAND circuit 86, the output from comparator 81 is applied to the input terminal a of a three input NAND circuit 87 and the output from ocmparator 82 is applied to the input terminal a of a three input NAND circuit 88.
  • the outputs from the two input NAND circuit 86 and three input NAND circuits 87 and 88 are supplied to clock pulse counters 92, 93 and 94, respectively, through NOT circuits 89, 90 and 91 and the outputs from these clock pulse counters are applied to the other inputs of the comparators 80, 81 and 82, respectively.
  • Comparators 80, 81 and 82 operate to respectively compare the contents of counters 25, 39 and 44 with the contents of counters 92, 93 and 94. When these contents coincide with each other, comparators produce 0 outputs whereas in the case of uncoincidence the comparators produce 1 outputs respectively.
  • NOT circuits 83, 84 and 85 are supplied to the input terminals a, b and 0, respectively of a three input NAND circuit 95. Further the output from NOT circuit 83 is supplied to the input terminal b of the three input NAND circuit 87, whereas that from NOT circuit 84 is applied to the input terminal b of the three input NAND circuit 88.
  • the clock pulse from a clock pulse generator 96 is applied to the input terminals c of three input NAND circuits 87 and 88 to the input terminal b of two input NAND circuit 86 through a two input NAND circuit 97 which operates to produce a signal similar to the clock pulse in response to the clock pulse supplied from the clock pulse generator 96 only when a l signal is applied to the input terminal b of two input NAND circuit 97.
  • the three input NAND circuits 87 and 88 produce outputs on their output terminals corresponding to the signals impressed upon their input terminals c only when l signals are applied on their input terminals a and b but produce 1" outputs when 0 signals are applied to their input terminal a or b.
  • the two input NAND circuit 86 and the three input NAND circuits 87 and 88 constitute a clock pulse prohibiting means, and as above described the outputs from these NAND circuits are supplied to NOT circuits 89, 90 and 91 respectively, to the respective input terminals a, b and c of the three input NAND circuit 98 and to the respective input terminals a of two input NAND circuits 99, 100 and 101, respectively.
  • the outputs from respective two input NAND circuits 99, 100 and 101 are applied to addition counters 120, 130 and 140, respectively, which are provided for respective receivers 7, 8 and 9.
  • the output from the three input NAND circuit 98 is applied to the input terminal a of a two input NAND circuit 102.
  • the other input terminal of this NAND circuit is connected to receive an output signal produced on the output terminal 1 of a set-reset type flip-flop circuit 103 (hereinafter designated as S- RFF).
  • S- RFF set-reset type flip-flop circuit 103
  • the S-RFF 103 is normally held in the reset condition to produce a 0 signal on its output terminal 1 and a l signal on its output terminal 0.
  • a stop signal is applied, manually or automatically, on the set terminal S upon completion of the classification of the sheets of one lot, the S-RFF 103 is changed to 'the set condition to produce a 1" signal'on its output terminal 1 and a 0 signal on its output terminal 0.
  • the output from above described two input NAND circuit 102 which receives at its inputs the outputs from S-RFF 103 and three input NAND circuit 98 is applied to a summation counter 104 and the output from this counter is applied to a sum comparator 105.
  • the summation counter 104 counts the'sum of the sheets of respective classes classified into respective receivers 7, 9 and 11,
  • the sum comparator 105 functions to compare the number of sheets of one lot preset therein with the result of the summation counter 104 to determine whether they coincide with each other or not thus producing a coincidence signal only when a coincidence is obtained.
  • the output from the three input NAND circuit is supplied to an input of sum comparator 105 through a NOT circuit 106 and an AND circuit 105A so that the the sum comparator 105 operates to compare when the output from three input NAND circuit 95 is zero, that is when a l signal is applied to sum comparator and a l signal from the output terminal 0 of .l-KFF 107 is applied to the sum comparator via AND circuit 105A.
  • the coincidence output from sum comparator 105 is delayed a definite time by a delay circuit 1 10 consisting of monostable multivibrators 108 and 109 and the delayed signal is then applied to the terminal T ofj-KFF 107.
  • Monostable multivibrators 108 and 109 are normally maintained in this reset conditions to produce 0 signals on their output terminals 1 and l signals on their output terminals 0.
  • the monostable multivibrator 108 is changed to the set condition thereby producing a l signal on its output terminal 1 and a 0 signal on its output terminal 0.
  • the monostable multivibrator 109 is reset by the trailing edge of the signal produced at the output terminal 1 of the preceding monostable multivibrator 108.
  • the output terminal 1 of .l-KFF 107 is connected to its K terminal and the output terminal 0 is connected to its J terminal so that the J-KFF 107 is normally maintained in the reset condition to produce a 0" signal on its output terminal 1 and a 1 signal on its output terminal 0.
  • the .l-KFF 107 is changed to the set condition thereby producing a l signal on its output terminal 1 and a 0 signal on its output terminal 0.
  • the signal appearing at the output terminal 0 of the J-KFF 107 is also supplied to the input terminal b of a two input NAND circuit 111.
  • Input terminal a of this NAND circuit 111 is connected to receive the signal produced at the output terminal 0 of the S-RFF 103 and the output of the NAND circuit 111 is applied to the input terminal b of NAND circuit 97.
  • NAND circuit 97, S-RFF 103, J-KFF 107 and NAND circuit 111 constitute a clock pulse pass control means.
  • the signal produced at the output terminal of J-KFF 107 is applied to respective input terminals b of the NAND circuits and 101 as well as to the input terminal b of the two input NAND circuit 112.
  • the output from NAND circuit 106 is applied to the input terminal a of NANDv circuit 106 while the 0 output signal from this NAND circuit 112 is supplied to the reset terminal K of J-KFF 107 thus resetting the same.
  • the 0 output from NAND circuit 112 is also supplied to summation counter 104 for resetting its content to zero.
  • the 0 output signal from NAND circuit 112 is applied -to various counters 25, 39 and 44, thereby resetting the contents thereof to zero.
  • NAND circuit 112 The output from NAND circuit 112 is applied to the input terminal a of two input NAND circuit 1 13, the other input terminal b thereof being connected to receive the output signal counters 92, 93 and 94 via a NOT circuit 114 thereby resetting to zero the contents of these counters when NOT circuit 114 produces an output signal.
  • the signal appearing at the output terminal 0 of the monostable multivibrator 108 of delay circuit 110 is applied to the reset'terminal R of S-RFF 103 so that when a 0" signal is produced at the output terminal 0' the S-RFF 103 is reset.
  • the sum comparator 105 does not produce a coincidence signal upon completion of the classification operation of the sheets of one lot, it is necessary to classify and count again the lot.
  • circuit elements 110, 112, 113 and 1 l4 constitute a timing means for providing an external zero reset signal.
  • the scircuit elements described above operate to determine whether the predetermined number of the sheets of one lot coincides or not with the sum of the sheets actually classified and collected in respective receivers and when a coincidence is obtained, the above described circuit element cummulatively sum up the number of sheets collected in each receiver each time the classification operation of the sheets of each lot is completed, whereas in the case of uncoincidence, said circuit element reset to zero the contents of respective counters by applying an external zero resetting signal and reset respective flip-flop circuits thus classifying and counting the particular lot which was erroneously counted and classified.
  • the NAND circuit utilized herein functions to provide a 0" output only when all inputs are 1. Further, although the operation of the logic circuits is explained herein in terms of the positive logic it is to be understood that the negative logic can also be used. For the negative logic it is necessary to change NAND to NOR, AND to OR and OR to AND.
  • FIG. 1D is a block connection diagram showing a binary coded decimal counter for one digit or order of magnitude utilized in counters 25, 39 or 44 shown in FIG. 18, clock pulse counters 92 to 94, or the summation counter 104 or addition counters 120, 130 and 140 forrespective receivers, shown in FIG. 1C.
  • Each one digit of this counter is comprised by four bits utilizing a code l-2-4-8, each bit comprising flip-flop circuits 150 151, 152 and 153, respectively.
  • the input pulse is applied to a terminal Cp
  • Each one of the flip-flop circuits ,150 through 153 is constructed to be set by the trailing edge of the pulse impressed upon its terminal Cp to produce an output at terminals Aout to Dout.
  • Flip-flop circuit 153 reverses its conditions when it receives an input at terminal Cp while a 1 input is being applied to input terminal S and a 0 input is applied to input terminal R thus changing the output from O to l
  • the binary coded decimal counter shown in FIG. 1D operates as follows: First, it is assumed that all flip-flop circuits 150 to 153 have been cleared by the application of a reset signal. Upon application of a positive pulse upon input terminal Cp the flip-flop circuit 150 will be set by the trailing edge of the pulse thus producing outputs 0001 representing a decimal l at respective output terminals Aout to Dout.
  • the next pulse resets the flip-flop circuit 150 to produce an output 0."
  • the flip-flop circuit 151 is set by the trailing edge of the second pulse thus producing outputs 0010 representing a decimal 2 at output terminals Aout to Dout.
  • the third input pulse sets the flip-flop circuit 150.
  • flip-flop circuits 150 and 151 are reset by fourth input while the flip-flop circuit 152 is set thus producing outputs 0100 corresponding to a decimal 4.
  • flip-flop circuits 150 to 152 will be reset. Since, at this time, the terminal R of flip-flop circuit 153 receives a 0 and the terminal S receives a l out signal of the flip-flop circuits 151 and 152, the flip-flop circuit 153 will be set producing outputs 1000 (decimal 8).
  • flip-flop circuits 150 and 152 are reset while flipflop circuits 151 and 153 are set thus providing 1010 (decimal 10)
  • the flip-flop circuit 153 will produce a carry signal.
  • the eleventh pulse input issupplied to the input of the flip-flop circuit comprising the first bit of the next digit (one order higher).
  • counting operations are successively performed for producing binary cod ed decimal outputs at respective output terminals Aout to Dout of respective orders of magnitude.
  • FIG. ID To use the counter shown in FIG. ID in counters 25, 25a, 39, 39a, 44 and 440 three counters shown in FIG. ID are used in each case so as to count three digits.
  • the outputs from detectors 23, 37 and 42 to counters 25, 39 and 44 are respectively applied to the terminal Cp shown in FIG. 1D.
  • clock pulse counters 92 to 94 shown in FIG. 1C function to apply the outputs from NOT circuits 89 to 91 to inputtermina1Cp,.
  • the summation counter 104 applies the output from NOT circuit 102 to input terminal Cp while addition counters 120, and are connected to apply the outputs of NOT circuits 99, 100 and 101 upon input terminal Cp FIG.
  • 1E shows a detailed connection diagram of one, for example 80, of comparators 80 to 82 shown in FIG. 1C.
  • one bit of comparator 80 comprises two NOT circuits 161 and 162, two AND circuits 163 and 164 and one NOR circuit 165.
  • Four bits constitute one comparator for one digit. Accordingly, where counter 25 and clock pulse counter 93 are constructed to count a numeral of three digits, for example, it is necessary to provide three such 1 circuits. For the sake of description, however, only one circuit is shown in FIG. 1E.
  • FIG. 1F shows a detailed connection digram of the sum comparator 105 shown in FIG. 1C.
  • This circuit is substantially identical to that shown in FIG. 1B so that corresponding elements are designated by the same reference numerals.
  • the inputs to be compared for respective bits are applied from summation counter 104 shown in FIG. 1C and from a one lot count number setter, not shown, which may be constituted by a counter identical to that shown in FIG. 1D.
  • an AND CIRCUIT 168 has five input terminals and to the fifth input terminals thereof are applied the outputs from NOT circuit 106 and J-KFF 107 via an AND circuit 170.
  • the output from AND circuit 168 is applied directly to delay circuit 110 shown in FIG. 1C without being inverted.
  • the AND circuit 170 is provided for each digit in order to simultaneously discriminate three digit binary coded decimal signals.
  • AND circuit 168 provides a coincidence signal for delay circuit 110 under the control of the output from AND circuit 170.
  • the embodiment described above operates as follows:
  • the sheets 2 are successively derived out of the magazine 1 by the operation of suction chamber 4 and are then conveyed in the direction of arrow 5 at a definite spacing by means of conveyor belts 3.
  • Each sheet is then checked of its configuration, width, length and thickness, etc., by means of check circuit to determine that the sheet should be collected in a particular one of the receivers.
  • a 1 signal having a predetermined width as shown in FIG. 2A is applied to classification signal conductor 70 so as to apply a l signal upon the terminal J of J-KFF 50 and a 0" signal upon the K terminal of the same J-KFF as shown in FIG S. 2B and 2C.
  • the J-KFF 50 will produce a 1" signal g at its output terminal 1 which is supplied to siwtching circuit 55 via amplifier 54. Responsive to this 1 signal, the switching circuit 55 is switches (shown by FIG. 2H) to supply current to gate driving relay 57 from DC source 56. Consequently, the first gate 17 is moved to the dotted line position to deflect the sheet in the direction of arrow 20 thus collecting the sheet in receiver 7.
  • the sheets classified into receiver 7 aredetected by the second detector 23 and the number of the detected sheets is counted by the counter 25.
  • the sheets subsequently classified into the receiver 7 are collected in the receiver and counted in the same manner.
  • Collection in receiver 9 is made as follows.
  • the sheets of the second class conveyed by the converyor belts are checked by detector 6 which applies a 1" signal 1' on classification signal conductor 90, a 1" signal 1 (FIG. 2]) to the terminal J of J-KFF 52.
  • this detect circuit 14 produces a detection signal (FIG. 2L).
  • the trailing edge of the detection signal is differentiated by means of differential NOT circuit 16 to form a signal m which is applied to the terminal J of J-KFF 52, as shown by FIG. 2N. Since the 1 signal (FIG. 2J) has been applied to the terminal J of the J-KFF 52, this J-KFF produces a 1 signal (FIG.
  • the detection signal A from the first detector 14 is also applied to the terminal J of JKFF 50 via differential NOT circuit 16 (see FIGS. 2M and 26), the J-KFF so provides a signal to its output terminal 0 and a 0 signal to the output terminal 1.
  • the first gate 17 is maintained in the solid line position thus advancing straight forwardly the sheets towards the third detector 28 in the direction of arrow 5.
  • the third detector 28 produces a detection signal r as the sheet passes therethrough. This detection signal r is converted into a signal s by the action of the differential NOT circuit 30, which is supplied to terminal J of JKFF 58, as shown in FIG.
  • the J-KFF 58 Since a l signal has been applied to terminal J, the J-KFF 58 produces a l signal (FIG. 2U) at its output terminal 1 which is applied to switching circuit 60 via amplifier 59. Thus, the switching circuit 60 is switched by the l signal to energize gate driving relay 61 from DC source 56, thus moving the second gate 32 to the dotted line position to carry the sheets of the second class toward receiver 9.
  • the sheets collected in the receiver 9 are detected by the fourth detector 37 and the number of the sheets is counted by counter 39.
  • the first and second gates 17 and 32 are held in their solid line positions so that the sheets are conveyed straight forwardly into receiver 11. More particularly, at this time too, detector 6 produces a 1 signal, but this signal is applied to only a counter 44a to be described later. Consequently, a 1" signal is supplied to the terminals K of J-KFF 50 and J-KFF 52 whereas a 0 signal is applied to the J terminals thereof. The signal from the first detector 14 is applied to terminals J of J-KFFs 50 and 52 to produce a l signal at the output terminal 0 of J-KFF 50.
  • this output signal 1 is not supplied to switching circuit 55 so that the gate 17 will be held in the solid line position whereby the' sheets are advanced straight forwardly.
  • the 1 signal appearing at the output terminal 0 of J-KFF 52 is coupled to the terminal K of J-KFF58. Since the detection signal from the third detector 28 is applied to terminal J of J-KFF 58, this J-KFF provides a l signal at its output terminal 0 but this 1" signal is not supplied to switching circuit 60. Consequently, the second gate 32 too is held in the dotted line position thus allowing the sheets of the third class to advance straight forwardly into receiver 11.
  • the sheets collected in this receiver are detected by the second detector 42 and the number of these sheets is counted by the counter 44.
  • the contents X X and X of counters 25, 39 and 44, respectively, are supplied to comparators 80, 81 and 82, respectively, shown in FIG. 1C.
  • stop signal 200 shown in FIG. 3 is applied, by a manual or an automatic operation, to the set terminal S of S-RFF 103 to produce'a signal 202 (see FIG. 3) at its output terminal 0.
  • the J-KFF 107 is in the reset condition and an 1 signal 204 is being provided at its output terminal 0.
  • NAND circuit 111 produces a 1" signal 205 which is supplied to NAND circuit 97. Since this NAND circuit 97 is supplied with the clock pulse 203 generated by clock pulse generator 96, it generates an output signal 206. Since at this time, comparator 80 produces a l signal 207, the NAND circuit 86 also produces an output identical to output 206.
  • This signal is inverted by the NOT circuit 89 and is then counted bythe clock pulse counter 92, as shown by a curve 209-in FIG. 3.
  • the output from NAND circuit 86 is applied to the input terminal c of NAND circuit 98 and to the input terminal of NAND circuit 101. Since the output from NAND circuit 87 and the output from NAND circuit 88 which are applied to two input terminals of NAND circuit 98 are both the' NAND circuit 98 will produce an output corresponding to the signal supplied to its input terminal 0.
  • the NAND circuit 102 Since the l signal 201 appearing at the output terminal 1 of S-RFF 103 is applied to the input terminal b of the NAND circuit 102 which follows NAND circuit 98, upon application of the output from NAND circuit 98 on its input terminal a, the NAND circuit 102 produces an output signal corresponding to the signal applied to its input terminal a and this output signal is counted by the summation counter 104, as shown by 208 in FIG. 3. Thus, concurrently with the commencement of the counting operation of the clock pulse counter 92, the summation counter 104 also starts to count. Although a signal is applied to NAND circuit 101, it will not produce any output signal since .l-LFF 107 produces a 0 output signal at its output terminal 1.
  • comparator 80 When the content of the clock pulse counter 92 coincides with the content of the counter 25, comparator 80 will produce a 0 output signal 210. Accordingly, the NAND circuit 86 will produce 1 signals at its all output terminals even when a clock pulse 206 is supplied to its input terminal b and these 1" output signals are inverted into 0 signals by the operation of NOT circuit 89 so that clock pulse counter 92 becomes inoperative, as shown by a curve 211 of FIG. 3. Further, the 0 output signal 210 from comparator 80 is inverted into a l signal by the operation of NOT circuit 83 and is then supplied to the input terminal a ofNAND circuit 95 and also to the input terminal b of NAND circuit 87.
  • the NAND circuit 87 Since the 1" output signal 212 from comparator 81 is supplied to the input terminal a of NAND circuit 37, upon application of the outputsignal 206 from NAND circuit 97 upon the remaining input terminal, the NAND circuit 87 will produce an output signal identical to signal 206, which is inverted by NOT circuit 90 and is counted by the clock pulse counter as shown by a curve 213 in FIG. 3. Also the output from NAND circuit 87 is supplied to NAND circuits 98 and 100. Since the output from NAND circuit 86 and the output from NAND circuit 88 which are supplied to two input terminals a and c of the NAND circuit 98 are both 1 signals, the NAND circuit 98 will produce an output corresponding to the output of NAND circuit 87.
  • the NAND circuit 102 in the next stage will produce a similar signal which is counted by summation counter 104 as shown by curve 215 in FIG. 3.
  • the summation counter 104 concurrently with the commencement of the counting operation of the clock pulse counter 93, the summation counter 104 also starts the counting operation.
  • a signal is also supplied to NAND circuit 100 since a 0 output is produced at the output terminal 1 of .l-KFF 107, l signals are produced thereby producing no output signal.
  • the comparator 81 produces a 0 output signal 216.
  • the NAND circuit 87 will produce l signals at its all output terminals and these 1 signals are inverted into l signals by the operation of NOT circuit 90 thereby stopping the counting operation of the clock pulse counter 93, as shown by' curve 217.
  • the "0" output signal from comparator 81 is inverted into a l signal by the operation of NOT circuit 84 and the inverted signal is applied to the input terminal b of NAND circuit 95 as well as to the input signal b of NAND circuit 88.
  • NAND circuit 88 Since the l output signal 218 from comparator 82 is applied to the input terminal a of NAND circuit 88, upon application of the output signal 206 from NAND circuit 97 on the input terminal 0, NAND circuit 88 will produce an output identical to the output signal 206 which is inverted by NOT circuit 91 and is counted by the clock pulse counter 94, as shown by curve 219. Further, the output from NAND circuit 88 is supplied to the input terminal a of NAND circuit 98 and the input terminal a of NAND circuit 99.
  • NAND circuit 98 Since two input terminals b and cof NAND circuit 98 receive l outputs from NAND circuits 86 and 87, in response to the output from NAND circuit 88, the NAND circuit 98 will produce a similar signal which is used to produce a similar signal from the succeeding NAND circuit 102.
  • the signal produced by NAND circuit 102 is counted by the summation counter 104, as shown by curve 220. More particularly, in the same manner as above described, concurrently with the commencement of the counting operation of the clock pulse counter 94, the summation counter 104 also starts the counting operation.
  • a signal is also supplied to NAND circuit 99, since the output from the output terminal 1 of J-KFF is a 0 signal, only 1 signals are produced thus producing no pulse signal.
  • the summation counter 104 counts the total sum of the numbers of sheets classified into respective receivers 7, 9 and 11 and the content of the summation circuit is applied to sum comparator 105.
  • 1 signals are applied to all input terminals a, b and c of NAND circuit 95 so that this NAND circuit will produce a 0 output signal which is inverted into 1 signal 292 by the action of NOT circuit 106 to be applied to the sum comparator 105.
  • the sum comparator 105 receives the 1 signal from the output terminal of J-KFF 107, the sum comparator 105 operates to determine whether the content of summation counter 104 coincides or not with the predetermined number of the sheets of one lot.
  • respective comparator 80, 81 and 82 Upon resetting to zero, respective comparator 80, 81 and 82 will produce again 1 signals as shown by curves 250, 251 and 252, respectively, and these l signals are inverted into 0" signals by the action of respective NOT circuit 83, 84 and 85 to be supplied to the NAND circuit 95.
  • the S-RFF 103 When reset, the S-RFF 103 produces a 1 signal at its output terminal 0 so that NAND circuit 111 will produce a 0 signal 253 to maintain a 0 signal at the output terminal of NAND circuit 97, as shown by curve 253.
  • the monostable multivibrator 109 in the next stage is set by the trailing edge 237 of the signal 236 generated at the output terminal 1 of the monostable multivibrator 108 and the leading edge 239 of the output signal from the monostable multivibrator 109 is applied to the terminal J of J-KFF 107 thus causing it to produce a l signal 240 at its output terminal 1 and a 0 signal at its output terminal 0. Consequently, NAND circuit 111 will produce again a l signal 242 since its inputs a and b are supplied with signals 1" and 0 respectively, so that NAND circuit 97 will produce a signal 245 at its output terminal corresponding to the clock pulse 203.
  • Signal 245 is counted (as shown by 246), again by the clock pulse counter 92 through NAND circuit 86 and NOT circuit 89 as above described and also by summation circuit 104 as shown by curve 280.
  • the output from NAND circuit 86 is also supplied to the input terminal a of NAND circuit 101. Since the input terminals b of these NAND circuits 101, 100 and 99 are supplied with the 1 signal 240 appearing at the output terminal 1 of .l-KFF 107, the summation circuit 104 also begins to count as shown by curve 290.
  • the comparator 80 applies a 0 signal 255 to the input terminal a of NAND circuit 86 thus causing it to produce a 1 signal at its output terminal so that the counting operations of the clock pulse counter 92 and the addition counter 140 are terminated, as shown by curves 281 and 282.
  • the 0 output signal 255 from comparator 80 is inverted into a l signal by NOT circuit 83 which is then supplied to the input terminal a of NAND circuit 95 and to the input terminal b of NAND circuit 87. Consequently, this NAND circuit 87 produces an output corresponding to signal 245 so that clock pulse counter 93 and summation counter 104 resume their counting operations as shown by curves 283 and 284. At this time, since the output from NAND circuit 87 is also supplied to the input terminal a of addition counter 130, this counter commences its counting operation as shown by curve 285.
  • the comparator 81 will provide a 0 signal 261 to the input terminal a of NAND circuit 87 to cause it to generate a 1 signal its output terminal thus terminating the counting operations of the clock pulse counter 93 and addition counter 130 as shown by curves 259 and 260.
  • the 0 output signal 261 from comparator 81 is converted into a l signal for application to the input terminal b of NAND circuit 95 as well as to the input terminal b of NAND circuit 88.
  • the NAND circuit 88 When supplied with a l signal to the input terminal b, the NAND circuit 88 produces an output corresponding to signal 245 thereby causing the clock pulse counter 94 and the summation counter to resume their counting operations, as shown by curves 262 and 263.
  • the output from the NAND circuit 89 is also supplied to addition counter 120 thus causing it to commence the counting operation as shown by curve 264.
  • the comparator when the contents of clock pulse counter 94 and counter 44 coincide with each other the comparator will apply a 0 signal 291 upon the input terminal a of NAND circuit 88 thereby terminating the counting operations of the clock pulse counter 94 and addition counter as shown by corves 265 and 266.
  • addition counters 120 and will store the same number of counts as those of counters 25, 39 and 44 respectively.
  • this NAND circuit Since 1" signals are reapplied upon the input terminals a, b and c of NAND circuit 95, this NAND circuit produces a 0" signal at its output terminal which is inverted into a 1 signal 267 by NOT circuit 106 and is then applied to the input terminal a of NAND circuit 112 and to the sum comparator 105. Since J-KFF produces a 0 signal 241 at its output terminal 0, the sum comparator 105 does not operate to produce a coincidence signal. However, as the 1 signal 240 appearing at the output terminal 1 of J-KFF 107 is applied to the input terminal b of NAND circuit 112, this NAND circuit produces a 0 output signal which is utilized to reset to zero the contents of summation counter 104 and respective counters 25, 39 and 44.
  • NAND circuit 112 resets J-KFF 107 to cause it to generate a l signal 270 at its output terminal 0 and a 0 output signal 271 at its output terminal 1. Consequently NAND circuit 111 produces again a 0 output signal 293. Further, the 0 output signal from NAND circuit 112 is impressed upon the input terminal a of NAND circuit 113. Since the l signal 272 appearing at the output terminal 0 of the monostable multivibrator 108 is impressed upon the input terminal b of NAND circuit 113, this NAND circuit produces a 1 output signal which is inverted into a 0 signal by the action of NOT circuit 114 for resetting to zero the contents of clock pulse counters 92, 93 and 94.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Mechanical Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Sorting Of Articles (AREA)
  • Controlling Sheets Or Webs (AREA)
  • Sheets, Magazines, And Separation Thereof (AREA)
  • Discharge Of Articles From Conveyors (AREA)
  • Conveying Record Carriers (AREA)
US00196895A 1970-11-11 1971-11-09 Apparatus for classifying and counting sheets Expired - Lifetime US3710936A (en)

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JP (1) JPS4926737B1 (xx)
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Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3800253A (en) * 1972-09-01 1974-03-26 Nasa Digital controller for a baum folding machine
US3932272A (en) * 1974-04-02 1976-01-13 Pitney-Bowes, Inc. Scan system
US3936802A (en) * 1972-09-05 1976-02-03 Societe Industrielle Honeywell Bull Control device for recording elements
US3983367A (en) * 1974-02-14 1976-09-28 Glory Kogyo Kabushiki Kaisha Sheet counting machine
US4017830A (en) * 1971-09-09 1977-04-12 Glory Kogyo Kabushiki Kaisha Sheet comparing system and comparator adapted for said system
US4025420A (en) * 1973-09-28 1977-05-24 Tokyo Shibaura Electric Co., Ltd. Thin-sheet-sorting apparatus
US4058815A (en) * 1974-01-25 1977-11-15 Rank Xerox Ltd. Metering system for a copier/duplicator machine
US4166030A (en) * 1975-08-06 1979-08-28 De La Rue Crosfield Limited Apparatus for handling sheets of paper
JPS556677A (en) * 1978-06-30 1980-01-18 Fujitsu Ltd Bill take in device
US4302198A (en) * 1977-01-26 1981-11-24 Kabushiki Kaisha Tokyo Kikai Seisakusho Odd copies bundling system in connection with fixed copies auto-bundling process
US4334619A (en) * 1978-11-30 1982-06-15 Tokyo Shibaura Denki Kabushiki Kaisha Apparatus for processing paper sheets
US4418417A (en) * 1980-04-08 1983-11-29 Laurel Bank Machine Co., Ltd. Reception control system for paper counting machine
US4437571A (en) 1980-10-13 1984-03-20 Tokyo Shibaura Denki Kabushiki Kaisha Thin sheet sorting apparatus
US4458816A (en) * 1978-10-30 1984-07-10 Tokyo Shibaura Denki Kabushiki Kaisha Thin sheet sorting apparatus
US4620634A (en) * 1982-05-25 1986-11-04 Computer Services Corporation Sorting device
US4792392A (en) * 1985-08-13 1988-12-20 Ben Johnson & Company Limited Dump gate control system
EP1331612A2 (en) * 2002-01-22 2003-07-30 Kabushiki Kaisha Toshiba Sheet processing apparatus
CN100567085C (zh) * 2006-01-10 2009-12-09 株式会社东芝 纸片处理设备
US20100282846A1 (en) * 2007-12-28 2010-11-11 Hyung-Hee Won Multi-pocket paper money calculating apparatus having an paper money discriminating function and an auto binding function and an operation control method thereof

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5547426B2 (xx) * 1972-11-04 1980-11-29
JPS5762456A (en) * 1981-08-03 1982-04-15 Laurel Bank Mach Co Ltd Currency dispenser
US4722444A (en) * 1985-04-08 1988-02-02 Banctec Inc. Method and apparatus for document processors
JPH01236169A (ja) * 1988-03-14 1989-09-21 Mita Ind Co Ltd ソータ

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3180122A (en) * 1962-02-06 1965-04-27 United States Steel Corp Sheet classifier

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3467371A (en) * 1966-08-25 1969-09-16 Xerox Corp Sheet distributor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3180122A (en) * 1962-02-06 1965-04-27 United States Steel Corp Sheet classifier

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4017830A (en) * 1971-09-09 1977-04-12 Glory Kogyo Kabushiki Kaisha Sheet comparing system and comparator adapted for said system
US3800253A (en) * 1972-09-01 1974-03-26 Nasa Digital controller for a baum folding machine
US3936802A (en) * 1972-09-05 1976-02-03 Societe Industrielle Honeywell Bull Control device for recording elements
US4025420A (en) * 1973-09-28 1977-05-24 Tokyo Shibaura Electric Co., Ltd. Thin-sheet-sorting apparatus
US4058815A (en) * 1974-01-25 1977-11-15 Rank Xerox Ltd. Metering system for a copier/duplicator machine
US3983367A (en) * 1974-02-14 1976-09-28 Glory Kogyo Kabushiki Kaisha Sheet counting machine
US3932272A (en) * 1974-04-02 1976-01-13 Pitney-Bowes, Inc. Scan system
US4166030A (en) * 1975-08-06 1979-08-28 De La Rue Crosfield Limited Apparatus for handling sheets of paper
US4302198A (en) * 1977-01-26 1981-11-24 Kabushiki Kaisha Tokyo Kikai Seisakusho Odd copies bundling system in connection with fixed copies auto-bundling process
JPS556677A (en) * 1978-06-30 1980-01-18 Fujitsu Ltd Bill take in device
US4458816A (en) * 1978-10-30 1984-07-10 Tokyo Shibaura Denki Kabushiki Kaisha Thin sheet sorting apparatus
US4334619A (en) * 1978-11-30 1982-06-15 Tokyo Shibaura Denki Kabushiki Kaisha Apparatus for processing paper sheets
US4418417A (en) * 1980-04-08 1983-11-29 Laurel Bank Machine Co., Ltd. Reception control system for paper counting machine
US4437571A (en) 1980-10-13 1984-03-20 Tokyo Shibaura Denki Kabushiki Kaisha Thin sheet sorting apparatus
US4620634A (en) * 1982-05-25 1986-11-04 Computer Services Corporation Sorting device
US4792392A (en) * 1985-08-13 1988-12-20 Ben Johnson & Company Limited Dump gate control system
EP1331612A2 (en) * 2002-01-22 2003-07-30 Kabushiki Kaisha Toshiba Sheet processing apparatus
EP1331612A3 (en) * 2002-01-22 2004-11-03 Kabushiki Kaisha Toshiba Sheet processing apparatus
US6892872B2 (en) 2002-01-22 2005-05-17 Kabushiki Kaisha Toshiba Sheet processing apparatus
CN100567085C (zh) * 2006-01-10 2009-12-09 株式会社东芝 纸片处理设备
US20100282846A1 (en) * 2007-12-28 2010-11-11 Hyung-Hee Won Multi-pocket paper money calculating apparatus having an paper money discriminating function and an auto binding function and an operation control method thereof
CN101960494B (zh) * 2007-12-28 2013-06-19 朴賛福 具有纸币识别功能和自动捆绑功能的多袋式纸币计数设备及其操作控制方法

Also Published As

Publication number Publication date
JPS4926737B1 (xx) 1974-07-11
DE2156085A1 (de) 1972-05-18
DE2156085C2 (de) 1984-02-16
GB1312180A (en) 1973-04-04

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