US3665496A - Electrical signal sampling device - Google Patents

Electrical signal sampling device Download PDF

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Publication number
US3665496A
US3665496A US39690A US3665496DA US3665496A US 3665496 A US3665496 A US 3665496A US 39690 A US39690 A US 39690A US 3665496D A US3665496D A US 3665496DA US 3665496 A US3665496 A US 3665496A
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Prior art keywords
priming
gate
output
gates
input
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Expired - Lifetime
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US39690A
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English (en)
Inventor
Jacques Donjon
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Societe de Fabrication dInstruments de Mesure SFIM SA
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Societe de Fabrication dInstruments de Mesure SFIM SA
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/04—Distributors combined with modulators or demodulators
    • H04J3/047—Distributors with transistors or integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors

Definitions

  • the present invention relates to an improved sampler.
  • a sampler is a device receiving simultaneously several electric signals at different inputs, taking successively, in a predetermined order, samples" of the value of these electric signals, in order to provide on its single output an output signal carrying these samples in the predetermined order.
  • the present invention provides a sampler of this type comprising for each input, a priming gate making it possible to connect the corresponding input to the output, and a ring counter controlling the successive opening of the priming gate according to a predetermined cycle in such a way that the samples taken on the different inputs appear on the output following this cycle.
  • each priming gate comprises one control input; at least two of the inputs of adjacent priming gates controlling the taking of samples, being able to be connected to each other in a detachable manner in order to introduce synchronization information into the output signal of the device.
  • the priming gates are field effect transistors comprising a control, the control being connected to a source of electrical supply through the intermediary of a diode connected in a direction such that the transistor does not allow any signal to pass in the absence of this supply.
  • FIG. 1 shows diagrammatically the sampler according to the invention.
  • FIG. 2 shows the electric signals appearing at various points of the diagram of FIG. 1.
  • the sampler of FIG. 1 comprises eight inputs 1 to 8 to which there are applied the electric input signals intended to be sampled and an output 9 at which the output signal carrying the samples appears.
  • priming gates 10 to 17 are associated with respective inputs and control the connections between the corresponding inputs and a common line 18 connected to the output 9.
  • the priming gates are field-effect transistors comprising a source S, a drain D and a control electrode P, the source S being connected to an input of the sampler and the drain D to the common line 18.
  • the state of conduction or non-conduction of the transistor is controlled by the application of electric signals on its control electrode P in known manner.
  • these control signals are provided by a ring counter 19 in such a way that the priming gates are each brought into a state of conduction in their turn according to a predetermined order. It can be seen that in the state of conduction, each transistor applies to the common line 18 an electric signal substantially identical to that which is on the corresponding input and for the duration of this condition. There thus appears at the output 9 samples of each of the input signals, each sample being identified within a cycle by its position.
  • the ring counter 19 is constructed for example of J-K flipflops 20 to 27.
  • Each of these trigger circuits comprises two synchronous inclock inputs of the different trigger circuits or bistable circuit.
  • the input K and the output Q of the same bistable circuit are connected to each other such that the bistable circuit returns to its previous condition after being triggered.
  • the output Q of a bistable circuit is connected to the input 1 of the following bistable circuit such that this latter is in turn triggered.
  • FIG. 2 the output signals at respective Q's are shown illustrating successive triggerings.
  • the output 29 of the last bistable 27 is connected by a lead to the input 30 of the first bistable circuit 20.
  • the signal coming from the outputs 6 of the bistable circuits is used to control the conditions of conduction or non conduction of the transistors 10 to 17.
  • the control signals from the bistable circuits are divided by a clock signal H (Identical to the clock signal H in logic gates NOT-OR" 31 to 38, the clock signal H being applied at 39.
  • the signals delivered by the different transistors on the common lead 18 are those shown on FIG. 2. It can be seen that in fact samples at only the inputs 1 to 6 are taken, the input 7 being connected to a predetermined D.C. voltage (for example of +2V) and the control electrodes of the transistors 16 and 17 being connected to each other by a detachable bridging connection or jumper 40.
  • the input 8 may provide the D.C. voltage (for example +2V) in order to serve as a synchronization signal; in addition, the control signal coming from the bistable circuit 26 is not chopped by the clock signal H since one of the inputs of the gate NOT- OR 37 has no connection.
  • the gate pulse appearing at 29, is fed to an external circuit (not shown) including an inverter in order to provide a signal at the input 41 in order to re-set'to zero (RAZ) all the bistable circuits except the last one 27.
  • RAZ re-set'to zero
  • This re-setting to zero takes place by firstly means of the clock signal H, opening a gate 42 to pass the gate pulse from the inverter and then by applying simultaneously to the RAZ inputs of the bistables 20 to 26 the signal thus passed.
  • This re-setting to zero is carried out in order to eliminate cases which could arise where one of the bistable circuits is in the one" condition.
  • a signal for resetting to one is applied to the input 43 which is connected to the RAU input (re-set to one) of the bistable circuit 27 and on the input 41 for resetting the other bistable circuits to zero.
  • the terminals 44 and 45 are respectively connected to the and poles of a source of direct current. There have not been shown, for the sake of clarity of the drawing, the leads from these terminals to the transistors.
  • the terminal 46 is connected to the substrates of the transistors.
  • a diode 47 is connected between the substrates and the positive supply terminal 44 in order to prevent a transistor from allowing a signal, which is applied to it, to pass, when no positive voltage is present on the terminal 44.
  • the device is made so that it may be connected by simple connection to another identical device in order to be able to sample a greater number of input signals.
  • the output 29 of the ring counter 19 is not permanently connected to the input 30; in this manner one can connect the output 29 to the input of another ring counter and make a connection between the output of this other counter and the input 30. Also for this reason, the bridge 40 connecting the grids of the transistors 16 and 17 is removable.
  • a logic AND" gate 50 for controlling the interconnection and operated by the clock signal H puts a similar auxiliary gate in a conducting condition (not shown in FIG. 1), the supply source for which is grounded and the collector connected to the lead 18, the effect of this is to provide a zero signal at terminal 9 during the period of interconnection except during the synchronization period, the gate being made inactive by the signal Q of the bistable circuit 26 arriving at its second output.
  • a sampler comprising:
  • a ring counter having a plurality of stages serially connected in an endless chain, the output of the last stage being connected to the input of the first stage, said stage being equal in number to the number of said inputs, each stage applying control signals to a different one of said priming gates to cause that gate to connect its respective input to said output for a predetermined duration, said stages operating in a predetermined order to apply their control signals and only one of said priming gates receiving a control signal at any one time, whereby samples of the electrical input signals appear one at a time at said output.
  • priming gates are field effect transistors each having a collector electrode, and including a positive D.C. source for said transistors and a diode connected between said collector electrodes and said source, thereby preventing the taking of samples in the absence ofa supply voltage.
  • a sampler including means for providing first and second identical clock signals, and a logic gate between each ring counter stage and its respective priming gate, and wherein each stage of said ring counter includes a trigger circuit responsive to each of said first clock signals for supplying a gate pulse, said gate pulses and said second clock signals being applied to the logic gate associated with that stage for opening its respective priming gate for a duration shorter than the duration of said gate pulse, whereby samples appear at said output at spaced apart intervals.
  • each of said priming gates includes a control electrode, and including a removable connection between the control electrodes of two adjacent priming gates, the logic gate associated with one of said adjacent priming gates being unconnected to said means providing second clock signals, whereby said two adjacent priming gates deliver a synchronization pulse.
  • a sampler according to claim 4 including means for deriving from the gate pulse of the last stage of said ring counter a signal for resetting the other stages to zero.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Tests Of Electronic Circuits (AREA)
US39690A 1969-05-23 1970-05-20 Electrical signal sampling device Expired - Lifetime US3665496A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR6916900A FR2044675A1 (enrdf_load_stackoverflow) 1969-05-23 1969-05-23

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FR (1) FR2044675A1 (enrdf_load_stackoverflow)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4903242A (en) * 1987-05-06 1990-02-20 Nec Corporation Serial access memory circuit with improved serial addressing circuit composed of a shift register
US5016263A (en) * 1988-07-07 1991-05-14 Kabushiki Kaisha Toshiba Sample-hold circuit with outputs taken between gates of dynamic shift register to avoid skew from unequal interstage connection lengths
US5371525A (en) * 1990-11-30 1994-12-06 Kyocera Corporation Image head

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2662175A (en) * 1947-03-05 1953-12-08 Hartford Nat Bank & Trust Co Multiplex transmission device
US3015806A (en) * 1958-03-12 1962-01-02 Wang Laboratories Machine tool control system
US3184663A (en) * 1960-07-25 1965-05-18 Warner Swasey Co Plural pulse responsive motor synchronizing control system with uniform pulse spacing
US3229115A (en) * 1962-02-21 1966-01-11 Rca Corp Networks of logic elements for realizing symmetric switching functions
US3280309A (en) * 1963-06-28 1966-10-18 Electro Optical Systems Inc Logarithmic pulse counter
US3461313A (en) * 1965-12-09 1969-08-12 Teletype Corp Circuit for maintaining selected circuits operated
US3517175A (en) * 1966-08-25 1970-06-23 Plessey Co Ltd Digital signal comparators

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2662175A (en) * 1947-03-05 1953-12-08 Hartford Nat Bank & Trust Co Multiplex transmission device
US3015806A (en) * 1958-03-12 1962-01-02 Wang Laboratories Machine tool control system
US3184663A (en) * 1960-07-25 1965-05-18 Warner Swasey Co Plural pulse responsive motor synchronizing control system with uniform pulse spacing
US3229115A (en) * 1962-02-21 1966-01-11 Rca Corp Networks of logic elements for realizing symmetric switching functions
US3280309A (en) * 1963-06-28 1966-10-18 Electro Optical Systems Inc Logarithmic pulse counter
US3461313A (en) * 1965-12-09 1969-08-12 Teletype Corp Circuit for maintaining selected circuits operated
US3517175A (en) * 1966-08-25 1970-06-23 Plessey Co Ltd Digital signal comparators

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4903242A (en) * 1987-05-06 1990-02-20 Nec Corporation Serial access memory circuit with improved serial addressing circuit composed of a shift register
US5016263A (en) * 1988-07-07 1991-05-14 Kabushiki Kaisha Toshiba Sample-hold circuit with outputs taken between gates of dynamic shift register to avoid skew from unequal interstage connection lengths
US5371525A (en) * 1990-11-30 1994-12-06 Kyocera Corporation Image head

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Publication number Publication date
FR2044675A1 (enrdf_load_stackoverflow) 1971-02-26

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