US3638048A - Store read units - Google Patents

Store read units Download PDF

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Publication number
US3638048A
US3638048A US2825A US3638048DA US3638048A US 3638048 A US3638048 A US 3638048A US 2825 A US2825 A US 2825A US 3638048D A US3638048D A US 3638048DA US 3638048 A US3638048 A US 3638048A
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US
United States
Prior art keywords
transistor
base
emitter
resistor
input terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US2825A
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English (en)
Inventor
Ferdinand Camerik
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
US Philips Corp
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US Philips Corp
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Filing date
Publication date
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Application granted granted Critical
Publication of US3638048A publication Critical patent/US3638048A/en
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G11C11/416—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
    • H03K17/62—Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors
    • H03K17/6242—Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors with several inputs only and without selecting means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/013—Modifications for accelerating switching in bipolar transistor circuits

Definitions

  • ABSTRACT Read unit suitable for reading a storage element whose stored information is available in the form of a voltage at an information terminal, said unit comprising a second transistor controlled by a first transistor, the latter being rendered conducting when the former is cut off for conducting away the charge accumulated in the base of the second transistor.
  • the invention relates to a read unit for scanning the information appearing in the form of a bivalent voltage signal at an information terminal, said unit for being selected by bivalent signals comprising an input terminal which is coupled through a first resistor with the base of a first transistor, one emitter of which is connected to the information terminal and the collector of which isconnected to the base of a second transistor, whose emitter is coupled with a source of constant potential and whose collector is connected on the one hand to an output terminal and on the other hand through a second resistor to a terminal of a supply source.
  • TI-Ie problem of scanning bivalent voltage signals is involved inter alia in semiconductor stores in which the storage elements are formed by bistable semiconductor devices.
  • a read unit of the kind set forth has become known from Electronics,"Apr. 4, 1966, page 122.
  • Vs is the maximum value of the input voltage for which the output voltage does not charge
  • Vt is the maximum voltage variation of the output voltage
  • the invention has for its object to provide under any condition a short switching time of the read unit mentioned above and hence to improve the enlargement of the anti-interence range.
  • the read unit according to the invention is characterized in that the input terminal is connected to a second emitter of the first transistor for temporarily rendering the first transistor conducting when the second transistor is cut off.
  • FIG. 1 shows a known read unit.
  • FIG. 2 shows an embodiment of a read unit in accordance with the invention.
  • FIGS. 3, 4 and 5 show embodiments of the invention, which are extended as compared with the embodiment shown in FIG. 2.
  • the read unit shown in FIG. 1 comprises a storage element G, which contains information in the form of a bivalent voltage signal.
  • the values of these voltages are unambiguously determined and they are either low, then corresponding to ground potential, or high, then corresponding to the positive voltage of the supply source.
  • These signal voltages may be derived from an information terminal of the storage element G.
  • the information terminal is connected to an emitter of the multiemitter transistor T, whose base is connected through a first resistor R, to a first input terminal y and a second emitter of which is connected to a second input terminal x, while the collector thereof is connected to the base of a second transistor T
  • the emitter of the transistor T is connected to ground and the collector is connected on the one hand to the output terminal U and on the other hand through the resistor R to the positive terminal V,, of a supply source (not shown).
  • the input terminals x and y receive bivalent signals, a high value of the signal denoting herein a high volt- -age,,i.e., the positive voltage of the supply source (not shown),
  • the transistor T will be cut off independently of the value of the voltage at the input terminal x, so that no base current is available for the transistor T which is thus also cut oil.
  • the output voltage at the terminal U is then equal to the positive voltage of the supply source (not shown). If the voltage at the input terminal y is high and that at the input terminal x low, the base-emitter junction of the multiemitter transistor T, is conducting. The collector voltage of transistor T, is under these conditions approximately equal to the voltage at the input terminal x so that the base voltage of the transistor T is also low and the transistor T remains cut off.
  • the output voltage of the terminal U remains high.
  • the output voltages may be employed for driving other circuits, it is required for them to have the same levels as the voltages of the element G.
  • this read unit is integrated in a circuit so that low dissipation is required. In order to satisfy these requirement, the transistor T is cut off for obtaining a high output voltage and the transistor T is driven in the saturation state for obtaining a low output voltage.
  • the base of the multiemitter transistor T When the voltage at terminal y is changed from a high to a low value, whereas the voltage at terminal x and at the information terminal is high, the base of the multiemitter transistor T, will be at a high voltage during the time lag C,,R,, whereas the emitter voltage is low so that the multiemitter transistor will operate as a transistor for said time. The base charge of transistor T will then be conducted away with an accelerated rate through the collector-emitter junction of the multiemitter transistor T, and the input terminal y. As a result the switching time is reduced so that the range of interference is smaller. If the time lag C,,R, is too short for a complete drain of the base charge of transistor T the parasitic capacitance C, may be enhanced.
  • the read unit shown in FIG. 3 obviates this disadvantage of I the read unit of FIG. 2.
  • a third transistor T whose base-emitter junction is connected between the resistor R, and the base of the multiemitter transistor T, is arranged so that the base of the transistor T is connected to the resistor R, and the emitter thereof is connected to the base of the multiemitter transistor T,.
  • the collector of the transistor T is connected through the resistor R to the positive terminal V, of the supply source (not shown).
  • the transistor T will be conducting because the base current for the transistor T passes from the positive tenninal of the supply source (not shown), via resistor R the emitter-collector junction of transistor T the basecollector junction of transistor T, and the base-emitter junction of transistor T The transistor T is then driven in the saturation state and a great charge is then accumulated in the base of this transistor. If only the voltage at the input terminal y is changed from a high to a low value, the base of the transistor T will follow this voltage drop with the time lag C,,R,; thus transistor T is cut off, which requires a certain amount of time, after which the base of the multiemitter transistor T, assumes a low voltage.
  • the emitter voltage of the multiemitter transistor T has followed the voltage drop at the input terminal y.
  • the multiemitter transistor T operates as a transistor for the time C R, plus the time required for the transistor T,, to be cut off and the stored charge will be conducted away completely via the base of transistor T and the collector-emitter junction of the multiemitter transistor T, to the input terminal y.
  • the transistor T is definitely cut off as soon as the base charge is conducted away so that a longer time lag than that strictly required is not objectionable.
  • the switching-on time of a conventional transistor is much shorter than the switching-off time, the result of including transistor T in the base circuit of the multiemitter transistor T, is that the base charge of transistor T is completely conducted away without the introduction of an additional time lag when the input voltage at terminal y is changed from a low to a high value.
  • the base-emitter junction of the multiemitter transistor T of these embodiments will be conducting.
  • the collector voltage of the multiemitter transistor T is then substantially equal to the low emitter voltage so that the base of the transistor T, which is connected to the collector of the transistor T,, has a low voltage and the transistor T will be cut off.
  • energy will be dissipated in the read unit, which is advantageous when the unit is integrated. This is obviated by the read unit shown in FIG. 4.
  • the read unit operates in a similar manner as that shown in H6. 3. If only the input voltage of terminal .1: is low, transistor T is cut off and the circuit for the base current of transistor T, is interrupted so that also in this case the multiemitter transistor T, and all other transistors included in the read unit are cut off so that the read unit is better suitable for being integrated.
  • the read unit of HO. 3 has removed from it the resistor R and the collector of transistor T, directly connected to the positive terminal of the supply source and a resistor R connected between the emitter of transistor T,, and the base of the multiemitter transistor T,.
  • the operation of this read unit is equal to that of H6. 3 with the exception that a lower input control current is sufi'rcient since the transistor T; is connected as an emitter follower. This has the advantage that a plurality of these inputs may be connected to one output. It is not essential for the embodiments described, above, with the exception of read unit shown in FIG. 4, for the input terminal at to be provided so that for certain uses this terminal need not be accessible.
  • a read unit for scanning information appearing in the form of a bivalent information signal on an information input terminal in response to bivalent switching signals on a switching signal input terminal comprising a first multiemitter transistor having a base, a collector, and at least two emitters, a first resistor, means for connecting the base of the first transistor to the switching signal input terminal through the first resistor, means for connecting a first emitter of the first transistor to the information input terminal, a second transistor having a base, a collector, and an emitter, conductor means for connecting the collector of the first transistor directly to the base of the second transistor, conductor means for connecting the emitter of the second transistor to a source of constant potential, conductor means for connecting the collector of the second transistor directly to an output terminal, a second resistor, means for connecting the collector of the second transistor to a supply voltage input terminal through the second resistor, and conductor means for connecting the switching signal input terminal directly to a second emitter of the first transistor through a low impedance path whereby the first transistor is driven temporarily into a conductive
  • a read unit as claimed in claim 2 further comprising a second switching signal input terminal, a fourth transistor, conductor means for connecting the second switching signal input terminal directly to a third emitter of the first transistor, a fourth resistor, means comprising the collector and emitter of the fourth transistor for connecting the emitter of the third transistor to the base of the first transistor, and means for connecting the base of the fourth transistor to the second switching signal input terminal through the fourth resistor.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Electronic Switches (AREA)
  • Static Random-Access Memory (AREA)
  • Bipolar Integrated Circuits (AREA)
US2825A 1969-01-16 1970-01-14 Store read units Expired - Lifetime US3638048A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL6900697.A NL162771C (nl) 1969-01-16 1969-01-16 Uitleeseenheid voor geheugens.

Publications (1)

Publication Number Publication Date
US3638048A true US3638048A (en) 1972-01-25

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ID=19805882

Family Applications (1)

Application Number Title Priority Date Filing Date
US2825A Expired - Lifetime US3638048A (en) 1969-01-16 1970-01-14 Store read units

Country Status (6)

Country Link
US (1) US3638048A (de)
JP (1) JPS4911768B1 (de)
DE (1) DE1964791C3 (de)
FR (1) FR2033242B1 (de)
GB (1) GB1257153A (de)
NL (1) NL162771C (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3970866A (en) * 1974-08-13 1976-07-20 Honeywell Inc. Logic gate circuits

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH632886GA3 (en) * 1979-02-21 1982-11-15 Piece of jewellery protected by a shielding of hard metal

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1192250B (de) * 1964-02-21 1965-05-06 Licentia Gmbh Logische Schaltung
US3427598A (en) * 1965-12-09 1969-02-11 Fairchild Camera Instr Co Emitter gated memory cell
US3510685A (en) * 1966-02-16 1970-05-05 Nippon Telegraph & Telephone High speed semiconductor switching circuitry

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3233125A (en) * 1963-01-08 1966-02-01 Trw Semiconductors Inc Transistor technology
US3452216A (en) * 1965-12-13 1969-06-24 Westinghouse Electric Corp Logic circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1192250B (de) * 1964-02-21 1965-05-06 Licentia Gmbh Logische Schaltung
US3427598A (en) * 1965-12-09 1969-02-11 Fairchild Camera Instr Co Emitter gated memory cell
US3510685A (en) * 1966-02-16 1970-05-05 Nippon Telegraph & Telephone High speed semiconductor switching circuitry

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3970866A (en) * 1974-08-13 1976-07-20 Honeywell Inc. Logic gate circuits

Also Published As

Publication number Publication date
DE1964791C3 (de) 1982-02-11
GB1257153A (de) 1971-12-15
DE1964791A1 (de) 1970-07-30
NL162771C (nl) 1980-06-16
NL6900697A (de) 1970-07-20
FR2033242B1 (de) 1975-06-06
FR2033242A1 (de) 1970-12-04
NL162771B (nl) 1980-01-15
JPS4911768B1 (de) 1974-03-19

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