US3573754A - Information transfer system - Google Patents

Information transfer system Download PDF

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US3573754A
US3573754A US650832A US3573754DA US3573754A US 3573754 A US3573754 A US 3573754A US 650832 A US650832 A US 650832A US 3573754D A US3573754D A US 3573754DA US 3573754 A US3573754 A US 3573754A
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storage unit
transistor
collector
binary information
transistors
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Jerry D Merryman
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Texas Instruments Inc
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Texas Instruments Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

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  • binary information from a first storage unit to a second storage unit in successive steps utilizing an intermediate storage unit and gates differently responsive to various conditions of an energizing source.
  • the binary information is transferred from the first 307/238 328/37 storage unit to the intermediate storage unit, gates allowing III- C].
  • the gates are differently 3,177,374 4/1965 Simonian et al. 340/173X responsive to two predetermined conditions of the energizing 3,218,613 1 1/1965 Gribble et a].
  • 340/173 source in order to effect the desired communication and 3,275,846 9/1966 Bailey 340/173X transfer of information between the storage units while these 3,297,950 1] 1967 Lee 328/37 gates are non responsive to the energizing source when it is 3,423,737 l/ 1969 Harper 340/ 173 changing between these predetermined conditions so that the 3,427,598 2/1969 Kubinec 340/173 desired operation of the system is achieved only during two 3,321,639 5/1967 Fowler et al. 307/291X predetermined conditions of the energizing source.
  • the present invention relates to information transfer systems and more particularly to shift registers wherein binary is transferred from one storage unit to another under the control of an energizing source.
  • the storage units are generally permanent bistable memory elements such as flip-flops, PNPN switches, or thyratrons.
  • intermediate storage units are utilized in transferring the binary information from one storage unit to another.
  • One kind of intermediate storage unit is a temporary memory element such as a resistance capacitance network which eliminates active devices as part of the intermediate storage device but requires large capacitors which cause timing difficulties and are not compatible with present day miniaturized monolithic semiconductor circuit techniques.
  • Another kind of intermediate storage unit is a permanent bistable memory element the same as that utilized for the other storage units of the shift register.
  • permanent intermediate storage units heretofore utilized to effect two step or two phase transfer of binary information from one storage unit to another has required complicated electrical circuitry.
  • one object of the present invention is to transfer binary information from one storage unit to another utilizing a simple system and circuitry.
  • Another object is to provide an information transfer system suitable for high or low speed two step transfer of the binary information between the storage units utilizing low power.
  • Still another object is to provide an information transfer system especially suitable for miniaturization utilizing monolithic semiconductor circuit technique and suitable for large scale integration in or on a single semiconductor material.
  • a feature of the present invention is an intermediate storage unit and gates differently responsive to various conditions of an energizing source for efiecting two step transfer of binary information from one storage unit to another.
  • FIG. 1 is an embodiment of the present invention
  • FIG. 2 is another embodiment of the present invention.
  • FIG. 3 is still another embodiment of the present invention.
  • FIG. 4 illustrates the top view of a monolithic integrated semiconductor circuit embodying the storage units FFl, FF2, gate 34 and resistors 11-14 of the embodiment illustrated in FIG. 2;
  • FIG. 5 illustrates a cross section of the FIG. 4 embodiment taken along the lines A-A.
  • FIG. 6 illustrates the top view of a monolithic integrated semiconductor circuit embodying the storage units FF], FF2, gates 28-29, 30-31, and resistors ll-l4 of the embodiment illustrated in FIG. 3;
  • FIG. 7 illustrates a cross section of the FIG. 6 embodiment taken along the lines B-B.
  • binary information contained in the storage unit FF! is to be transferred to the storage unit F F3 by way of the intermediate storage units FF2.
  • the storage units FFl, FF2 and FF3 are identical bistable flip-flops each comprising two transistors. Each transistor of a storage unit has its collector directly connected to the base of the other.
  • the emitters of transistors 1, 2, 5 and 6 are connected to ground and the emitters of transistors 3 and 4 are connected to the energizing source of clock pulse 17.
  • the collector bias voltage +v is connected to the collectors of transistors 1-6 by way of the resistors 11-16.
  • Gate 34 comprises diodes 7 and 8.
  • the diode 7 has its cathode connected to the collector of transistor 1 and its anode connected to the collector of transistor 3 while diode 8 has its cathode connected to the collector of transistor 2 and its anode connected to the collector of transistor 4.
  • Gate 35 comprises diodes 9 and 10.
  • Diode 9 has its cathode connected to the collector of transistor 3 and its anode connected to the collector of transistor 5 while diode 10 has its cathode connected to the collector of transistor 4 and its anode connected to the collector of transistor 6.
  • FIG. 1 represents one and one-half bits of a shift register. That is to say, one bit comprises storage unit FFl and intermediate storage unit FF2. Storage unit FF3 and another intermediate storage units would be a second bit of the shift register.
  • the information transfer system of FIG. 1 operates as follows:
  • the 1 state of a storage unit shall be defined as the collector voltage of the right-hand transistor being higher than the collector voltage of the lefthand transistor of a storage unit.
  • transistor 1 is on and transistor 2 is off.
  • transistor 1 is off and transistor 2 is on.
  • the collector voltage of transistor 3 is higher than the collector voltage of transistor 4 and the collector voltage of transistor 3 is suffi cient to forward bias diode 7 and turn it on while the collector voltage of transistor 4 is insufficient to forward bias the diode 8.
  • diode 7 drives the collector voltage of transistor 3 lower which in turn lowers the voltage on the base of transistor 4.
  • Transistor 4 begins to conduct less heavily, increasing the positive voltage on the base of transistor 3 whereby transistor 3 turns on and transistor 4 turns off.
  • Diode 8 remains off since the collector voltage of transistor 4, even when on, is insufficient to forward bias the diode 8. However, when transistor 3 is on, its collector voltage is still sufficient to maintain diode 7 forward biased. In this manner, intermediate storage unit F F2 is driven into the 1 state corresponding to the 1 state of storage unit FFl.
  • gate 35 blocks communication between the intermediate storage unit FF2 or storage unit FF] and the storage unit F F3 while gate 34 allows communication between the storage unit PH and the intermediate storage FF2 to cause the state of intermediate storage unit FF2 to be driven into correspondence with that of storage unit of F Fl.
  • the action of gate 34 in response to the voltage levels caused by the +1 condition of the clock pulse 17 allows the storage unit FFl to communicate with the intermediate storage unit FF2 and maintain the state of the intermediate storage unit FF2 in correspondence with the state of the storage unit F F1 while the gate 35 blocks communication between the intermediate storage unit F F2 or the storage unit FF] and the storage unit FF3.
  • the storage unit FFl is in the 1 state
  • the intermediate storage unit F F2 is in the 1 state
  • the clock pulse is at 1 volts.
  • the collector voltages of transistors 3 and 4 decrease and becomes negative, the collector voltage of transistor 3 more negative than the collector voltage of transistor 4.
  • Both diodes 7 and 8 are reverse biased thereby preventing any communication between storage unit FFI and intermediate storage unit F F2.
  • storage unit FF3 may be in the l or state and it will be driven or maintained in the 1 state.
  • the collector voltage of transistor 5 is sufiicient to forward bias the diode 9 since the cathode of diode 9 is sufficiently more negative than the cathode of diode l0.
  • diode 9 turns on since the collector voltage of transistor 5 is sufficiently positive with respect to the cathode of diode 9 to forward bias diode 9 thereby decreasing the collector voltage of transistor 5, decreasing the base voltage of transistor 6, and causing transistor 6 to conduct less heavily. Consequently, the collector voltage of transistor 6 increases and causes the base voltage of transistor 5 to increase. Transistor 5 now turns on and transistor 6 turns off placing storage unit FF3 in the 1 state. Diode 10 remains off since the negative voltage at its cathode is insufficiently negative with regard to the voltage swing at the collector of transistor 6 to reverse bias diode 10. In this manner, gate 35 allows intermediate storage unit FF2 to communicate with storage unit FF3 and drive the state of storage unit FF3 into correspondence with the state of the intermediate storage unit FF2.
  • the gates 34 and 35 respond differently to the two predetermined conditions of the energizing source 17 to allow and prevent communication between the desired storage units.
  • gate 34 continues to allow communication between the storage units FF 1 and FF2 only until the clock pulse reaches a certain lower voltage level (about +0.7 volts) at which time the gate 34 ceases to allow communication, and at an even lower voltage level (about 0.2 volts) the gate 35 responds if necessary i.e.
  • the gate 35 responds at about 0.7 volts and maintains the already existing 1 state of the storage unit FF3.
  • the gate 34 responds at about +0.7 volts and maintains the already existing 1 state of the intermediate storage unit F F2.
  • the gate 35 is in a blocking condition and isolates the storage unit FF3 from the preceeding storage unit and the gate 34 drives or maintains the state of the intermediate storage unit F F2 in correspondence with the state of the storage unit FF 1.
  • both gates 34 and 35 are nonresponsive that is, there is no communication between the storage units, until certain levels of the energizing source are reached at which time the gates 34 and 35 become responsive to the second condition of the energizing source and the gate 34 blocks and isolates storage unit FF 1 from the succeeding storage unit while gate 35 drives or maintains the state of storage unit F F3 in correspondence with the state of the intermediate storage unit F F2.
  • the energizing source may take the form of a clock pulse as illustrated in the drawings or may be any wave shape that rises and falls above and below a predetermined voltage range which in the case described is about 010.2 volts. During this predetermined range or third condition, the gates 34 and 35 are nonresponsive to the energizing source. If the storage unit PH and the storage unit FF2 are in the same state, this conformity of the states is maintained at about +0.7 volts. However, if the storage unit FFl and the intermediate storage unit FF2 are in different states, the intermediate storage unit FF2 is driven into the opposite state at about +0.2 volts.
  • the information transfer system of the present invention thereby senses and responds to two conditions of the energizing source to effect the two step transfer of binary information from one storage unit to another while being essentially insensitive or non responsive to the third condition of the energizing source when it is changing between the first and second predetermined conditions.
  • FIG. 2 in similar to that of FIG. 1 and operates in the same manner.
  • gates 34 and 35 of FIG. 2 comprise transistors each having its collector and base electrodes electrically shorted together.
  • This construction is especially suitable for incorporation into a miniaturized monolithic semiconductor circuit since all the transistors 1-6 and 1821 are identical and can be fabricated and processed at the same time and in like manner in a single semiconductor material.
  • the embodiment and circuit figuration of FIG. 2 are especially suitable for lower speed applications where high H, is desired and incorporation into a monolithic integrated semiconductor circuit utilizing triple diffused processing techniques as will more fully be described later in connection with FIGS. 4 and 5.
  • FIG. 3 is similar to the embodiment of FIGS. 1 and 2 except that multi emitter transistors 22-27 are employed in place of the transistors l-6 and gates 34 and 35 of FIGS. 1 and 2.
  • the embodiment of FIG. 3 operates in the same manner as the embodiments of FIGS. 1 and 2 except that the intermediate storage unit of FIG. 3 has a state which is inverted with respect to the state of the storage unit F Fl. For example, assume that the storage unit FFl is in the 1 state and the clock pulse 17 is at the -l volt condition.
  • the emitter 31 is more positive than the emitter 30.
  • intermediate storage unit FF2 is in the 1 state (transistor 24 on, transistor 25 off) the collector voltage of transistor 25 is more positive than the collector voltage of transistor 24 whereby the PN junction represented by the base of transistor 24 and the emitter 30 is forwarded biased, lowering the collector voltage of transistor 25 and causing transistor 24 to turn on and transistor 25 to turn off. Consequently, intermediate storage unit FF2 is driven into the 0 state so that it inversely corresponds to the state of storage unit FFI.
  • the clock pulse 17 is at -I volts, the gate represented by emitters 30 and 31 is blocked and emitter 33 becomes more negative than emitter 32. Regardless of whether storage unit FF3 is in the 1 or 0 state, it will be driven or maintained in the 1 state.
  • the collector voltage of transistor 26 is more positive than the collector voltage of transistor 27.
  • the PN junction represented by the base of transistor 27 and the emitter 33 is forward biased while the PN junction represented by the base of transistor 26 and the emitter 32 is reversed biased. Accordingly, the collector voltage of transistor 26 decreases and turns transistor 26 on while driving transistor 27 off.
  • the forward biased PN junction represented by the base of transistor 27 and the emitter 33 in effect adds current to the transistor 26 which is initially off.
  • current is taken away from a transistor which is on in order to drive a storage unit into the opposite state.
  • the storage unit FF3 has been driven into the 1 state and now corresponds with the original state of storage unit FFI from which the binary information was transferred.
  • the only inversion that takes place is in the intermediate storage unit FF2.
  • FIG. 3 The embodiment and circuit construction of FIG. 3 are especially suitable for microminiaturized monolithic integrated semiconductor circuits since the multiemitter transistors 22-27 are identical ad can be fabricated and processed at the same time and in like manner in a single semiconductor material. Moreover, the embodiment of FIG. 3 is especially suitable for incorporation in monolithic integrated semiconductor circuits of the single or double epitax ial type which will be more fully described later in connection with FIGS. 6 and 7.
  • FIG. 4 illustrates the top view of a monolithic integrated semiconductor circuit of the triple diffused type embodying transistors l-4, resistors 11-14 and gate 34 illustrated in FIG. 2.
  • transistor 1 comprises a diffused collector 1c, diffused base 1b and diffused emitter 1e
  • transistor 2 comprises diffused collector 2c, diffused base 2b, and diffused emitter 2e
  • transistor 3 comprises diffused collector 3c, diffused base 312 and diffused emitter 3e
  • transistor 4 comprises diffused collector 4c, diffused base 4b and diffused emitter 4e.
  • the transistors 18 and 19 of gate 34 are formed respectively in the diffused collectors 3c and 4c of transistors 3 and 4.
  • Transistor 18 comprises collector region 180 which is integral with the diffused collector 3c and ohmically connected therewith in the semiconductor material.
  • the base 18b of transistor 18 is formed within the collector 3c or 180, the diffused emitter of transistor 18 being 18e.
  • the transistor 19 is formed within the diffused collector 4c.
  • transistor 19 comprises collector region 190 integral with the collector 414 and ohmically connected therewith within the semiconductor material, diffused base 19b and diffused emitter 19e.
  • Transistor 1-4 and transistors 18 and 19 interconnected in the manner shown comprise one bit of a shift register. FIG.
  • transistors 34 and 35 formed within the diffused collectors 1c and 20 which transistors 34 and 35 are identical to 18 and 19 and would comprise the gate coupled to a preceeding intermediate storage unit of the shift register for controlling the inputs to the storage unit FFl.
  • the resistors 11-14 are diffused resistors made at the same times as the collector diffusion so that one end of each resistor is integral with and ohmically connected to the collector of its corresponding transistor.
  • the monolithic integrated semiconductor circuit is fabricated by the planar process in which an oxide film is thermally grown on a P-type silicon substrate of the desired resistivity by placing it in a furnace at an elevated temperature and passing an oxidizing agent over it.
  • the silicon dioxide produced acts as a masking medium against the impurities which are later diffused into the substrate. Holes are produced in the oxide film to allow subsequent difiusion processes to form the isolation, resistor and transistor functions.
  • These holes which are patterns of the desired circuit elements are produced by photolithographic techniques. Contacts and interconnections to the circuit elements are made by similar photolithographic techniques using for example evaporated aluminum over the oxide to form a pattern connecting the circuit elements together.
  • the connecting pattern comprises conductive strips 36 37, etc.
  • FIG. 5 is a cross section taken along the lines A-A of FIG. 4 and illustrates principally the semiconductor portion of the structure to show the transistor 1 and gate transistor 34 formed in its collector region.
  • transistor 1 comprises the N-type collection region lo, the P-type base region lb, and the N-type emitter region le.
  • the gating transistor 34 is identical to the transistors 18 and 19 and comprises the N-type collector region 10.
  • the metal contact 36 is deposited on the P-N junction formed by the zones 10 and 39 and shorts out this P-N junction so that the base and collector electrodes of transistor 34 are shorted together as is illustrated in FIG. 2 with respect to the transistor 18 and 19.
  • FIG. 6 illustrates the top view of a monolithic integrated semiconductor circuit of the single epitaxial type embodying the multiemitter transistors 22 through 25 and resistor 11-14 illustrated in FIG. 3.
  • the monolithic integrated semiconductor circuit of the epitaxial type comprises a P-type silicon substrate having a N-type epitaxial layer deposited on one surface thereof.
  • the multiemitter transistors 22-25 on formed by silicon oxide masking, diffusion techniques and photolithographic techniques to form the isolation, resistor and transistor functions whereby the transistor 22, for example comprises an N-type collector region 41 comprised of the epitaxial layer, a P-type diffused base region 42 and diffused multiemitters 28 and 43.
  • the diffused emitter 43 is ohmically connected to the emitter 44 of transistor 23 and to ground by the metallic strip 52.
  • the additional emitter 28 of transistor 22 would be connected to a proceeding stage of the shift register.
  • the resistors 11-14 are diffused resistors having one end respectively connected to the collectors of transistors 22-25 by metallic strips 53.
  • the circuit elements illustrated in FIG. 6 are interconnected utilizing a connecting pattern in the form of strips over the silicon oxide insulating layer to interconnect the various components and where the metal strips need to crossover one another to effect the circuit interconnections, multi level interconnections are utilized as is more fully described in the aforementioned copending application.
  • strips 53 are illustrated as crossing over the strips 53 which connect the base of transistor to a resistor. This crossover can be effected using multilevel connections, strips 54 being formed on a first level pattern and strips 53 being formed on a second higher level.
  • FIG. 7 is a cross section of FIG. 6 taken along the lines B-B and illustrated the semiconductor portion of the structure wherein 45 is the P-type silicon substrate.
  • 41 is the N-type epitaxial layer deposited on the surface of the P-type substrate 45, 47 represents the p+ isolation diffusions made by selectively diffusing a P-type impurity through the N-type epitaxial layer in order to leave islands of N-type material 41 in which the circuit elements are to be formed.
  • 50 is the P-type diffused base region of transistor 22 formed in the N-type epitaxial collector region 41 and 28 and 43 are the N-type diffused multiemitter regions.
  • 51 represents an N+ buried diffused region under the collector region 41 to provide lower collector saturation resistance as is known from U.S. Pat. No. 3,21 1,972.
  • An information transfer system comprising: a first storage unit containing binary information, a second storage unit, a variable energizing source, transfer means including an intermediate storage unit responsive to said variable energizing source for transferring binary infonnation from said first storage unit to said second storage unit, said transfer means including gate means responsive to one condition of said variable energizing source for transferring said binary information from said first storage unit to said intermediate storage unit, while blocking the transfer of binary information into said second storage unit and responsive to a different condition of said energizing source for transferring said binary information from said intermediate storage unit into said second storage unit while blocking the transfer of binary information from said first storage unit into said intermediate storage unit and nonresponsive to said energizing source when it is changing from said one condition to said different condition and wherein said first storage unit comprises first and second transistors, the collector of said first transistor being directly connected to the base of said second transistor, the collector of said second transistor being directly connected to the base of said first transistor, the emitters of said first and second transistor being connected together, said intermediate storage unit compris
  • An information transfer system comprising a first storage unit containing binary information, said first storage unit comprising first and second transistors, the collector of said first transistor being directly connected to the base of said second transistor, the collector of said second transistor being directly connected to the base of said first transistor and the emitters of said first and second transistors being connected together, a second storage unit comprising third and fourth transistors, the collector of said third transistor being directly connected to the base of said fourth transistor, the collector of said fourth transistor being directly connected to the base of said third transistor, and the emitters of said third and fourth transistors being connected together, a variable energizing source, transfer means including an intennediate storage unit responsive to said variable energizing source for transferring binary information from said first storage unit to said second storage unit, said transfer means including gate means responsive to one condition of said variable energizing source for transferring said binary information from said first storage unit to said intermediate storage unit while blocking the transfer of binary infonnation into said second storage unit and responsive to a different condition of said energizing source for transferring
  • first, second, third and fourth asymmetrically conductive means each comprise a transistor having its base and collector electrodes connected together.
  • An infonnation transfer system comprising a semiconductor wafer, a first storage unit containing binary information fonned at one surface of said semiconductor wafer, a second storage unit formed at said one surface of said semiconductor wafer, a variable energizing source, transfer means formed at said one surface of said semiconductor wafer, said transfer means including an intermediate storage unit responsive to said variable energizing source for transferring binary information from said first storage unit to said second storage unit, said transfer means including gate means responsive to one condition of said variable energizing source for transferring said binary information from said first storage unit to said intermediate storage unit while blocking the transfer of binary information into said second storage unit and responsive to a different condition of said energizing source for transferring said binary information from said intermediate storage unit into said second storage unit while blocking the transfer of binary information from said first storage unit into said intermediate storage unit and nonresponsive to said energizing source when it is changing from said one condition to said different condition and wherein said first storage unit, said second storage unit and said intermediate unit each comprise a direct coupled collector to base triple
  • An information transfer system comprising a semiconductor wafer, a first storage unit containing binary information formed at one surface of said semiconductor wafer, a second storage unit formed at said one surface of said semiconductor wafer, a variable energizing source, transfer means formed at said one surface of said semiconductor wafer, said transfer means including an intermediate storage unit responsive to said variable energizing source for transferring binary information from said first storage unit to said second storage unit, said transfer means including gate means responsive to one condition of said variable energizing source for transferring said binary information from said first storage unit to said intermediate storage unit while blocking the transfer of binary information into said second storage unit and responsive to a different condition of said energizing source for transferring said binary information from said intermediate storage unit into said second storage unit while blocking the transfer of binary information from said first storage unit into said intermediate storage unit and nonresponsive to said energizing source when it is changing from said one condition to said'different condition and wherein said semiconductor wafer comprises a semiconductor substrate of one conductivity type and an epitaxial layer of opposite conductivity type on said semiconductor
  • An infonnation transfer system comprising: a first storage unit containing binary information, a second storage unit, a variable energizing source, transfer means including an intermediate storage unit responsive to said variable energizing source for transferring binary information from said first storage unit to said second storage unit, said transfer means including gate means responsive to one condition of said variable energizing source for transferring said binary information from said first storage unit to said intermediate storage unit, while blocking the transfer of binary information into said second storage unit and responsive to a different condition of said energizing source for transferring said binary information from said intermediate storage unit into said second storage unit while blocking the transfer of binary information from said first storage unit into said intermediate storage unit and nonresponsive to said energizing source when it is changing from said one condition to said different condition and wherein said first storage unit comprises first and second transistors, the collector of said first transistor being directly connected to the base of said second transistor, the collector of said second transistor being directly connected to the base of said first transistor, the emitters of said first and second transistor being connected together, said intermediate storage unit compris
  • An information transfer system comprising a first storage unit containing binary information, said first storage unit comprising first and second multiemitter transistors, the collector of said first transistor being directly connected to the base of said second transistor, the collector of said second transistor being directly connected to the base of said first transistor and one of the emitters of said first and second transistors being connected together, a second storage unit comprising third and fourth multiemitter transistors, the collector of said third transistor being directly connected to the base of said fourth transistor, the collector of said fourth transistor being directly connected to the base of sad third transistor, and one of the emitters of said third and fourth transistors being connected together, a variable energizing source, transfer means including an intermediate storage unit responsive to said variable energizing source for transferring binary information from said first storage unit to said second storage unit said transfer means including gate means responsive to one condition of said variable energizing source for transferring said binary information from said first storage unit to said intermediate storage unit while blocking the transfer of binary information into said second storage unit and responsive to a different condition of said energizing source

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  • Semiconductor Memories (AREA)
  • Logic Circuits (AREA)
  • Shift Register Type Memory (AREA)
  • Bipolar Integrated Circuits (AREA)
US650832A 1967-07-03 1967-07-03 Information transfer system Expired - Lifetime US3573754A (en)

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US3297950A (en) * 1963-12-13 1967-01-10 Burroughs Corp Shift-register with intercoupling networks effecting momentary change in conductive condition of storagestages for rapid shifting
US3423737A (en) * 1965-06-21 1969-01-21 Ibm Nondestructive read transistor memory cell
US3427598A (en) * 1965-12-09 1969-02-11 Fairchild Camera Instr Co Emitter gated memory cell
US3391311A (en) * 1966-02-07 1968-07-02 Westinghouse Electric Corp Constant current gain composite transistor

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3693057A (en) * 1968-03-01 1972-09-19 Ibm Monolithic circuits with pinch resistors
US3885169A (en) * 1971-03-04 1975-05-20 Bell Telephone Labor Inc Storage-processor element including a bistable circuit and a steering circuit
US3851187A (en) * 1971-03-05 1974-11-26 H Pao High speed shift register with t-t-l compatibility
US3831155A (en) * 1971-12-29 1974-08-20 Tokyo Shibaura Electric Co Nonvolatile semiconductor shift register
US3715030A (en) * 1972-01-03 1973-02-06 Trw Inc Integratable high speed reversible shift register
US3771030A (en) * 1972-01-26 1973-11-06 G Barrie Large scale integrated circuit of reduced area including counter
US4125877A (en) * 1976-11-26 1978-11-14 Motorola, Inc. Dual port random access memory storage cell
US4151609A (en) * 1977-10-11 1979-04-24 Monolithic Memories, Inc. First in first out (FIFO) memory
US4434474A (en) 1981-05-15 1984-02-28 Rockwell International Corporation Single pin time-sharing for serially inputting and outputting data from state machine register apparatus
US4879680A (en) * 1985-10-18 1989-11-07 Texas Instruments Incorporated Multi-slave master-slave flip-flop

Also Published As

Publication number Publication date
DE2037023B2 (de) 1974-02-28
NL6809401A (enrdf_load_stackoverflow) 1969-01-07
GB1321895A (en) 1973-07-04
NL7010709A (enrdf_load_stackoverflow) 1971-01-27
FR2055522A5 (enrdf_load_stackoverflow) 1971-05-07
US3614469A (en) 1971-10-19
DE1774492A1 (de) 1972-01-13
GB1226673A (enrdf_load_stackoverflow) 1971-03-31
BE753696A (fr) 1970-12-31
DE2037023A1 (de) 1971-02-04
BE735610A (enrdf_load_stackoverflow) 1969-12-16
FR1574949A (enrdf_load_stackoverflow) 1969-07-18
DE2037023C3 (de) 1974-09-26

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