US3508194A - Error detection and correction system - Google Patents
Error detection and correction system Download PDFInfo
- Publication number
- US3508194A US3508194A US357368A US3508194DA US3508194A US 3508194 A US3508194 A US 3508194A US 357368 A US357368 A US 357368A US 3508194D A US3508194D A US 3508194DA US 3508194 A US3508194 A US 3508194A
- Authority
- US
- United States
- Prior art keywords
- reg
- bus
- data
- exit
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
- G11B20/1833—Error detection or correction; Testing, e.g. of drop-outs by adding special lists or symbols to the coded information
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
Definitions
- RESET D 7-12 -DATA REG 8 TR READ TRANSLATE 22B-As BIT 5 A 21A 82W BUS OUT 2 A 83B-AX BUS OUTS A ,+DATA REG 1 TR +READ SHIFT BYTE l "MB-AT 2 0R4 READ TRANSLATE BIT 2 22B-AY ZZME READ TRANSLATE BIT 6 April 21, 1970 D.'T.
- FIG. 16 AE +READ TRANSLATE BIT 6 NA +R-W REG4 TR 22B-BA April 21, 1970 o. T. BROWN Filed April 6 1964 FIG. 16
- FIG.I8A READ MHV SHIFT BYTE 10R3 A 22W +READTRANSLATE m2 AP -DATA REG 'ITR AM 228% +RYEADTRANSLATE BITO 21 5A +R-W REG 0 TR April 21, 1970 D. T. BROWN ERROR DETECTION AND CORRECTION SYSTEM Filed April 6 1964 516 Sheets-Sheet 19 FIG.I8A
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Signal Processing (AREA)
- Detection And Correction Of Errors (AREA)
- Error Detection And Correction (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Indexing, Searching, Synchronizing, And The Amount Of Synchronization Travel Of Record Carriers (AREA)
- Programmable Controllers (AREA)
Description
April 7 D. T. BROWN 3,508,194
ERROR DETECTION AND CORRECTION SYSTEM Filed April 6, 1964 {516 Sheets-$heet 1 FIG. 1
2 CYCLIC 0m REDUNDANCY INPUT RESIDUE cIRcuIT DIGITAL p COMPARING O CIRCUIT SUB-BLOCK ERROR PATTERN CHECK I CIRCUT RESIDUE CIRCUIT SUB-BLOCK POSITION 7 ERROR 4 5 INDICATOR INVENTOR DAVID I BROWN ATTORNEY April 21, 1970 D. T. BROWN 3,508,194
ERROR DETECTION AND CORRECTION SYSTEM Filed April 6, 1964 516 Sheets-Sheet 2 LRC SAMPLE nmz R v CLOCK r 22 A m ERROR 7 A SHIFT C 2s COR K R 2 5 PATTERN 52 RD r0 coRR I R TEST WRITE 0 1a DATA ENTRY\ K 54 T0 TAPE A u WR cRc CHAR CPU wR DATA R/W OE T0 CPU\ TAPE RD DATA 14 10 REG 16 x9 mo TRACK SET UP A A OR FIND A M TRACK FIND TR GK n E X9 55 X9 TEST coRR TIME se BEGIN FIND \32 42 TRACK TIME I A /Si cRc CHAR 1 I R N CORRECTIONS L, A
READ TIME R I 45 0 R I NORMAL READ 26, a E /5 RRTocoR A m RUE 21 R M R CLOCK ERROR ENTERVRC I A ERROR CLOCK I TRACK 56 L 20 mocmwe GARE A 0 x9 L ZERO TEST/47 LRC-SUM A LR 0 j FiQR LRC SAMPLE TIME M;
April 21, 1970 D; T. BROWN 3,505,194
ERROR DETECTION AND CORRECTION SYSTEM Filed April 6, 1964 E 516 Sheets-Sheet 3 FIG.3A
j EPR & VRC READ WRITE CLOCK Bus SS M 109MB J 52 3 B B FlNAL SKEW R-W AMPS REGS REG 48A & B, 40A &B 18A & B
50 44A & B 20A & B e & v coir: FIRST CRCR L BIT 28A,
36 28B 27B 1 B i DENS LRCR & XLATOR SELN 21A8AB CONTROL 408A & B 46A&5 22A & B LINES T0 A TAPE UNITS (J 99A A B READ WRlTE HI CLIP RECG CLOCK 4. VRC CONTROL 57A B B 106A &B 47A & B
LINES I FROM W TAPE UNITS DEL CTR SIMULATE SIMULATE 400A A B GATING REG SELECT HTA&B,120 154,135 433 B L G0 WR CLK & DEL CTR BKWD LR Q CONTROLS 85A&B 405A I12A&B
RD w DELAY wB CLK CONDITION CTR &DEL CTR 104 113A & B, 050-5 145 106A & B
TU SEL RESET DECODER 61A & B 62A & B SEO IND UF 131A & B BUSY LATCHES 432 96A,B,C,D 87A & B, A 94A1\& B
April 21, 1970 3,508,194
D. T. BROWN ERROR DETECTION AND CORRECTION SYSTEM Filed April 6, 1964 516 Sheets-Sheet 4.
' FIG.3B
R 1 c DATA BUS COMPARE CHECK m P 26A & 8 26A & B 23A & B R s T T' BYTE R HIF 74A a CTl. BUS IN 72A & B, 811 75A & B 75A & a 9 A W W J ERROR BUS OUT TAR: B 6 DATA REG P 35 e- 24A & B T 1 F Hl/LOW ERROR BUS OUT COMPARE STOP cm: W
TAPE OP COMMAND gg ggg LINE DECODING T MANUAL MODE COMMAND CONTROLS CONTROLS E 121,129 65A &8 64A &B
ERR) ARRR TU SEL PULSE & DECODER A GATING SENSE & TU SEL 95A & B GATING REG 60A &B,95A &B
A 55A & B A UF SCAN INTER- E L AF SEER? 955 5% 9m. CA) W 54A & B
UF INTR- INTER- SCANNER FACE OUT FACE IN 97A,B,C,D 5A R B 4 TU LINES VALID 69A A B April 21, 1970 Filed April 6, 1964 D. T. BROWN ERROR DETECTION AND CORRECTION SYSTEM 516 Sheets-Sheet 5 BUS m 2 EXIT EXIT EXIT 8OB-AB AA A5 A0 ENTR ENTR ENTR 8OB AD -BUS IN 0 A0 I AR AS SOHO BUS IN 1 BUS [N5 EXIT EXIT EXIT ENTR ENTR A A A A 808% AD AE AF AT F AU 80B AH BUS IN 4 ENTR A 805M BUS m5 Av EXIT EXIT ENTR ENTR 80B AE *BUS IN 7 9A AG AH AW AX 80B sus m a ADDRESS IN EXIT EXIT ENTR ENTR A NP AJ AK AY AZ BOB-AM SERVICE N EXIT EXIT ENTR ENTR 8 A A OB AJ AL AM BA BB 808 STATUS IN EXIT EXIT ENTR 8OB AN 0PERATIONAL IN AN AP 80 ENTR BC EXIT JAN 8OB BE -REOUEST m1 EXIT CHAN A ril 21, 1970 I 0.1". BROWN 3,508,194
ERROR DETECTION AND CORRECTION SYSTEM Filed April 6, 1964 516 Sheets-Sheet 8 EXIT EXIT EXIT 99 SEL HIGH ORDER Cg F a; G g
9:19 :23 52-AR B EXIT EXIT EXIT EXIT 5H6 ML A A*X r A? A;
-WR|TE BUS 5 F 52% SEL TU 5 99 AR -WRITE s 7 52-AA EXIT EXIT 52% WRITE BUS e 8 F 8 52M 'WR!TE BUS 5 EXIT EXIT EXIT 99 MM B B*F r B 99 -AB W2 99 -AA EXIT EXIT EXIT 52 WRITE BUS P g B g H F BJ 52 AL WR|TE 9us2 99 SET READ smus EXIT EXIT 99 REWIND UNLOAD BO BR 99 BKWD EXIT EXIT EXIT EXIT 99 -Az 99 as r TUO BL BM I BN BP 99 -AN 99 WRITE TRIGGER RELEASE f 99 WR|TE PULSE SET.WRITE smus 99 SEL TUB 99 -AV L EXIT L EXIT EXIT EXIT EXfT 99 AW as as 9e BU BV ew BX F BZ 99 M REWIND April 21, 1970.
Filed April 6, 1964 D. "r. BROWN ERROR DETECTION AND CORRECTION SYSTEM 516 Sheets-Sheet 1O F|G.9 WAN +DATA REG 3 TR A I'READ BYTE 2 OR i q AV +ADDRESS 5W 2 SOB-AR A +ADDRESS m M L +sERv1cE m AB l v +BUS IN 2 AE +DATA REG 11 TR 25A,80A Z'AN A A 755M +READ BYTE 3 AF +DATA REC YTR 758M +READ BYTE 4 A 16 AF +DATA REG 4 TR AK 1 OR AT R 4 R A AX A HF +DATA REG 8 TR AH A OR OR +BUS IN?) 23A,80A AM 57 AE +SENSE BITE AN AL AM A N BUS m3 6OB As +ADDRESS SW5 AP AR 25A 96D BB +BUSY STATUS A 539% +STATUS m TR A0 April 21, 19 70 Filed April 6, 1964 D. "r. BROWN ERROR DETECTION AND CORRECTION SYSTEM 516 Sheets-Sheet 11 FIGJO 958 +444 SEL 4 44 545% +ADDRESS 44 SPAN +SENSE BIT4 A 72B AG +$ERV|CE IN AB WAN +0444 REG 5 TR OAR +4540 BYTE 2 AC {MN +0444 REG 1 TR lT OR N IN 4 7584 +4540 BYTE3 AF AV AE 668M +0444 0044 +BUS IN 4 4 HF -ILLEGAL COM 44 A 23A,80A 53MB +s444us 44 TR BA L +044 END TR OR amt 0P TR A K MN +0444 REG 9 TR O R 758M +4440 BYTE 4 AG :E HF +0444 REG 4044 A 4 A AH {HF +0444 REG 2 TR M L {HF +0444 REG 6 44 AL A WW +SENSE BITS AP F OR} ()R N BUS IN 5 958% W 35L 5 TR B8 AM 44 234,429
+BUS 445 +BUSY s444us A M REWlND UNLOAD TR April 21, 1970 Filed April 6, 1964 FIGJI 95B BE +TU SEL 6 TR D. T. BROWN 3,508,194
ERROR DETECTION AND CORRECTION SYSTEM 516 Sheets-Sheet 12 54B AQ I-ADDRESS IN AA 1 ISENSE [III 6 WAH +UN|T CHECK TR A 53B BD ISTAIUS IN IR AD WAN +DATA REG 7 TR A 16 AN IDATA REG 5 TR OR OR N B IIII6 +READ mm A M E AF 25A,129 75B'AT AH +BUS IN 6 AE 12 AN IDATA REG II III 23A,80A,I29
758M +READ BYTE 4 42 AF +DATA REG I2 IR HF +DATA REG 4 TR AM 1 OR OF? N BUS IN? A AR AN B NF +DATA REGS TR AP A0 I AR +BUS m 7 A 23A,80A A0 378M +UNIT EXCEPTION TR A5 I 0R +SENSE BY 7 A 58-AM AT A 95B AC +TU SEL 7 IR AV April 21, 1970 Filed April 6 1964 D. T. BROWN ERROR DETECTION AND CORRECTION SYSTEM 516 Sheets-Sheet 15 F IGJZ us T 825-80 B 3 A T7 83% BUS ou A A0 DATA REG 121R 9,11,18A
+WRlTE SET BYTE 2 7 M A A SBA +WR|TE SET BYTE 3 A ?5B-AH AD A ' R H DATA REG 12 m 75A 27AM -w REG R A -RESET 0 7-12 YZB-BE A 835 +BUS 0m 6 AH 125m A BZB-BF AK A DATA REG 11 TR 9,11,18A
OR N A AL AM AN DATA REG H m 75A A ---AM 22MB +RE'AD TRANSLATE BIT 6 AP April 21, 1970 D. T. BROWN ERROR DETECTION AND CORRECTION SYSTEM Filed April 6 1964 516 Sheets-Sheet 14 82W +BUS OUT 1 T A AA +BUS ours 83B-AW A AC DATA REG 10TR 8,10,1BA A A0 L DATA REG H REG 5 TR 10m 75A 27A A 758 +WR|TE s51 BYTE 2 AG 758% +WR|TE SET awn +BUS OUT 4 82B-BE A 72W RESET 01-12 AH +8USOUT 0 828-88 A +READ SHIFT BYTEZ AK 74B AT 0R 4 0 TA REG 9m A AN L l 8,10,18A
A TRAS T T4 228 +RE D N LA E Bl DATA REG 9TR April21,i970' 053mm] 3,508,
ERROR DETECTION AND CORRECTION SYSTEM Filed April 6. 1964' 516 Sheets-Sheet 15 MM H REG 7 TR A H REG T0 DATA REG BCF OR Hf BUS OUT 7 A 753M WRITE SET BYTE 1 AA 82880+ BUS OUT 3 A 75BAH+WRITE SET BYTE 3 AC |+DATAREG8TRAF l 9,11,18A,19A
RESET D 7-12 -DATA REG 8 TR READ TRANSLATE 22B-As BIT 5 A 21A 82W BUS OUT 2 A 83B-AX BUS OUTS A ,+DATA REG 1 TR +READ SHIFT BYTE l "MB-AT 2 0R4 READ TRANSLATE BIT 2 22B-AY ZZME READ TRANSLATE BIT 6 April 21, 1970 D.'T. BROWN Filed April 6 1964 516 Sheets-Sheet 16 +DATA REG 6 TR HG 15 L 8,10,48AAF 828% +BUSOUT1 A +BUS OUT 5 83B-AW A N AC AE AF *DATA REG 6 TR 27AM +R w REG 7 TR 2mm AU 72B RESET 0 1-6 m +R-W REG 5 TR 75H +WRITE SET BYTE 5 T YSB-AP SET BYTE DATA REG 5 m M L 8,10,21A MHV +READ SHIFT BYTE10R3 A AH 745% +R-w REG T0 DATA REG BCF A 82MB +BUS ouro AJ 1 A N U 82B-BE OUT 4 AK AV AN -DATA REG 5m A0 21A,?5A
AE +READ TRANSLATE BIT 6 NA +R-W REG4 TR 22B-BA April 21, 1970 o. T. BROWN Filed April 6 1964 FIG. 16
316 Sheets-Sheet 1 '7 2mg +READ TRANSLATE B|T5 A 828% +BUS 0UT3 A +BUS mm 838 AY A AC 2TA REG T 4TR 21A,T5A +wBTTE SET BYTE 2 A AG 758 +WRITE SET BYTE 1 H0 +R-W REG T0 BATA REG BCF +Bus ouTe UB AW RESET BT-B AH +BUS ouT2 82B BF A My +READ SHIFT BYTE 10R3 AK 3TR21A,75A
A AL A 22B AL+READ TRANSLATE BIT 4 AP A NEW +READ TRANSLATE BIT y April 21, 1970 D. T. BROWN I 3,508,194
ERROR DETECTION AND CORRECTION SYSTEM Filed April 6, 1964 316 Sheets-Sheet 1s SSHZ TRANSLATE MD R-W REG T0 DATA REG BCF +R-W REG 1 TR 278 DATA REG 2 TR M 82B +BUS oun 75B AP +WRITE SET BYTE 1 83B +BUS 0ur5 A I N Ac AF +READ HHS TRANSLATE am A AG F RESET D1-6 A +DATA REG 2 TR AF 8,10,19A L A OR AL ORW 82MB +BUS ouro A Av +WRITE SET BYTE 2 A N +DATA G A AA AN BZB-BE AH AN 8,10,19A,20A
READ MHV SHIFT BYTE 10R3 A 22W +READTRANSLATE m2 AP -DATA REG 'ITR AM 228% +RYEADTRANSLATE BITO 21 5A +R-W REG 0 TR April 21, 1970 D. T. BROWN ERROR DETECTION AND CORRECTION SYSTEM Filed April 6 1964 516 Sheets-Sheet 19 FIG.I8A
ERROR DETECTION AND CORRECTION SYSTEM Filed April 6, 1964 516 Sheets-Sheet 2O FIGJSB *RW REG 6TR 25A,52
+R-W REG 6 TR 2mm AW +R-W REG 6 TR 25A R-W REG 6TR +R-W REG 7 TR R-W REG T TR 27A. +R-W REG T TR 25A R-W REG 7 TR 25A,52
+R-W REG 4 TR 25A R-W REG 5 TR 25A,52
+R-W REG 5 TR T54 -R-W REG 5 TR 27A AV
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US35736764A | 1964-04-06 | 1964-04-06 | |
| US35737164A | 1964-04-06 | 1964-04-06 | |
| US35736864A | 1964-04-06 | 1964-04-06 | |
| US357370A US3404376A (en) | 1964-04-06 | 1964-04-06 | Computer sub-system circuits |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US3508194A true US3508194A (en) | 1970-04-21 |
Family
ID=27502904
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US357371A Expired - Lifetime US3508195A (en) | 1964-04-06 | 1964-04-06 | Error detection and correction means |
| US357368A Expired - Lifetime US3508194A (en) | 1964-04-06 | 1964-04-06 | Error detection and correction system |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US357371A Expired - Lifetime US3508195A (en) | 1964-04-06 | 1964-04-06 | Error detection and correction means |
Country Status (8)
| Country | Link |
|---|---|
| US (2) | US3508195A (en) |
| JP (1) | JPS4942804B1 (en) |
| BE (1) | BE662155A (en) |
| CH (1) | CH431147A (en) |
| DE (1) | DE1287339B (en) |
| GB (2) | GB1031554A (en) |
| NL (1) | NL162760C (en) |
| SE (1) | SE310807B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5617432A (en) * | 1994-11-09 | 1997-04-01 | International Business Machines Corporation | Common error protection code for data stored as a composite of different data formats |
| US6298398B1 (en) * | 1998-10-14 | 2001-10-02 | International Business Machines Corporation | Method to provide checking on data transferred through fibre channel adapter cards |
| CN102812431A (en) * | 2010-03-22 | 2012-12-05 | Lrdc系统有限公司 | A method of identifying and protecting the integrity of a set of source data |
| CN116107783A (en) * | 2021-11-11 | 2023-05-12 | 三星电子株式会社 | Systems and methods for detecting on-chip communication errors in reconfigurable hardware systems |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3582633A (en) * | 1968-02-20 | 1971-06-01 | Lockheed Aircraft Corp | Method and apparatus for fault detection in a logic circuit |
| US7228467B2 (en) * | 2003-10-10 | 2007-06-05 | Quantum Corporation | Correcting data having more data blocks with errors than redundancy blocks |
| US11095295B2 (en) | 2018-06-26 | 2021-08-17 | Silicon Laboratories Inc. | Spur cancellation for spur measurement |
| US10840897B1 (en) * | 2019-10-31 | 2020-11-17 | Silicon Laboratories Inc. | Noise canceling technique for a sine to square wave converter |
| US11038521B1 (en) | 2020-02-28 | 2021-06-15 | Silicon Laboratories Inc. | Spur and quantization noise cancellation for PLLS with non-linear phase detection |
| US11316522B2 (en) | 2020-06-15 | 2022-04-26 | Silicon Laboratories Inc. | Correction for period error in a reference clock signal |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3051784A (en) * | 1961-05-12 | 1962-08-28 | Bell Telephone Labor Inc | Error-correcting system |
| US3069657A (en) * | 1958-06-11 | 1962-12-18 | Sylvania Electric Prod | Selective calling system |
| US3222643A (en) * | 1961-06-22 | 1965-12-07 | Ibm | Error detecting and correcting systems |
| US3291972A (en) * | 1961-08-21 | 1966-12-13 | Bell Telephone Labor Inc | Digital error correcting systems |
| US3308429A (en) * | 1963-11-15 | 1967-03-07 | Bell Telephone Labor Inc | Cyclic and multiplication by 2 mod n permutation decoder for systematic codes |
| US3311878A (en) * | 1963-02-14 | 1967-03-28 | Ibm | Error checking system for binary parallel communications |
| US3315228A (en) * | 1963-08-19 | 1967-04-18 | Futerfas Jack | System for digital communication error measurements including shift registers with identical feedback connections |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3209327A (en) * | 1960-02-23 | 1965-09-28 | Ibm | Error detecting and correcting circuit |
| US3155818A (en) * | 1961-05-15 | 1964-11-03 | Bell Telephone Labor Inc | Error-correcting systems |
| US3227999A (en) * | 1962-06-15 | 1966-01-04 | Bell Telephone Labor Inc | Continuous digital error-correcting system |
-
0
- GB GB1053174D patent/GB1053174A/en active Active
-
1964
- 1964-04-06 US US357371A patent/US3508195A/en not_active Expired - Lifetime
- 1964-04-06 US US357368A patent/US3508194A/en not_active Expired - Lifetime
-
1965
- 1965-03-26 GB GB13074/65A patent/GB1031554A/en not_active Expired
- 1965-04-01 NL NL6504178.A patent/NL162760C/en not_active IP Right Cessation
- 1965-04-02 JP JP40018988A patent/JPS4942804B1/ja active Pending
- 1965-04-03 DE DEJ27831A patent/DE1287339B/en not_active Withdrawn
- 1965-04-05 CH CH471265A patent/CH431147A/en unknown
- 1965-04-06 BE BE662155A patent/BE662155A/xx unknown
- 1965-04-06 SE SE4439/65A patent/SE310807B/xx unknown
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3069657A (en) * | 1958-06-11 | 1962-12-18 | Sylvania Electric Prod | Selective calling system |
| US3051784A (en) * | 1961-05-12 | 1962-08-28 | Bell Telephone Labor Inc | Error-correcting system |
| US3222643A (en) * | 1961-06-22 | 1965-12-07 | Ibm | Error detecting and correcting systems |
| US3291972A (en) * | 1961-08-21 | 1966-12-13 | Bell Telephone Labor Inc | Digital error correcting systems |
| US3311878A (en) * | 1963-02-14 | 1967-03-28 | Ibm | Error checking system for binary parallel communications |
| US3315228A (en) * | 1963-08-19 | 1967-04-18 | Futerfas Jack | System for digital communication error measurements including shift registers with identical feedback connections |
| US3308429A (en) * | 1963-11-15 | 1967-03-07 | Bell Telephone Labor Inc | Cyclic and multiplication by 2 mod n permutation decoder for systematic codes |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5617432A (en) * | 1994-11-09 | 1997-04-01 | International Business Machines Corporation | Common error protection code for data stored as a composite of different data formats |
| US6298398B1 (en) * | 1998-10-14 | 2001-10-02 | International Business Machines Corporation | Method to provide checking on data transferred through fibre channel adapter cards |
| CN102812431A (en) * | 2010-03-22 | 2012-12-05 | Lrdc系统有限公司 | A method of identifying and protecting the integrity of a set of source data |
| US8769373B2 (en) | 2010-03-22 | 2014-07-01 | Cleon L. Rogers, JR. | Method of identifying and protecting the integrity of a set of source data |
| CN116107783A (en) * | 2021-11-11 | 2023-05-12 | 三星电子株式会社 | Systems and methods for detecting on-chip communication errors in reconfigurable hardware systems |
| US11994938B2 (en) | 2021-11-11 | 2024-05-28 | Samsung Electronics Co., Ltd. | Systems and methods for detecting intra-chip communication errors in a reconfigurable hardware system |
Also Published As
| Publication number | Publication date |
|---|---|
| CH431147A (en) | 1967-02-28 |
| SE310807B (en) | 1969-05-12 |
| DE1287339B (en) | 1969-01-16 |
| GB1053174A (en) | |
| JPS4942804B1 (en) | 1974-11-16 |
| GB1031554A (en) | 1966-06-02 |
| NL6504178A (en) | 1965-10-07 |
| NL162760C (en) | 1980-06-16 |
| BE662155A (en) | 1965-08-02 |
| US3508195A (en) | 1970-04-21 |
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