DE1287339B - Circuit arrangement for error detection and correction - Google Patents

Description

1 2

The invention relates to a circuit block in the non-equivalent elements caused by

arrangement for error detection and correction in inequality, indicating the presence of errors

binary encrypted data blocks in which each in indicates the deletion of the receiving register and

characters made up of η bits in parallel form for transferring the content of the first shift

A parity bit to supplement its bit registers in the receive register as well as the input

number to odd or even write a binary 1 bit in the lowest

(vertical redundancy) and the end of a stage of the first shift register, furthermore the

Data block is marked by a check character, simultaneous shifting of the contents of both

using feedback shift registers and comparing the content of the

registers to calculate check characters for io second shift register with the content of the

cyclical redundancy check. Receive register in the antivalence elements

It is known to cause errors in on Ma- and the shifts in the event of equality

gnetband recorded data blocks the parallel of the register contents terminated, with the position

recorded bits of each character by a pari- des binary 1-bits in the first shift register the

ity bit for odd or even numbers to 15 indicates faulty data track and the data

supplement (vertical redundancy) and at the end of the block the receive register with a new check

Data blocks to record a check character, through the vertical redundancy function and at

that the number of bits in each data track within an error detection a correction of the error

Odd or even blocks adhere to bits by linking what has been read

is supplemented (longitudinal redundancy). 30 characters and the content of the first return

In this way, error detection is made possible in the shift register coupled to the non-equivalence light. It is also known to have an effective fault-causing effect
recognition by ensuring that each

Character a certain number of binary 1-bits Developments of the invention are in the sub-items. 25 addresses marked. The following will be

For the purpose of error correction, it is necessary to use the drawings

Lich, that not only wrote the presence of an error. The drawings show in

is determined, but the error is localized and Fig. 1 shows the block diagram of the circuit arrangement

can then be corrected. for error detection and correction,

If the error is localized, the correction 30 Fig. 2 can be a detailed block diagram of the circuit

by inversion of the erroneous bit. processing arrangement according to Fig. 1,

Known circuit arrangements for errors - Fig. 3 A and 3B the test circuit for the correction, which use the longitudinal redundancy to tikal redundancy, in the following briefly as vertical one Incorrect bit position in a character of a redundancy check circuit or VRP circuit be data block have the disadvantage that 35 draws,

with the help of the longitudinal redundancy only about 50% of all FIGS. 4A and 4B comparison circuits,

possible errors that occur in a data block Fig. 5A and 5B the register for checking the

can be recognized. This disadvantage is caused by cyclic redundancy, hereinafter referred to as

the circuit arrangement according to the invention wide-cyclical redundancy test register or ZRP register

avoided, as the use of three denotes 40,

according to different mathematical laws - Fig. 6 A and 6 B the error pattern register, im

the ability of calculated test characters to be referred to below as the FM register for short,

exposed to about 95%. The circuit F i g. 7 the circuit for switching the on

arrangement according to the invention is characterized gears of the error pattern register for reading select

by 45 rend of the tape rewind,

..., - /. _x , ·, Fig. 8 the circuit for checking the content

a) eme with the receive register is connected to _{one Regist} e _rs testing the longitudinal redundancy, known per se circuit for testing the _dag ^ f £ _{FTIR the} ^ _{2 as a} longitudinal redundancy Prüfyertikal redundancy that upon detection of a _re ^ _{gter od} for _LRP . _Register is designated,
Error em binary 1-bit a first jerk- *. _{p the switching} £ _{mr the} bit pattern control, coupled η-stage shift register with only _p . * _{1Q a ΖΚΡ} . _κ ^ _{δΐ6Γ FTIR} 7 bits without internal zufuhrt a data input, the outputs _R f _{O {ick} pp _lun g _Sver bindimgen,

both with a group of antivalence members _p . ^ ^ _Failure ermusterregister for 7 bits without

_{and internal} feedback connections with the inputs of the receive register,

as well as about the group of antivalence members _p . ^ ^ / ^^^ of a data block, des

with a second feedback / z-stage _ZRP . | _{eicliens and the L} RP sign on one

Shift register connected smd, its off magnetic tape

also go to the antivalence elements and *? _{13 em R (} ^ _{ster mr g B {tg} ^ ^ _{6n back} _

a circuit for Bitmusterkontrolle drove _k opplungsverbmdungen _and

and its content simultaneously with the content _6o gi J _{4 a Fe} Mermusterregister for 9 bits with the first shift register after receiving ^^ feedback connections,
ernes sign jeweds shifted one step ^ _{the p} . On which the data bits is referred to a polymer formed from the received data checking _Zeicne ^ _{G s B} ^ _e ^^ _{the au z} S _geneil lines Verwird and after reading a data block an _b indungsleiringen represents, parallel super-character for the cyclic redundancy contains , ^ ^ _n ^ _{d trageQ riche} it _en lines encryption

b) a control unit, which via control lines a connecting lines on which control signals are transmitted Comparison of the contents of the two can be fed back. A number in square brackets next to one th shift register after reading a data- dashed line indicates the number of each other

3 4

independent connecting lines that go through several of them are in the course of the description

the dashed line will be shown. mentioned.

In Figs. 3 to 9, the symbol - [> means The write operation takes place in two steps. The one input or the symbol [> - at an output First step consists of writing the data path, that one from the left one with one or 5 bit groups, which are referred to as bytes. the the other of the symbols provided with data is received from a tape control unit Signal is inverted before it is sent to the right and transferred from there byte by byte to the tape, is transmitted further. Each byte has a parity bit for error detection

A circle added to an input or output line. Other methods of writing

(O- or -O) ^a Fig ^for denotes a control io characters that a redundancy for error detection

lines that have control signals to or from the control unit are suitable; z. B. each byte can have a

transmission. contain predetermined number of ones and zeros. Each from read-write register 24 to

I. General description of the error detection tape device transmitted characters is also the

and error correction * 5 ZRP register 22 (Fig. 2) supplied. In this register the data are entered in such a way that they

F i g. 1 shows the general circuit arrangement with the current content of the register in FIG

for error detection and correction. The data are linked to a group of antivalence folds

which can be moved by a bus line 12 for data entry and by one place. Fig. 10

recorded. The data blocks are in the same size and 13 represent a ZRP register in simplified

Sub-blocks, e.g. bytes, subdivided. A partial block diagram is shown. The register 13 has back

Test circuit 14 generates an output signal when coupling connections are open so that the content is selected.

it is determined that a sub-block can be modified due to an error in the shifts,

that has vertical redundancy. Each sub-block ZRP register 22 is shown in FIGS. 5A and 5B

is recorded with redundancy in such a way that it is shown in detail when it is recorded. When receiving the last

if an error occurs, the test circuit 14 fixes this byte of a data block in the tape control unit

represents. The error display is identified with the FM - this is used both for the tape device and for the

Neten error pattern register 15 supplied. The data ZRP register 22 is forwarded. Then with the

itself the register labeled ZRP 13 contents of the ZRP register 22 an additional ver

for checking the cyclical redundancy. 30 shift carried out. Then the content of the

After reading a complete data block ZRP register 22 to read-write register 24

a test character is transmitted, the so-called cyclical transmission, which is achieved by a control signal from the control

Redundancy test characters or ZRP characters, to which circuit 29 is effected. It happens like this

Bus 12 for data entry. This will ensure that the content of certain bit positions of the ZRP register

is checked by the sub-block test circuit 14 and also complemented 35 sters. Then the content of the

to the register, which checks the cyclical redundancy, read-write register as ZRP check byte on tape

13 transferred. Written after receiving the data block. This will ensure that the

and the test mark can now be the digital longitudinal redundancy test mark LRP, which is after the

equal circuit 16, the input signals are recorded from both ZRP characters, an odd one

which the cyclic redundancy checking register 13 40 has tical redundancy. It cannot do that

as well as from the error pattern register IS, it should happen that the LRP character is louder

determine the location of the error in the sub-block. Your zeros exist. Such a sign that

Output signal is the circuit 17 for display reading backwards forms the first character, namely would

fed to the fault location in a sub-block. for magnetic recording according to the so-called

For the described embodiment according to 45 th NRZI method, in which only the binary digit 1 F i g. 2, a sub-block consists of 9 bits that form a byte by changing the magnetic flux. The sub-block test circuit VRP 21 is one that is not recognized.
Parity check circuit. The ZRP register 22 and the FM register 23 after the previously mentioned complementing are shift registers with feedback of certain bit positions of the ZRP register, the content connections. The data input and output of the read-write register as ZRP check byte follows via the read-write register 24. The digital tape is written after the end of the data comparison circuit is reached by a group of blocks (see Fig. 12). Another test antivalence elements 25 are formed. This is used in conjunction with control signals as the longitudinal redundancy test character LRP , which denotes the content, is after the ZRP byte (FIG. 12) of the ZRP register during the test time for the 55 on written the tape.

Move errors in a sub-block. In this The longitudinal redundancy test mark LRP has the

Case, the circuit shows the point of failure in the part- the following property: It ensures that in each

block on. Trace an even number of ones onto the tape

is written. For example, the fourth bit is

Control of a magnetic tape with error correction 60 of the LRP character selected so that in the entire block

an even number of ones in the fourth track

The following paragraphs describe which errors are included. The LRP mark is used all over correction on a magnetic tape and record on recorded block including the written fig. 2 reference. Writing, reading and ZRP bytes are calculated. The conversion to read described with correction. Then matched bits of the ZRP character are used when it is converted of these basic operations for the return to the read-write register in their complete reading described. There are several ways to want an odd parity for the LRP byte opportunities to implement these modifications and ensure. This property is during the

5 6

Backward reading advantageous. How this is achieved The read operation is carried out as follows

will be discussed later in a separate section about the leads: The tape begins on the basis of a read command

The mode of operation of the shift register is described. to run. The data read from the tape arrive

A write delay device initiates from the tape unit into the tape control unit

the tape unit, between the check bytes and the 5 and become the read-write register 24 (Fig. 2)

last data byte in the block a larger transfer. From this register they are accessed via the

stood as the normal from the write clock generator group of antivalence elements 25 to the ZRP regi-

to insert controlled byte spacing. transfer 22 as it is also done when writing

. . is happening. The vertical redundancy for the data

Checking the write operation ₁₀ ^ _n J _{calculated by the} VRP circuit 21. if

by subsequent reading it is calculated that the data is incorrect

The selected tape unit writes bytes with a one in another register, namely in the

the print head. While the tape moves from the error pattern register 23, briefly called the FM register 23,

Write head away and past the read head, draws, inserted. The error pattern register 23

If the tape unit reads a prerecorded byte 15, it is the same as the ZRP register 22 except that

and transmits it to the tape control input for testing- there is only one input for one in reading or

Ness. This examines every normal input byte writing by checking the vertical redundancy.

out of the tape unit to determine: has detected errors. Simplified block diagram

,,. ,, ,, ,,,., Positions of a ZRP register and an FM register

_{1. whether the 20 sters} recorded on the magnetic tape show Fig. _lo and 11. The FM register is data have a sufficient strength to be read at the same time Multiplexer scho pateren with the CRC register read operations to _{ben The} displacement is carried out by both the shift MAY, signals from the control unit 29th

2. Whether each byte is odd or even. ^If an error in the vertical redundancy contains the number of bits and whether the number of bits ^a 5 is determined by the circuit 21, an error with the state of the flip-flop for the odd signal is generated by the control unit 29 central data redundancy matches, processing unit sent.

Any character or byte of data read from the tape

3. Whether distance errors (misalignment error) when activating a read clock generator and will have occurred under the drawing of the byte, ₃₀ control of read clock pulses is transferred. To

4. Whether the bit structure for the check bytes of the block of the read operation is the read clock is reversed. When the tape unit sets the check bytes and transmits a delay counter in the control switch to the tape control unit, the ^ f ²⁹ must be switched on. These delay counter bytes correspond to the provisions which are jerked by the tape control unit (LRP and ZRP registers) M every time a data byte is read and set back in motion. When the payer has been calculated. ^{would like to be reset by the} following data byte,

it reaches the counter reading 36. This is

The selected tape unit therefore writes every thing that, as can be seen from FIG. 12, the byte received from the tape control unit on ZRP characters not directly, but only on magnetic tape. During the same block write 4 ° the last character operation is followed by a predetermined distance, but in a separate check operation of a data block. After this has been reached, the tape unit reads each counter reading 36 written shortly before, becomes a byte of the first check character and transmits the data to the tape control unit to the interlocking circuit in the control unit. The tape controller checks every byte from 29 on. If this interlock switch of the tape unit is turned on in response to recording errors, it is assumed that this may have occurred in the block. The tape next 2x1 reading byte is the ZRP character. The control unit sends the data to the tape unit, entering the ZRP character in the register 24 so that a data block is recorded and, like the data fed to the ZRP register, performs a test operation on the data at the same time. The vertical redundancy of this But, um, within the block that the tape unit has already written 50, as already mentioned earlier, the sign is a not out of pure NuI-before. len existing longitudinal redundancy test mark LRP

Data is read into the tape by a magnetic head, possibly different from the one for the control unit, and the block is transferred to the data. Therefore, the vertical redundancy check vertical redundancy VR and longitudinal redundancy of the LRP character is checked by a signal from the danz LR. The LRP character is modified in the LRP 55 control circuit 29 so that this possible register 26 is calculated. If is taken into account according to the block writing. The ZRP character will not operate an error in the vertical redundancy is transmitted to the central data processing unit, or if an error has been detected shortly thereafter, the delay counter delivers a longitudinal redundancy through the circuit 27 to the Kon pulse 96, and a dem The second check character is applied to the content of the LRP register, hereinafter referred to as 60 interlocking circuit in the control unit, briefly referred to as LRP interrogation circuit 27, is permanently switched on. It is assumed that this has been set if an error signal is issued about the next character received is the LRP character. This character is not sent to the ZRP register and informs it that the write operation is sending, and it is also not sent to the central unit that has not been carried out properly. Transferred to 65 processing unit. In this way, several bytes of information are now sent to an LRP register. This is the end of the ZRP byte and an LRP byte, written on normal read tape. Now the LRP will become as shown in FIG. ster by the LRP interrogation circuit27 for errors

7 8

queried and the ZRP register is attempted through the door. This is done by the interconnection 28 for bit pattern control, hereinafter referred to as a plurality of control interlocking circuits, briefly referred to as bit pattern control circuit 28, and an interlock circuit for the vertical 5, a special interlock circuit (track search redundancy check in the control circuit 29 is interlock circuit) in the control unit 29 is interrogated to determine whether this is set when reading. The contents of the FM register and the ZRP block, an error in the vertical redundancy register, are recorded. At the beginning of the next step is. If such errors have occurred, data blocks read for error correction are sent by the control unit 29 to reset an error signal to the read / write register 24, and the content of the central data processing unit is sent. If an error occurred, the ZRP registers contain, and a one is in the highest position of the ster 22 and the FM register 23 is a pattern of one FM registers from the Control unit 29 feed and zeros, the sequence of which occurred. After that, the ZRP register and that corresponds to an error. With these registers, 15 FM registers are simultaneously shifted. After it is possible to determine the track in which the error occurred, the content of the ZRP will be used for each position shift. The normal way of working consists in comparing the register bit by bit with the contents of the read / write register on the tape by the length of the block just read. Reset the comparison and read it again, and by entering the contents of the ZRP register 22 characters, for which the vertical redundancy check ao in the group of non-equivalence elements 25. Correct the errors by changing the - Output signals of the antivalence elements 25 go to that bit in the erroneous characters complement bit pattern control circuit 28 that generates an output signal that corresponds to the track in which the error was detected when the content of the ZRP register is the . The point in time at which the faulty and the content of the read-write register 24 bits for stuck track is determined lies somewhere in which 25 bits match. If there is an exact coincidence period, which exists through the completion of the read operation, the so-called correction lock for the first block and the reception of data is switched on in the control unit 29 during the next read operation. and the sliding process ends. Then the in-case shows the arrangement according to FIG. 2, the FM register receives the faulty track, including the faulty track before the start of the position of the individual 1-bit in the FM register of the second read operation during the time in which. The ZRP register is deleted,
the tape experiences an acceleration in order to read the block again. The data block can now be reread. The process could also go astray. Data will now be changed as with the normal going, that the calculation of the read operation is carried out under the control of the read clock error-prone track at the end of the first read operator in the read-write register 24, and the result obtained, However, if there is an error in a data byte in the erroneous track, the error is saved. If the vertical redundancy is found, the bit that corresponds to the result in the central data processing unit corresponding to the track that would be stored as faulty by the FM register if the circuit for the detection could be indicated as defective is complemented. This happens in connection with the faulty track in connection with other 40 as follows: The outputs of the VRP register tape devices and / or other records on 21 and the FM register 23 are connected to the non-equivalents of the same tape device before attempting to link 25. Since the FM register becomes only one, to correct the error in the original record one in the one corresponding to the faulty track. If the original faulty location contains the same output signals as the previous recording is to be corrected, 45 valence elements 25 could be transmitted back to the input signals with the exception of the display of the faulty track to one of the output signals of that non-equivalence element, additional tape device, namely that of the faulty track Track corresponds to and this from together with further information, through which the FM register was supplied with a one. The bit of the read belonging to the faulty track that has been switched to error correction by the additional device is used. The storage of the display of the error-prone write register is complemented. The corrected track could also be made in the tape control unit in yawed bytes to the central processing unit in a special memory. The central data and to the ZRP register 22 are transferred. In spite of this, the processing unit would then have to give special commands to the contents of the LRP register which are not corrected in order to prevent the erroneous data from being read again.

Record the information about the faulty 55 After all the data of the tape block has been read

removed trace from the memory. The Er- also read the ZRP sign. Its vertical redundancy

The calculation of the faulty track can also be different from that of the data. she is

at the end of the tape reset or during, however, predictable. The ZRP character becomes

of a special cycle between two operations ZRP register 22, but not for central data transfer

take place. 60 processing unit transferred. Then the LRP

In the example shown in FIG. 2 characters are stored in the LRP register 26, but not in the

Information about a faulty track is transferred to ZRP register 22. This is the end of the

left if the correction cycle is not immediately in the reading process with correction cycle. Now is the time

Is attacked. That means querying the operations for errors. The ZRP register is through

must have the following sequence: The recording 65 interrogated the bit pattern control circuit 28 to

The information is read and the error is detected, it detects that it does not correspond to an error

follows the reset of the tape, and then has a bit pattern. The LRP register is through

Read operation carried out in which the error correction interrogated the LRP interrogation circuit 27 in order to

909 503/1558

9 10

see that it only contains zeros with the possible highest digits now leading to the lowest exception of the digit in which the error correction takes place, and vice versa. It is very important that this should follow. This is done by blocking the query ZRP register itself must be symmetrical, ie that the position that corresponds to the track calculated as faulty, the feedback connections symmetrically around the (result contained in FM register 23). 5 are arranged around the middle of the register.
If an error is displayed, an error signal is sent to the input lines of the ZRP register, which is a

is via the control unit 29 to the central data processing shift register, are in Fi g. 5 A and 5 B with one processing unit sent. Circuit arrangement for switching the input

There are several exceptions to the general lines shown. When this switchover works. There is an exception, if io follows, it must also be possible to calculate the Leitunkeine track as faulty for the error correction. gen at the output of the FM register toggled. One possibility for this is that eight digits differ. This is shown in FIG. 8. The reason for this is, exercises take place without a match that when comparing the content of the FM register between the content of the ZRP register and the content of the ZRP register, the number of stops of the read / write register, that at this time - 15 shifting operations, which are necessary in order to obtain a match point, the previous content of the FM register on - tuning to the tracks after which has been taken, is achieved. Another possibility of switching the input line assigned to them is that the ZRP register refers to the opposite and not in the manner in which it neither contains all zeros nor has a special track with the central data processing unit. In these two cases is when the ao are connected. Therefore, in order to correct an error in the rich content of the ZRP register is shifted to the current track, the output line contents after the location shift must be identical to the gen of the FM register as well as the input line and the previous content. That is, if the ZRP register is switched over when there are louder genes.
Zeros a shift takes place after the Another important factor in backwards

Shift is all zeros again, and read 35 is the correct formation of the check character. Since that if the other special content is shifted LRP characters are not sent into the ZRP register If he is identical to himself before the shift, one must know which of the reception. Under these circumstances, no trace genes become the LRP sign and whichever the attempted calculation. If no faulty track is a ZRP character. If only one certification mark at a time is calculated, the ZRP register and the 30 is received, this is difficult. Therefore is for it FM register cleared, and the read process ensures that the LRP character will never be safe like normal reading, i.e. That is, the vertical line consists of all zeros. For this purpose, the Errors found in the redundancy check are included in the veriikal redundancy of the ZRP character during the FM register and the data in the ZRP register have been changed in a write operation. Hence the LRP-led. Of course, no correction is made here. When returning, reading the LRP character is read first.

The one with the two test characters, the ZRP character It is not entered in the ZRP register, and the tape described by the LRP character could rend all other characters in the ZRP register supernaturally cannot be entered for error correction on one. While reading backwards it is directed tape controller. While 40 possible, the vertical redundancy of the ZRP character the checkmark read time would predict both checkmarks. This must therefore either from the entered into the LRP register, but the information central data processing unit or from the tion of the ZRP mark was disregarded. If memories are supplied in the tape controller, the time allotted for entering the test characters or the vertical redundancy of this character long enough to enter the ZRP character and 45 not queried. With the present execution If there is an LRP mark in the additional device, an example is the last-mentioned measure has been hit between ligaments with and without. Reading backwards is like the pre-recorded one ZRP sign. reading the other way round, apart from these special

There is a tape read operation called reverse turns. Since the ZRP character is not known to read errors. The tape in which the 50 is asked if it is not possible to read in reverse direction is read in the opposite direction. lent to correct errors occurring in the ZRP character. In this case, the test characters are placed first. If the vertical redundancy of the ZRP-sen and then the data that were known in the reverse character were known, it would be possible for an incorrect spelling sequence to appear. To correct the error in the ZRP character outlined above,
Correction scheme works when reading backwards 55 After a backwards reading operation, in which errors are about the same as with normal reading. However, there are several special cases to be taken into account. port operation performed. It is not read.

First, since the data must be calculated during the normal At the beginning of the next backward read operation, read and write operations are calculated in a particular track with errors. In the direction read in the ZRP register and adjust 6Fo data an error correction is attempted,
This general method of operation can be broken down into

read backwards. This can be done in different ways. A possibility in that when reading backwards the shift would be when finding an error during a ZRP register contents opposite to the normal backward read operation, the correction is automatic Slide direction takes place. Another possibility to read out 65 during the next forward read operation Achieving the same result is what will take in. Another would be several types the ZRP register leading data lines in order to provide commands such as z. B. a normal switch on that those who normally enter the read command and a command "read with correction".

In this case the central data processing unit would give a normal read command until an error is detected. Then that would make the mistake containing trace determined. The next time the central data processing unit would do one Give the command "Read with correction" and the data in the block would be corrected in the calculated track.

The shift register used in the embodiment described here is one of a class of possible circuits that can perform the same operation. These circuits must meet the following important conditions: First: They must be linear, ie if a data record A is fed to the circuit, its content can be designated with F (A) after it has been entered. When entering a data set JS into the circuit, its content can be designated with F (B) after the entry. If A and B, the data, are now modulo-2-added bit by bit and input into the circuit, the content of the circuit is denoted by F (A ή; B) . The circuit is linear if F (A) φ F (B) equals F (AfB) , where the symbol =) = stands for a bitwise addition modulo 2. The second condition is: The circuit must be constructed in such a way that during at least nine shifts (or a number of shifts equal to the number of tracks) the content of the circuit is different after each shift. The third condition is: In order to achieve a match when comparing the content of the FM register with the content of the ZRP register by shifting the positions, it is necessary that when a pattern is entered at one input of the circuit, its content is the same as whether the same pattern had been fed to a different input of the circuit and several additional position shifts had been made. The fourth condition is: For backward reading, the vertical redundancy of the test character should be predictable if possible. The last condition is: For backward reading, the circuit should be constructed as symmetrically as possible.

One group of circuits that meet all of these requirements are linear shift registers with feedback. Polynomials are typically used to describe feedback shift registers. If a coefficient of the polynomial is equal to one, the shift register has a feedback connection at the corresponding point. If the polynomial cannot be broken down into a product of smaller polynomials, there is only one pattern (namely all zeros) that will be the same if it is shifted once. If a polynomial contains the factor 1 + X , a pattern of ones and zeros is created that remains unchanged when the position is shifted, and the vertical redundancy of the check character can be calculated. If the polynomial is self-reciprocal, ie if it is the same when the coefficients are exchanged (the highest with the lowest), the associated shift register is constructed symmetrically. For the embodiment shown here, one of the 8th degree polynomials was multiplied by 1 + X. The polynomial chosen was self-reciprocal. Of course, other polynomials could have been chosen. Although a particular type of shift register is shown here, there are several other possibilities including the use of delay lines and the use of special follower circuits that meet all of the above conditions.

If the polynomial describing the ZRP shift register can be broken down into a factor (1 + X) and another polynomial, a pattern of ones and zeros is created that remains unchanged when the position is shifted. For the shift register of FIG. The pattern 13 is 111010111. This pattern is important for two reasons. Firstly, it must be recognized when an attempt is made to compare the contents of the FM register and the ZRP register, so that a comparison is not made incorrectly with regard to the first track. Second, this pattern can be used to change the vertical redundancy of the ZRP character. This is done by writing the ZRP character as it has been calculated, with the exception that those places in which this special character contains ones are complemented. Since the number of ones is odd, this changes the vertical redundancy of the ZRP character. If this character is reintroduced, the ZRP register would normally go into the state in which it contains "all zeros". However, since these specific positions of the check character have been complemented, the ZRP register finally contains this pattern of ones and zeros when reading without errors. This makes it possible to write the ZRP character with the desired redundancy. To calculate the vertical redundancy of the character, refer to the following table:

redundancy
of the block number
of bytes
in the block Vertical parity
of
ZRP character Vertical parity
of
LRP mark Vertical parity
of the ZRP mark
after
Complement
in selected
Place Vertical parity
of the new
LRP mark just
just
odd
odd just
odd
just
odd just
just
just
odd just
just
just
just odd
odd
odd
just odd
odd
odd
odd

In order to ensure that it works properly. Moving is no longer done in the

perform, there is a correct sequence for every written character, and in this case there is one

Shift necessary when reading. If for any correction impossible. Therefore this must be avoided

Basically a character is completely lost, i.e. H. will. One way is to use all characters

is not read at all, there is no shift to write with even parity and that more

Do not allow existing zeros. Another solution is to automatically postpone it when it appears that a draw has been lost. This can be done in different ways Way done. For example, a special shift command can be given when a Delay counter, which is switched on after each read clock cycle, over a certain one Point, e.g. B. 16, got out and the read clock

If an odd redundancy toggle is set and a two-byte (plus one check byte) block is written to tape, the second byte resets the character count toggle, showing that there was an even number of bytes in the Block stands. If the bit structure of the first decimally encrypted character is 7, 6, 5, 4, 3, 2, P and of the second character 7, 5, 3, the check byte has the

encoder is triggered again. This would result in bit structure 6, 4, 2 and P. Because the toggle switch occurs when more than one whole character time is set to "Odd parity", the first ones will

would have been deleted without a sign appearing. That is, there will be a special shift inserted where a character is likely to be missing.

II. Circuits for error detection and correction

a) Non-cyclical error detection

Checked both bytes in the block for odd parity. The character count toggle is in the OFF state, when the check byte is transferred to the tape controller and therefore examines the VRP circuit the check byte for even parity.

If the toggle switch »Odd redundancy« is set and one of three bytes (plus check byte) If an existing block is written to tape, in the embodiment 20 described here, the third byte brings the character count toggle again is used for non-cyclical error detection in the setting state and thereby indicates that made by an odd number of in front of the test mark

,. ,.,,.,. ,, ". ,,, sign is. If the bit structures are binary

1. a bistable flip-flop for payment, whether _{decimally encrypted} characters 7, 6, 5, 4, 3, 2, P; the number of characters is even or odd; you _{25? 5} 3 _{and? 5 4 loudly, the ? Lüfbyte has the bit} . is used below as the number of characters flip-flop _{structure? j} ^ ^ _{2> p The first three charactersQ des}

blocks are checked for odd parity. because

2. a longitudinal predundancy test (LRP), the character count toggle is set when

3. a vertical redundancy check (VRP) for ^the check byte is transmitted to the tape control unit, data items ³ ° the VRP circuit ^{examines the check byte}

odd parity.

A byte in the command word indicates that the tape control unit examines the bits of the

■ Magnetic tape bytes to be recorded with odd check bytes for a parity error, but the state or even parity should be written. the toggle switch shows "Odd Redundancy" If the byte of the command word is odd 35 does not necessarily indicate whether the check byte is odd Parity specified will contain a toggle switch or an even number of bits. "Odd redundancy" at the beginning of the write Before setting one assigned to the check byte operation discontinued. The vertical redundancy flip-flop circuit, briefly known as the test byte flip-flop circuit Test circuit (VRP circuit) examines the bit-referred to, causes each input character to be taken out structure of the 40 of the tape unit stored in the read-write register, a change of state of the bistable Bytes. If a byte in the read-write register is a character count toggle. If the block is a contains an odd number of bits and therefore contains the flip-even number of correct characters circuit "odd redundancy" reset, the last correct character in the block is the toggle or if the byte is an even number of bits decremented back; if the block is an odd holds and the toggle "Odd Redundancy" contains 45 number of correct characters, brings the last one is set, the tape controller inserts a correct character check bit in the block the flip-flop in (P-bit) for the character transmitted to the tape unit. the setting status. If the character counting toggle " ^. ,. ,. ,,,., .. ,, ". ,, turned off when in the reset state

1. T _he bistable flip-flop Zeichenzähl _the tape control unit receives the check byte must

The character count toggle, which in the 50 the check byte contain an even number of bits. Control circuit 29 (Fig. 2) determines whether, if the character count toggle is in setting Tape block before the check byte is an odd or state, if the tape controller has the has an even number of bytes. Received in all check bytes determines the state of the toggle read cycles with the exception of the "Odd redundancy" circuit of the check byte, whether the check byte The bistable character counting toggle 55 is initiated with an odd or an even number of bits

circuit is actuated and changes its state. If the flip-flop is in the reset (OFF) state, when the tape controller receives the check byte (indicating that an even number of bytes are prior the check byte), the VRP circuit examines the check byte for even parity. If the counting toggle is in the set (ON) state when the tape controller receives the check byte

should contain.

2. Longitudinal redundancy check register
(LRP register)

The LRP register contains nine flip-flops
(P and 0 through T), one for each of nine tape tracks. The LRP register checks each complete
Tape block.

1-bits entered into the LRP register cause

receives (which indicates that a

odd number of bytes stands), the 65 examines that the output potentials of the corresponding

VRP circuit sets the check byte to odd parity. bistable flip-flops of the LRP register the

This process will assume the opposite state (rise or

illustrated. fall; the first 1 bit at the P input represents the toggle

circuit F on; the next 1-bit at the P input resets the flip-flop P , etc.). After the tape controller has processed the LRP byte, all flip-flops in the LRP register must be in the reset state. An output from any flip-flop of the LRP register at the end of the operation indicates an error and causes error and data check flip-flops to be turned on.

3. Vertical redundancy checking circuit
(VRP circuit)

During read and write operations, bytes contained in the read-write register become the VRP circuit transferred, but the byte in the read-write register can only have a Contains errors related to vertical redundancy. The VRP circuits determine whether the byte is a contains odd or even number of bits.

The tape operation command states that bytes transferred to and from the tape unit are either an odd number of bits (odd parity) or an even number of bits (even parity) must contain. If the command for the tape operation indicates odd parity, press the Belt control unit a toggle "Odd redundancy" in control circuit 29. All at the Execution of the command bytes read from tape except for the check byte must be odd Number of bits included. If the command for the tape operation does not cause the tape controller to use the To set the toggle switch »Odd redundancy«, all bytes read from the tape except of the check byte contain an even number of bits.

On a write operation, the tape controller brings Flip-flops of the VRP circuit and the data test circuits in the setting state, if

1. The toggle "Odd Redundancy" is activated and it is determined that any Byte contains an even number of bits with the exception of the check byte,

2. the toggle switch "odd redundancy" has not been set and it is determined that any byte other than the check byte contains an odd number of bits.

During a read operation, the tape controller only brings the flip-flop for the vertical redundancy check in the setting state to indicate a parity error.

If bits when transferring a byte from the selected tape unit to the tape control unit are lost, the VRP circuits display an error only if an odd number of Bits failed.

During a write operation, the flip-flop circuit P of the read-write register is not used, because the data register does not transfer the parity bit of a byte to the read-write register. The belt control unit compares the result of the vertical redundancy check with the status of the Toggle switch »Odd redundancy«. When the VRP circuits determine that the byte is in the read-write register contains an odd number of bits (excluding the parity bit), and the The toggle "Odd redundancy" is not activated, the tape control unit adds a "1" as a parity bit to the byte transmitted to the tape unit. If the byte in the read-write register contains an odd number of bits and the flip-flop "Odd redundancy" is activated, the tape control unit transfers the byte in the read-write register to the tape unit with a "0" as the parity bit. The data register can contain odd bytes or even parity to the read-write register

ίο transmitted, but the byte that the tape controller transmits to the tape unit, must have the parity that the toggle switch "Odd Redundancy" indicates.

b) Cyclical error detection

1. Description

the cyclical data error detection

The ZRP register can be used for error detection. That is done by while writing the ZRP character is written during the recording. When reading the recording, the ZRP characters read. If the read ZRP character does not match the one calculated when reading the data ZRP characters, an error is detected. The following is a description of the mode of operation of the ZRP register when it is used to calculate the ZRP character.

The mode of operation of the ZRP register is the same for reading and writing with the exception that A check character is written at the end of the write process and the ZRP register at the end of the read process is queried for errors. The ZRP register is shown in FIGS. 5 A and 5 B and the F i g. 13th shown. It contains nine flip-flops.

When the + shift ZRPR line is energized (this line enters at the top left of Figure 5A), the output of the exclusive OR circuit CA is applied to the flip-flop AA. This is done via two AND circuits DA and EB. The + shiftZRPR line leads to these two AND circuits. The output signal of the antivalence element CA goes directly to the AND circuit DA and to the setting input of the flip-flop. If the output signal of the antivalence element CA were a "1", the flip-flop would therefore be set. If the output signal of the exclusive OR element CA were a "0", it would be inverted by the inverter DB , and when the signal + shiftZRPR occurs, the two inputs of the AND circuit EB would be energized, this AND circuit would generate an output signal and the flip- Flop AA would be reset to the null state. Each of the 9 bits in the shift register is treated in the same way. One input signal for the exclusive OR circuit CA is the + ZRPR P-bit, the other the output signal of an OR circuit BA. If the output signal of BA is a "0", the output signal of the antivalence element CA is exactly the input signal marked + ZRPR P-Bit. That is, when a shift signal occurs, the ZRPR P-bit signal passes through the exclusive OR element CA, the output signal of which is then exactly the same ZRPR P-bit . This runs through the two AND circuits DA and EB. You set the flip-flop on or off, depending on whether a "1" or a "0" was present on the ZRPR P-bit line. The relationships for the 6-bit are almost identical, only the line ZRPR 1-bit takes the place of the line P-bit.

909 503/1558

If, therefore, all zeros are present as output signals of the OR gates BA, BB, BC, BD, BE, BF, BG and BH when a shift signal occurs, the content of the flip-flops is shifted down one place. That means that the content of the lowest flip-flop for the P-bit goes into the flip-flop for the 7-bit, the content of this flip-flop, i.e. the flip-flop AA, is shifted to the flip-flop AB, which is the flip-flop for the 6-bit, the content of this flip-flop is shifted to the flip-flop AC for the 5-bit, but there is a small change to the flip-flop for the 4-bit. The setting output of the flip-flop AC is, as with the stages of the ZRP register described above, connected to one input of an antivalence element CE. Their second input is not directly connected to the output of an OR circuit, but to the output of a further exclusive OR element CD , one input with the setting output of the flip-flop for the P-bit and the other input with the output of a OR circuit BD is connected (inner feedback connection of the shift register). It is assumed again that the output signal of the OR circuit BD is a "0". The output signal of the exclusive OR element CD is then the ZRPR P-bit. This reaches the antivalence element CE, into which the + ZRPR 5-bit of the flip-flop AC is also introduced. The output signal is the non-equivalence function of the P-bit and the 5-bit. The shift pulse + shiftZRPR reaches the AND circuits DG and EH. As you can see, this arrangement of AND circuits is the same as that described for the 7-bit, because if the output signal of the antivalence element CE is a "1", the "1" goes to the AND circuit DG, and when the Shift pulse the flip-flop AD is set. If, on the other hand, the output signal of the exclusive OR element CE is a "0", this is reversed by the inverter DH. The AND circuit EH is prepared, and when the shift pulse occurs, the flip-flop / iD is reset. The flip-flops AE, AF and AG for the 3-bit, the 2-bit and the 1-bit work in the same way. Fig. 13 shows the general feedback circuit, showing the feedback connections without reference to the detailed arrangement.

The mode of operation of the shift register just described applies in the event that no data input signal is present. When a data input signal is present, the + forward line in FIG. 5A or the + reverse line in FIG. 5A is energized. The + Forward line is energized when the tape unit is traveling in the forward direction. At the time the + shift ZRPR line is energized, there may be data on the bus known as the read line. Nine such lines are shown in Figures 5A and 5B. Let us consider one of these lines, namely the line that is labeled + read line 1-bit. It leads to the line + forward zxl of the AND circuit AA. The output signal of this AND circuit is a "1" if there was a "1" on the line + read line 7-bit , and an "ö" if there was a "0" on the line. At this point in time, the line labeled + Reverse contains a "0", so that the output signal of the AND circuit AB is a "0". The output signal of the OR circuit BA corresponds exactly to the output signal of the AND circuit AA. The output of the OR circuit BA is connected to one input of the antivalence element CA mentioned earlier. The output signal of the antivalence element CA is the antivalence function of the + ZRPR P-bit and the signal on the line + reading line7-bit. When the line + shift ZRPR is energized, the flip-flop AA is set in the state which corresponds to the output signal of the exclusive OR element CA , as described above. The same applies to the flip-flops assigned to the 6-bit, 5-bit, O-bit and P-bit. The feedback stages assigned to the 4-bit, 3-bit, 2-bit and 1-bit are slightly modified. As an example, consider the stage assigned to the 4-bit. When the + forward line is energized, the inputs to AND gate ^ G are the + forward signal and the + read line 4-bit signal. Since the + forward line is energized, the + reverse line is ineffective, and the input signal of the AND circuit AH is a "0", so that the output signal of the OR circuit BD is equal to the output signal of the AND circuit AG. This arrives at the antivalence element CD. The output signal of this circuit is the non-equivalence function of the + ZRPR P-bit and the signal on the line + read line 4-bit. This output signal is fed to the antivalence element CE. The output signal of this circuit is now the antivalence function of the + ZRPR 5-bit and the + ZRPR P-bit. When the + shift ZRPR line is energized, this output goes into the flip-flop AD as described above. The 3-bit, 2-bit and 1-bit flip-flops work in the same way. It has now been described how the ZRPR operates in the presence of data input signals while the tape is moving forward.

During the backward movement, the mode of operation is almost identical to that of the forward movement, only the stage assigned to the 7-bit receives the ZRPR the signal on the line + read line P-bit via the AND circuit AB, the stage assigned to the 6-bit receives the Input signal via the line + read line O-bit, the stage assigned to the 5-bit via the line + read line 1-bit , etc. This is an interchange of the input signals that is necessary to carry out error detection during backward reading.

To illustrate how the ZRPR works , reference is made to Tables 1 to 6 below, which are used to describe the ZRP operation and the LRP operation.

Ten. 1 Table 1 Ten. 3 Ten. 4th Ten. 5 1 (Five data characters) 0 0 0 Bit no. 1 Ten. 2 0 0 1 7th 0 6th 0

Continuation of the table

Bit no. Ten. 1 Ten. 2 Ten. 3 Ten. 4th Ten. 5 5 O 1 1 O O 4th O O O 1 1 3 O 1 1 1 O 2 O O O 1 1 T-H O 1 O 1 1 O 1 1 1 1 1 P. O 1 O O O

Table 2 (ZRPR content after adding the data from Table 1)

Bit no. At first Ten. 1 Ten. 2 Ten. 3 Ten. 4th Ten. 5 After the last
shift Content of the ZRPR
written on tape 7th O 1 O O 1 O 1 O 6th O 1 1 O O O O 1 5 O O O O O O O 1 4th O O O O O 1 1 1 3 O O 1 1 O O O 1 2 O O O T-H 1 1 1 1 1 O O 1 O 1 O O 1 O O 1 T-H O 1 O O 1 P. O O O 1 O 1 O 1

Table 3 (Message written on tape)

Bit no. Ten. 1 Ten. 2 Ten. 3 Ten. 4th Ten. 5 ZRP LRP 7th 1 O O O O O 1 6th 1 O O O 1 1 1 5 O 1 1 O O 1 1 4th O O O 1 1 1 1 3 O 1 1 1 O 1 O 2 O O O 1 1 1 1 1 O 1 O 1 1 1 O O 1 1* 1* 1 1 T-H O P. O 1 O O O 1 O

Table 4 (content of the ZRPR after the block according to Table 3 has been read without errors)

Bit no. ZRPR FMR LRPR 7th 1 O O 6th 1 O O 5 1 O O 4th O O O 3 1 O O 2 O O O 1 T-H O O O 1 O O P. 1 O O

Table 5

(Contents of the ZRPR and the FMR after reading the block

according to table 3 with errors in the * digits INV means inverted in digits 7, 6, 5, 3,1, 0, P)

Bit no. ZRPR ZRPR with INV ZRPR once
postponed with INV FMR 7th 1 O 1 1 6th O 1 0 0 5 O 1 1 1 4th O O 0 0 3 O 1 1 1 2 O O 0 0 1 1 O 1 1 O 1 O 0 0 P. O 1 0 0

Table 6
(ZRPR content if the table 3 data is entered during backward reading)

Bit no. At first Zchn.l Ten. 2 Ten. 3 Ten. 4th Ten. 5 At the end 7th 0 1 0 1 0 0 rH 6th 0 1 0 1 0 1 1 5 0 1 0 1 1 1 1 4th 0 1 0 0 1 0 0 3 0 1 1 0 T-H 1 1 2 0 T-H 0 1 0 0 0 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 P. 0 0 1 0 T-H T-H 1

Assume a five-character block as shown in Table 1. Table 2 shows the contents of the ZRP register after each of the bytes listed in Table 1 has been entered. As you can see, the content of the ZRP register is exactly the same as the character after entering the character 1 1. After entering the character 2, the content of the ZRP register corresponds to the value of the respective Antivalence function formed from a bit of character 1 and the corresponding bit of character 2, if the character 1 was previously shifted one place down. If a 1 in the P-bit position stands, the feedback connections are effective, so that after receiving the character 3 pattern remaining in the ZRP register is the pattern which is determined by the values of the bits of the character 2 with the corresponding bits of the character 3 is given non-equivalence functions, It should be noted that two non-equivalence elements follow one another in the feedback stages of the ZRP register.

During writing, the content of the ZRP register is shifted once after the last character has been entered. Then 7 of the 9 bits are inverted namely bits 7, 6, 5, 3, 1, 0 and P and this is written to tape. Table 3 shows the message written on tape. When this message is read, each of the characters except the LRP character is entered into the ZRP register. If there are no errors after reading, the ZRP register contains a pattern as shown in Table 4. This table contains ones in the positions of the ZRP register, the content of which was inverted when the ZRP character (byte) was written. Should there be an error (assuming that the two places marked with asterisks in Table 3 are in error), the ZRP register contains a pattern which generally does not resemble the pattern in Table 4, as shown in Table 5 after the message is read. This pattern differs from the pattern in Table 4; its occurrence indicates that there is an error in the record. In FIG. 9, the AND circuit AB is scanned by the signal + LV 140. If the pattern at the input of this AND circuit does not exactly match the pattern in Table 4, an error signal called -ZRP-Error is transmitted to an error-locking circuit in the control unit 29 (FIG. 2).

Table 6 shows the content of the ZRP register for each character if the characters according to Table 3 in entered in reverse order and after reversing the bits in the manner described above will. The final content of the ZRP register is then identical to the content that is to be found in a normal forward read operation. That is, the final contents given in Table 6 are the same exactly the content given in Table 4.

2. Error detection after attempted error correction

The ZRP register is used for error detection during normal read operations. aside from that it is used for error detection after an attempted error correction. In Fig. 2 appear the corrected data during a correction cycle on the line, which are from the group of non-equivalence

23 24

divide 25 to the central data processing unit concerns several tracks and one track wrongly as leads. They also appear on the line that was calculated with errors. In this case leads to ZRP register 22. They will be checked and the correction will be attempted. The longitudinal redundancy die Circuit 28 for bit pattern control. After the exam allows an independent check after Error correction, the LRP register is queried 5 to correct the data. This test ensures to ensure that there are zeros in all digits so that there is not an error to be corrected contains, and this is done by the circuit 27 is an error that bezur several tracks LRP control. However, the query is hit on the. This is important because of the cyclical redundancy Correction located track prevented by checking an error affecting only one track the error track display in the FM register 23. In the io can not distinguish from an error that LRP registers will affect the uncorrected data of several tracks. If indeed a mistake entered, d. H. the data before it is corrected. has occurred that affects multiple tracks, this will be

The LRP register 26 consists of nine flip-flops, with high probability due to the longitudinal

one for each bit of a byte that the Mo redundancy check determined.

Form the dulo-2 sum of their input signals. The 15

output signals are identical to the input signals Q cyclic error correction
of read-write register 24. The flip-flops are

bistable complementary flip-flops. That is, description of the error correction
every time an input signal changes from the 0 level to the! level, the output signal has three separate changes to the! - and FM mark, secondly the opposite value. The output signal z. B. the calculation of the faulty track under Bedes flip-flops for the 6-bit is used for circuit 27 using the ZRP and FM characters and third for the LRP control (for details see Fig. 8) about correction of the recording during to carry again. In Fig. 8, the + LRP6-bit line is the 25 read operation fetched using the in output line of the 6 flip-flop for the 6-bit. The second part calculated information about the error leads to the AND circuit AB, whose other defective track,
gang is labeled + FMR 6-Bit. This is a .
AND circuit that generates an output signal, ^a -> ^{reading of the block}
if a 1 is at the upper input and an O is at the lower input. This function is indicated by reading the recording and calculating the arrow at the lower input of the AND circuit. ZRP and FM characters are used for reading errors. This means that the AND circuit detection is very similar. No output signal is generated from the ZRP register in AB if the signal is operated in the same way as has been described in the detection of the level of the LRP register 35 associated with the error. The FM-a 1 and the signal of the register assigned to the 6-bit are also used. Referring to FIG. 2, the level of the FM register will be a 1. If the data signal in the read-write register 24 were transmitted to the ZRP register 22 via the non-equivalence of the level of the FM register element 25 assigned to the 6-bit. The one “0” and that of the vertical redundancy level assigned to the 6-bit of each byte of the data becomes a “1” in the LRP register if the AND switch 40 of the VRP circuit 21 were checked. If to derspretung ^ iß generate an output signal. An error in the vertical redundancy signal of each stage of the LRP register is generated at the same time when it is transmitted to the FM register 23. The outputs of all stages are connected to one another by means of a shift, and the output signals register similar to the ZRP register. A block switch is supplied to the AND circuit BF, which is shown at 45 frames of the FM register in Fig. 14, and every time + LV 140 is queried. The AND as you can see, there is only one input, the input signal FMR 6-bit VRP ~ error supplied with circuit AB , at the bottom of the has the purpose of interrogating the register assigned to the 6-bit.

The FM register is shown in FIGS. 6A and 6B.

Signal + FMR 6-Bit is a 1. This is the case when 50 is put. It contains nine interlock circuits,

corrected straight errors in the track for the 6-bit each identified by their output lines

will. The same goes for the remaining stages of becoming. For example, in Fig. 6A is the top one

LRP register. Interlock circuit designated with FMR 7-Bit ,

Both the LRP circuits for error detection the next with FMR 6-bit, the next with

as well as the ZRP circuits for error detection 55 FMR 5-bit. If the line is excited, move +

detect errors after a correction is attempted in Fig. 6A the data is shifted, i.e. h., the

has been. This feature of the error detection content of the register level for the 7-bit is via the

even after a bug is corrected is very important. An AND circuits JM and DA to the register stage

The reason for this is that when it is repeated it shifted for the 6-bit. That happens in detail

Reading the data from the tape is possible that the 60 is as follows: If the register level for the 7-bit is a

Error pattern between the first and the second "1" contains, is at the upper output of the flip-flop

Read operation has changed. This means that either AB is a "1" and a "0" at the lower output.

now another track is faulty, or the output lines both lead to the AND

a character dropout may have occurred. A character circuit of the register stage for the 6-bit, and

failure means that where a character is written, the upper output line to the AND switch

ben is, none has been read. tung JM and the lower output line to the

Another important reason is the guarantee AND circuit DA. When the command + move

performance of protection against errors, if an error is given, the AND circuit generates their

909 503/1558

both input signal are "1", one output signal. If the register stage for the 7-bit contains a "1", the AND circuit JM generates an output signal which then sets the flip-flop CA of the register stage for the 6-bit. If the content of the register stage for the 7-bit is a "0", the AND circuit DA generates an output signal which resets the flip-flop CA of the register stage for the 6-bit. The same applies to the register levels of the 7-bit, des

In most cases, when an error has occurred, the FM register will not contain all zeros. If z. B. read the data from Table 3 with errors in the places marked with asterisks 5, the FM register has the content shown in Table 5 after reading.

b) Determination of the faulty track

The second part of the error correction cycle, namely

6-bit, 5-bit, Ö-bit and P-bit. The IO borrowed the determination of the faulty track, is register levels for the 4-bit, the 3-bit, the 2-bit and also quite simple. The circuit described as implementing the 1-bit by feedback connections is designed as modified. The register level is described for the fact that the 4-bit, which the others are basically the same, is as little technical effort as possible. It is necessary to carry out the calculations; some of them have an antivalence element JB whose output 15 of the parts are therefore used several times,
signal the non-equivalence function of the 5-bit and the If an error is detected, it is expected,

P bits of the FM register. If the one bit that the central data processing unit is a "1" represents when the shift command is given; Arranges return transport and then again the output signal of the AND circuit JP the flip-fetched read operation. This turns the tape into flop HA of the register stage for the 4-bit. If 20 is brought to such a position that the same record is "0", the output signal of the antivalence element JB , in which an error has just been detected, is inverted by the inverter JE and is read again. At the beginning of the repeated when the shift command is given, and the read-out operation, the content of the FM register 23 is the output signal of the AND circuit JQ sets the flip by a signal from the control unit 29 Transfer the flop HA of the register stage for the 4-bit return. The 25 FMR transferred to the read-write register 24 flip-flop HA is set by the output (Fig. 2). In addition, the content of the register stage for the P is transmitted by a signal + ZRPR signal from the exclusive OR element JB, which transmits the content of the switch through (FIG. 4A), the output signal of the register stage for the 5-bit before shifting and ZRPR 22 to the exclusive OR elements 25 Bit after shifting on the nine output lines of these circuits is fed. The value of the non-equivalence radio for the 3-bit, the 2-bit and the 1-bit then applies to the register levels 30, the correspondence between a bit of the ZRP register and the corresponding one. After the shift, they assign the speaking bit of the read-write register. The In value of the non-equivalence function from the content of the halt of the read / write register is now equal to the register level shown above them and the In content of the FM register, which is then cleared, halts the register level for the P bit. The next 35 to the uppermost point of the FM register (Fig. 6A) is set to the register stage for the P-bit (Fig. 6B) by a signal FMR "1" from the register is modified by an input signal. If a control unit 29 (Fig. 2) entered a "1".
Signal - VRP error is present and the signal Error From now on the FM register 23 is used as a counter

read in is available, the AND circuit NC is used. It counts the sliding operations that are necessary, actuated. Your output signal will match the content of 40 to ensure a match between the content of the register level for the O-bit of the non-equivalence element NF ZRP register and the current content of the

Read-write register. If at all outputs of the nine non-equivalence elements (Fig. 4A and 4B) zeros are present, there is a match between all bits of the ZRP register and the read-write register. If this is the case, the pushing operations are switched off by a signal the circuit 28 for bit pattern control (Fig. 2) ended. If the correction antivalence elements after

to the FM register (FIGS. 6A and 6B) as well as to a 50 of FIGS. 4A and 4B as output signals of a locking circuit for the vertical redundancy zeros, this is determined by the OR circuit BC (FIG. 9) . Their output signal reaches the AND circuit BF via the inverter BG. This AND circuit is blocked provided that the ZRP register does not contain all zeros, which is determined by the OR circuit BA , and that the ZRP register does not have the content 111010111, which is indicated by the AND Circuit BB is established. When the AND is entered. In addition, if the LRP register is prepared in the 60 circuit, the signal is interrogated in a manner described above. If corrective interlock circuit. If there is an error in one of these positions, it is set, it terminates the position shifting interlocking circuit for the data check in the FM register and the ZRP register. Except control unit 29 switched on. This information is cleared by the ZRP register and generated, the central data processing unit will clear the signal ZRPR that leads to each of the flip-flops. of the ZRP register.

If there are no errors, the FM register 23 (FIG. 2) can only do so

Register after the read operation all zeros. carry out long push operations until the end

fed. The output signal of this circuit is then sent to the flip-flop of the register stage for the P bit fed when the shift command is given.

The VRP circuit is in Figures 3A and 3B shown. This circuit is used to determine the parity or the VRP character of the content of the Read-write register. Your output signal will be

Test for reading and writing and to an interlock circuit for data testing, the both contained in the control unit 29 (Fig. 2) are transmitted.

After the read operation, the ZRP register is queried, as described in the section on the zur ZRP register used for error detection has been written to in order to determine whether an error has occurred.

output signal of the circuit 28 for bit pattern control indicates that the output signals of the antivalence elements 25 are all zeros. If this is the case immediately, no sliding processes take place at all. When a shift pulse occurs, it is sent to the FM register and the ZRP register. If no If a match is displayed, another sliding process takes place. This is done for eight Shifts, i.e. nine comparisons. If there is a match in any of these shifts had taken place, the pushing operations would have been canceled. The so-called correction lock circuit in the control unit 29 would then have been set. The content of the FM register would consist of the "1" entered above and shifted several times. This would indicate which lane contains the error. The ZRP register would be cleared, and it can Now the third part of the correction operation, the actual data correction, takes place. Before this so is written, several details of the FM register and the comparison will be explained.

The 7-bit position of the FM register is set to "1", as shown in FIG. 6A. This is done by writing the FMR »1« signal. The OR circuit YES is reached. When this signal is present and a shift pulse occurs, the "1" goes through the AND circuit JK and sets the flip-flop AB . Therefore a "1" is entered into the level of the FM register for the 7-bit.

The following is a description of the operations shown in FIG. 2 antivalence elements shown as block 25. They are shown in more detail in Figures 4A and 4B. Each circuit is similar to the circuit for the 7-bit, which will be described below. When the line + ZRPR is energized , the content of the stage for the 7-bit goes to the AND circuit DF. It goes through the OR circuit DG; the inverter DH, the AND circuit DJ, the AND circuit DK and the OR circuit DL form an exclusive OR circuit.

As an example of the mode of operation it is assumed that there is a "1" on the -ZRPR 7-bit line of the ZRP register (ie that there is a "0" on the + ZRPR 7-bit line ) and that the signal + LS register 7-bit is equal to "1". This means that the -L-S register 7-bit signal is "0". Now there is a "1" at both inputs of the AND circuit DF , and therefore the output signal is also a "1". The output signal of the AND circuit DE is equal to "0" and is not used now. The output signal of the OR circuit DG is equal to "0". As a result, the output signal of the AND circuit DJ becomes "0". The inverter DH fed by the OR circuit DG generates a "1", but the input signal of the AND circuit DK is a "0" at the input -LS register 7-bit. Therefore, the AND circuit DK generates a zero output signal. Now both input signals for the OR circuit DL are equal to "0", so that its output signal is a "1", which is transmitted to the inverter AA , which now generates a "0". So if there was a "1" on the - ZRPR 7-bit line and the signal on the + LS Register 7-bit line was a "1", the output signal on the + read line 7-bit line is a "0"; ie if the content of the stage for the 7-bit of the ZRP register and the stage for the 7-bit of the read-write register are not the same, the output signal on the 7-bit read line is a "0". The same applies to the non-equivalence elements for the 6-bit, the 5-bit, the 3-bit, the 1-bit, the O-bit and the P-bit. However, the inputs to the 4-bit circuit and the 2-bit circuit in Figures 4A and 4B are a signal on the -ZRPR 4-bit line and a signal on the -ZRPR2-bit line, respectively. These output signals from these circuits are equal to zero when the content of the stage of the read / write register and the content of the stage for the corresponding bit of the ZRP register are the same. All nine output signals are zeros if the contents of the stages of the ZRP register and the read / write register for the 7-bit, the 6-bit, the 5-bit, the 3-bit, the 1-bit, the The O-bit and the P-bit are different and the contents of the levels of both registers for the 4-bit and the 2-bit match. This takes into account the fact that the ZRP character has been written as a complement in the relevant bit positions.

c) Error correction of a data block

The data will now be corrected. It does this in a fairly simple manner. Let it be up F i g. 2 referred to. The data is transferred to the read-write register 24 in the normal manner. If the VRP circuit 21 determines that the data byte is an incorrect VRP character possesses, the data are stored in the place by the non-equivalence elements 25, which the as erroneous he corresponds to the calculated track, complemented. The information about the faulty track is in the FM register contain. The content of the FM register 23 is transferred to the antivalence elements 25, if there is a signal 21 »read / write VRP characters«. Because the content of the FM register is louder With the exception of the "1", there are zeros in the position that corresponds to the faulty track, left the data, the antivalence elements 25 in the same form in which they were supplied to them, but with the exception that the content of the register stage corresponding to the faulty track is inverted became. The corrected data are transferred to the data register of the Additional tape device and therefore transferred to the central data processing unit. Also be it is forwarded to the ZRP register 22 in order to determine whether the correction has been made correctly. The uncorrected Data is supplied to the LPR register 26. After the read operation with correction, these Registers both queried by circuits 27 and 28 as described in the section on error detection to ensure that they are in the correct condition, in to which they indicate that no errors have occurred. The LRP symbol is used by the circuit 27 Control of the LRP character (Fig. 8) queried. As you can see, the query is suppressed in the place in which the FM register has a "1"; d. i.e., the LRP character is queried to see if it consists of all zeros with the possible exception of the position in which the FM register has a "1" contains, d. H. the point that corresponds to the track calculated as faulty. This is the error correction cycle.

The important part of the components for the correction, which in the error correction just described

are used, consists of the antivalent elements shown in Figs. 4A and 4B. The following is a description of the use of these non-equivalence elements to correct an error in a byte. As an example it is assumed that the presence of an error in the 7-bit has been calculated. In this case, the content of the level of the FM register for the 7-bit is a “1”. This is fed to the AND circuit DE. If there are no errors ^, the VRP error signal is "0". The output signal of the OR circuit DG is therefore a "1". If the signal on the line + L-S register 7-bit was a "1", the output signal is AND =. Switching DJ a "1". The output signal of the OR circuit DL is therefore a “0”. Then * 5 the output signal of the inverter AA is a "1". In this case, the data pass through the non-equivalence elements without any changes. However, if there had been a signal on the line ^ VRP * Error , both input signals of the AND circuit DE would have been ones. The output signal of the OR 'circuit DG would be a "Q", therefore the output signal of the inverter DH would be a "1". If the signal on the + LS Register 7-Bit line were a "1", the signal on the -LS Register as 1-Bit line would be a "0". None of the AND circuits DJ and DK would be energized. Therefore, the output signal of the OR circuit DL would be a "1". The output signal of the inverter AA would then be a "0". In other words, in this case the content of the stage of the read-write register for the 7-bit would be inverted. The output signal on the 7-bit read line is then forwarded to the transmission circuit and, under normal control, to the central data processing unit. This output signal is also fed to the ZRP register.

Claims (4)

Patent claims: 1.Circuit arrangement for error detection and correction in binary encrypted data blocks, in which each character in parallel form is made up of η bits for test purposes Parity bit to supplement its number of bits to odd or even numbers (Vertical redundancy) and the end of a data block is marked with a check character, using feedback shift registers to calculate check characters for cyclical redundancy check, identified by a) a known per se connected to the receiving register (24 in FIG. 2) Circuit (21) for checking the vertical redundancy when a fault is detected a binary 1-bit with a first feedback η-stage shift register (23) feeds only one data input, the outputs of which are connected to a group of non-equivalence elements (25) and to the inputs of the receiving register (24) as well are connected via the group of antivalence elements (25) to a second fed-back «-stage shift register (22), its outputs also to the antivalence elements (25) and to a circuit (28) lead to the bit pattern control and its content simultaneously with the content of the first Shift register shifted by one level after receiving a character and after reading a data block, a block is formed from the received data Contains test marks for cyclical redundancy, b) a control unit (29) which compares the contents of the causes both feedback shift registers after reading a data block in the antivalence elements (25), in the event of inequality, which indicates the presence of errors, the deletion of the receive register and the transfer of the contents of the first Shift register (23) in the receiving register (24) and the writing of a binary 1-bit in the lowest level of the first shift register, also the simultaneous shifting of the contents of both Shift register and comparing the content of the second shift register with the content of the receive register in the non-equivalence elements and the shifts are terminated if the register contents are the same, where the position of the binary 1-bit in the first shift register represents the faulty data track and which the data block to the receiving register with renewed examination of the Adds vertical redundancy and, if an error is detected, a correction of the defective one Bits by combining the read character and the content of the first fed back Shift register in the antivalence elements (25) causes. 2. Circuit arrangement according to claim 1, characterized in that the feedback connections of the shift register except from Output to input are arranged symmetrically to the center of the shift register. 3. Circuit arrangement according to claim 2, characterized in that the order of Input lines of the first shift register for error detection and correction in the Delivery of the data can be switched in reverse order. 4. Circuit arrangement according to claim 3, characterized in that for error detection and correction when the data is delivered in reverse order instead of switching of the input lines reverses the shift direction of the first shift register will. In addition 5 sheets of drawings