US3492422A - Printing telegraph apparatus - Google Patents

Description

United States Patent O 3,492,422 PRINTING TELEGRAPH APPARATUS Frederick Percival Mason, Sutton, and Alfred Lawrence Joseph Luke Suban, London, England, assignors to Creed & Company Limited, Hollingbury, Brighton, Sussex, England, a British company Filed May 3, 1967, Ser. No. 635,895 Claims priority, application Great Britain, May 3, 1966, 19,418/66 Int. Cl. H041 /34 U.S. Cl. 178-26 2 Claims ABSTRACT 0F THE DISCLOSURE This invention relates generally to apparatus for converting start-stop, serial-mode signals into parallel-mode signals, and in particular to means for improving the timing of the instants at which the parallel-mode output signals are offered to a utilization device, such as a printer or perforator, operating in either start-stop or neverstop manner.

In a conventional serial-to-parallel converter, the code elements of a received combination are loaded serially into a first store under the control of a start-stop timebase. When the code becomes valid in the first store, it can be offered to the utilization device by opening a set of gates, the code elements generally being concurrently transferred into a second store.

However the instants at which successive transfers can occur are Ifixedly related to the arrival instants of successive start signals.

Moreover the presence of line distortion can cause the incidence time interval, between two consecutive start signals, to become less than the interval at which they were transmitted. Therefore it follows that the lifetime of a code combination in the second store can be less than the nominal transmission interval. The cycle time of any utilization device cannot be greater than the least lifetime of the code in the second store and is consequently less than the nominal transmission interval.

It is this situation that can be improved by adopting the invention described herein.

Accordin-g to the invention in its broadest aspect there is provided serial-to-parallel code conversion apparatus comprising a storage device that is arranged to be serially loaded under the control of a conventional start-stop timebase, which apparatus is characterised by the incorporation of auxiliary timing means whose output pulse controls the opening of a set of gates through which the parallel-mode signals from the connection apparatus are offered to a utilization device, the auxiliary timing means being prepared by a signal from the start-stop timebase and triggered to yield a further output pulse when it has measured out a prescribed time interval whose duration is greater than the least interval between the arrival of consecutive start signals but less than the nominal transmission interval between successive start signals.

If the invention is employed with a start-stop utilization device, the act of offering the parallel-mode signals 3,492,422 Patented Jan. 27, 1970 to the device can be made effective to start a cycle of operation thereof.

Before describing how the invention may be used with a so-called neverstop utilization device, it is deemed advisable to identify clearly the principal characteristics of a neverstop system.

By a neverstop device is meant one having contiguous operating cycles that are effected continuously. lIt is this characteristic that permits the mechanical version of a neverstop device, such as a neverstop printer, to avoid the need for a clutch that often demands frequency maintenance attention.

In a neverstop system it is arranged that pulses are vemitted to announce the instants of passage from one operating cycle to another.

It will be appreciated that there can be an entirely random phase relationship between the pulses emitted by the neverstop system and the instants at which parallel-mode codes are offered at the output of the serial-to-parallel converter.

Nevertheless, the emitted pulses can still be used t0 interrogate the store into which the signals are offered under the control of auxiliary timing means, by using pulses of short duration to open a second set of gates.

In exactly the same manner as for a start-stop utilization device, the invention allows the neverstop system to have a cycle time almost as great as the transmission cycle time.

However, in common with most utilization devices, a neverstop printer needs a parallel-mode input that is sustained for the whole printing cycle. This requirement is fulfilled by providing a further stage of storage into which the signals are transferred when the said second set of gates are opened by the interrogation pulses.

Since at the time of occurrence of the interrogation pulse, there may be no code waiting-at the converter output, a signal must be provided that indicates to the utilization device, by its presence or absence, whether or not a code is awaiting processing.

The exact means whereby the system according to the invention cooperates with a neverstop printer or perforator will be better understood from the following detailed description of such an embodiment.

This embodiment is illustrated in FIGURES l and la of the accompanying drawings which, when placed together, are in the form of a block schematic diagram showing a neverstop printer responsive to receive startstop signal combinations.

In this embodiment it is assumed that the received signal combinations comprise an immutable start element, five permutable code elements and an immutable stop element of indefinite duration. These signal combinations are received in serial mode over the input line on the left of the figure.

The detection of a stop-start transient by the detector SD triggers a first time base TB1 whose distributed output samples the incoming code combination at the midpoints of successive elements. A first (sequential) store S1 is reset as necessary by the sampled start signal, and is then loaded with the incoming code combination as gates G1 are opened singly and successively by the distributed output pulses of the start-stop timebase TB1.

The received code combination becomes valid in store S1 when the fifth permutable element is sampled; whereupon a first memory (bistable) M1 changes to its set condition (1). The output of M1 triggers a l-shot auxiliary timebase TBZ, Whose output immediately prevents any further triggering of itself by energizing a inhibit gate I, and also resets as necessary a second (concurrent) store S2. After a short delay to allow store S2 to be properly reset, a second set of gates G2 are opened by a differential pulse from the timebase TBZ, to transfer the valid code from S1 to S2, reset memory M1 and set a further memory M2.

With memory M2 set, a pulse from a further (neverstop) timebase TB3 resets as necessary a (concurrent) store S3 and a memory M3, then after a short delay opens gates G3 to transfer the valid code from S2 to S3, and changes memory M3 to its set condition. Since the minimum lifetime of the valid code in S2 is determined by the l-shot auxiliary timebase TBZ, the interval between the pulses from the neverstop timebase TB3 is such that at least one pulse occurs during this lifetime. It is to be understood that the neverstop timebase TB3 could be a purely mechanical device directly operated by the printing mechanism.

The output of memory M3 resets memory M2 and causes the marshalling or translating system MT to select the type or function in accordance with the parallel code in S3 and, after a delay to allow marshalling to take place, energizes the type or function actuator A. It is to be understood that the marshalling system MT could also control the operation of a tape punch in addition to, or instead of, a printer.

When the next start signal element arrives, the operation of the system will depend on the interval that has elapsed since the previous start signal element was received. If the interval is equal to or greater than a normal character period, the auxiliary timebase TBZ will have completed its cycle before the new code becomes valid to change memory M1 to its set condition. Therefore the sequence of operation will be as described for a previous i code. However, if the interval is less than a normal character period the auxiliary timebase TBZ will not have completed its cycle when memory M1 becomes set to denote that the new code is valid in store S1. Nevertheless, as soon as the auxiliary timebase does complete its cycle, it is re-triggered by memory M1. Although the period of the auxiliary timebase is made almost equal to a character period, the lifetime of the valid code in S1 is always suficient to allow the auxiliary timebase to complete its previous cycle and be re-triggered to open the gates G2 before S1 can be reset by the arrival of a further start signal element.

When no further start signal elements are received, memories M1, M2 and M3 are all reset as the previous code is processed. Although the nevertstop timebase TB3 continues to emit regular pulses, the marshalling system MT receives no further command signals from memory M3.

What we claim is:

1. An improved serial-to-parallel code converter of the type having a iirst store arranged to be serially loaded with received code signals by way of a iirst set of gates under the control of an original start-stop timebase and a second store coupled to said iirst store and arranged to be concurrently loaded with said signals by way of a second set of gates, wherein the improvement comprises an auxiliary timebase circuit, coupled between said original timebase and said second set of gates, for providing an independent timebase which permits full use of converted code signal combinations by a utilization device in cases of received signal distortion, said auxiliaiy timebase circuit including:

a bistable memory element coupled to the original time-l base, said memory element being set by said original timebase whenever a code combination is validly entered in said first store;

an inhibiting device, having afirst input coupled to said memory element and an inhibiting second input, said inhibiting device providing an output in response to a corresponding input from said memory element in the absence of a signal at said inhibiting input; and

a monostable device, having a predetermined time period of operation which is greater than the least interval consecutive input code start signals but less than the normal interval between said start signals, said monostable being input coupled to said inhibiting device and being output coupled to the inhibiting second input of said inhibiting gate, to said second set of gates, and to said memory element, said monostable device providing an output of said predetermined duration in response to a validly entered code combination in said rst store, which output inhibits the inhibiting device for said duration, resets said memory element, and opens said second set of gates to allow the transfer of the code combination in the first store to said second store, whereby a subsequent setting of said memory element from a prematurely arrived succeeding code combination will be retained for a time sucient to allow said utilization device to make full use of the preceding code combination in said second store, while the transfer of said succeeding code combination to the second store is permitted before it can be erased by a further succeeding code combination to be entered in said first store.

2. Apparatus according to claim 1 further including a concurrent third store coupled to said utilization device, a third set of gates coupled between said second and third stores for controlling the transfer of code signals therebetween, a control gate coupled to said third set of gates for initiating said transfer of code signals, a seccond bistable memory element coupled to the output of said monstable device and to said control gate for priming said control gate in response to an output signal from said monostable device, a further time base circuit coupled to said control gate for providing enabling signals to said control gate, and a third bistable memory element coupled to said control gate and said utilization device for generating a triggering signal to said utilization device in response to a signal from the enabled control gate.

References Cited UNITED STATES PATENTS 2,961,649 l1/l960 Eldredge et al. 340--1463 1,576,167 3/1926 Wheeler, et al 178--l7.5 3,267,460 8/ 1966 Merrell, et al. 340--347 3,376,384 4/ 1968 Achramowicz 178--26 THOMAS A. ROBINSON, Primary Examiner M. M. CURTIS, Assistant Examiner U.S. Cl. X.R.

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