US3392313A - Semiconductor device of the four-layer type - Google Patents

Semiconductor device of the four-layer type Download PDF

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Publication number
US3392313A
US3392313A US601219A US60121966A US3392313A US 3392313 A US3392313 A US 3392313A US 601219 A US601219 A US 601219A US 60121966 A US60121966 A US 60121966A US 3392313 A US3392313 A US 3392313A
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semiconductor body
semiconductor
junctions
zones
zone
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US601219A
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English (en)
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Patalong Hubert
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Siemens AG
Siemens Corp
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Siemens Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/60—Impurity distributions or concentrations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/228—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a liquid phase, e.g. alloy diffusion processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D18/00—Thyristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • My invention relates to silicon controlled rectifiers, dynistors and other semiconductor devices of the fourlayer type, having a substantially monocrystalline semiconductor body with four layers of alternately different types of conductance forming p-n junctions.
  • Such semiconductor devices afford a switching operation of thyratron character.
  • the load current through all of the four layers may be started by means of an ignition current applied between one of the two intermediate layers and the adjacent outer layer. Switching-off is effected by the load current approaching, or passing through, zero.
  • the two outer layers carry respective electrodes for the load current, and one of the intermediate layers carries a base or gate contact for supplying the igniting or firing current.
  • the four-layer device may ignite without application of a firing current.
  • the voltage magnitude at which this takes place is the so-called forward break-over voltage. This voltage decreases with increasing temperature so that p-n-p-n devices may lose the ability to block forward voltage.
  • efforts have been made to increase the break-over voltage as much as possible, because this voltage determines the rated load voltage of the device.
  • the distance or spacing between the two outer layers and the intermediate p-n junction on the surface of a p-n-p-n semiconductor body is larger by at least a factor of 20 than the diffusion length of the minority charge carriers in one surface layer of each intermediate layer. It has been found that this affords greatly increasing the break-over voltage, especially at elevated temperatures. This may be explained by the observed fact that even at room temperature the reverse current which exists while the four-layer semiconductor device is in the non-ignited state, flows mainly on the surface of the semiconductor body. Even with low voltages this surface current may reach such a high value that ignition will occur. Consequently, the ignition can be considerably retarded by a corresponding reduction of the surface current.- This is particularly necessary at elevated temperatures, for instance, 100 to 150 C.
  • FIGS. 1 and 2 show enlarged cross sections of two four-layer silicon-controlled rectifiers embodying features of the invention
  • FIG. 3 is an explanatory diagram.
  • the device illustrated in FIG. 1 is produced in the following manner.
  • a circular disc of n-type silicon has a resistivity of from to 100 ohm-centimeters, a diameter of 18 mm., and a thickness of 250 microns.
  • the disc is subjected to a diffusion process with aluminum and 3,392,313 Patented July 9, 1968 is thus provided with a p-type region which completely surrounds the disc on all sides.
  • By working an annular groove 5 into the disc the region is subdivided into two p-type regions 4 and 3.
  • the intenior of the semiconductor body constitutes the original, unmodified n-type zone 2.
  • the diffusion of aluminum into the body may be effected, for instance, by introducing a plurality of such semiconductor bodies and an amount of aluminum into a quartz ampoule which is then sealed off.
  • the ampoule preferably is kept :in an electric resistance furnace, at a temperature of 1200" C. for a period of approximately 60 hours. Thereafter the penetration depth. of the aluminum diffused into the semiconductor body is approximately 60 to 70 microns.
  • the aluminum concentration near the surface is approximately 3x10 cm.
  • the groove 5 may be obtained by etching.
  • the semiconductor body can be coated with Picein varnish.
  • a pattern corresponding to the desired groove shape for instance an annular trace, is scratched into this Picein layer on one of the flat faces of the round semiconductor disc.
  • the entire unit is dipped into an etching solution which will now attack the semiconductor body surface only in those areas where the Picein has been removed therefrom.
  • the depth of the groove is easily determined by correspondingly selecting the etching time.
  • the groove must, along its entire length, penetrate at least the aluminum-doped marginal zone.
  • the groove depth may be approximately microns, its width depending on the width of the trace scratched open in the Picein coating and being, for instance, about 1 mm.
  • the drawing illustrates the semiconductor elements on an enlarged and greatly disproportionate scale, particularly with respect to the thickness ratios thereof.
  • the groove 5 may also be obtained by a suitable mechanical process such as by grinding or lapping, using a tool of the hollow drill type, or by milling or cutting.
  • the required contacting electrodes are provided on the semiconductor body by a subsequent alloying proc ess, with the still missing fourth zone being produced simultaneously therewith.
  • the semiconductor body is placed upon an aluminum foil having approximately the same diameter as the semiconductor body and having a thickness of about 60 microns.
  • An annular foil consisting of a gold-antimony compound (approx. 0.5% Sb) and having an interior diameter of about 4 mm. and an outer diameter of about 11 mm. is superimposed upon the grooved surface of the semiconductor body.
  • Another foil consisting of gold containing boron and having a diameter of approximately 3 mm. is placed centrally into the aperture of this annular disc.
  • the foils may have a thickness of approximately 40 microns.
  • the entire assem bly is then heated in a furnace to a temperature of approximately 800 C., and the unit illustrated in FIG. 1 is obtained.
  • the zone 3 receives a contact electrode 6 formed by the aluminum foil alloyed to the unit.
  • An annular zone 7 doped with antimony and consequently exhibiting an n-type conductivity is formed on the top surface of the semiconductor element. llt is contacted by an electrode 8, while the zone 4 carries a contact electrode 9.
  • the semiconductor element thus comprises a four-layer structure consisting of the Zones 3, 2, 4 and 7 arranged in a p-n-p-n sequence in accordance with the schematic diagram shown in FIG. 3 where the same respective reference numerals are applied as in FIG. 1.
  • the intermediate p-n junction which will exert a blocking action as long as the semiconductor device is not ignited, is the p-n junction between zones 2 and 4.
  • the dimensions of the semiconductor member are such that the spacing A or B of the two outer layers 3, 7 from this p-n junction on the surface of the semiconductor body is larger by at least the factor 20 than the diffusion length of the minority charge carriers in the semiconductor material of the two intermediate layers 4 and 2 on the surface of the semiconductor body.
  • the distance A on the surface of the semiconductor body between the layer 7 on the one hand, and the p-n junction located between the layers 2 and 4 on the other hand, is particularly of special importance. This distance was made approximately 2 mm. (this resulted from the chosen dimensions of the gold-antimony foil employed).
  • the diffusion length L of the minority carriers in this range of the semiconductor surface is approximately 50 microns, so that the requirement is met because As a result, the reverse current on the surface is considerably reduced, whereby the forward break-over voltage and its temperature stability are greatly increased.
  • FIG. 2 illustrates another embodiment of a four-layer semiconductor element embodying features of the present invention.
  • the design and composition thereof is substantially the same as in FIG. 1. Identical zones and electrodes, respectively, are denoted by the same reference numerals.
  • the method of production thereof is substantially the same as described with reference to the first-mentioned embodiment.
  • the only essential difference consists of adding a process step after the diffusion step producing the p-type marginal zones 4 and 3, and before the alloying process, so as to reduce consider-ably the diffusion length of the minority carriers within the surface area of zone 4.
  • the surface area denoted by 4a in FIG. 2 is flooded with impurities which are diffused therein.
  • This may be effected by first coating the entire surface area of the semiconductor disc with an oxide layer, for instance by way of oxidation in steam at higher temperatures. Then an annular zone of this oxide layer is removed from the surface of the semiconductor body, for example by mechanical removal of the oxide with the aid of a tool of the hollow drill type. This annular zone may have an interior diameter of about 15 mm. and an outer diameter of about 17 mm. Then boron is diffused in a manner similar to the diffusion of aluminum forming the p-type marginal zone. This diffusion of boron, however, merely produces a high marginal concentration in the order of approximately 10 to 10 cm. Heating to a temperature of approximately 1280 C. for a duration of approximately one hour will be sufficient.
  • the penetration depth of boron is only slight (about 5 to microns) and will have the desired effect on the surface only.
  • the same results can be obtained by increasing the annular width of the groove 5 and/or reducing the diffusion length of the minority carriers within the surface area at the bottom of groove 5.
  • This is effective when the n-conductive Zone 2 is contacted by an electrode at the bottom of groove 5 or at a similarly exposed area and is used as the gate.
  • separation between p-conducting zones 3 and 4 is not accomplished by etching but rather by completely cutting off the periphery of the disc. This is done by directing a sand blast at the location of the groove 5 and turning the disc through its vertical axis. The sand stream is then continued until it passes through the zone 2 and the entire thickness of the disc from top to bottom. In this case it is the dimension B, constituted by the thickness of zone 2, which is critical.
  • a semiconductor element comprising a substantially monocrystalline semiconductor body having a surface and a plurality of zones of alternating conductivity type forming three spaced intermediate p-n junctions one of which is formed between two others and emerges at the surface of said semiconductor body, said one of said p-n junctions being spaced from another of said p-n junctions by a distance along the surface of said semiconductor body larger than the diffusion length of the minority carriers on the surface of said semiconductor body between said p-n junctions by at least a factor of 20.
  • a semiconductor element as claimed in claim 4 further comprising a contact electrode on said one of said inner zones at the surface of said semiconductor body between said p-n junctions.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thyristors (AREA)
US601219A 1962-06-19 1966-12-12 Semiconductor device of the four-layer type Expired - Lifetime US3392313A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DES79974A DE1209660B (de) 1962-06-19 1962-06-19 Steuerbares Halbleiterbauelement mit einem im wesentlichen einkristallinen Halbleiterkoerper und vier Zonen abwechselnd entgegengesetzten Leitfaehigkeitstyps

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US3392313A true US3392313A (en) 1968-07-09

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US601219A Expired - Lifetime US3392313A (en) 1962-06-19 1966-12-12 Semiconductor device of the four-layer type

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US (1) US3392313A (en, 2012)
CH (1) CH396229A (en, 2012)
DE (1) DE1209660B (en, 2012)
FR (1) FR1415513A (en, 2012)
GB (1) GB1037804A (en, 2012)
NL (1) NL290680A (en, 2012)
SE (1) SE301192B (en, 2012)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3832709A1 (de) * 1988-09-27 1990-03-29 Asea Brown Boveri Thyristor

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2959681A (en) * 1959-06-18 1960-11-08 Fairchild Semiconductor Semiconductor scanning device
US2993154A (en) * 1960-06-10 1961-07-18 Bell Telephone Labor Inc Semiconductor switch
US3097335A (en) * 1959-10-14 1963-07-09 Siemens Ag Electric current inverter
US3164500A (en) * 1960-05-10 1965-01-05 Siemens Ag Method of producing an electronic semiconductor device
US3175934A (en) * 1960-01-19 1965-03-30 Hitachi Ltd Semiconductor switching element and process for producing the same
US3210563A (en) * 1961-10-06 1965-10-05 Westinghouse Electric Corp Four-layer semiconductor switch with particular configuration exhibiting relatively high turn-off gain
US3211971A (en) * 1959-06-23 1965-10-12 Ibm Pnpn semiconductor translating device and method of construction

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL268728A (en, 2012) * 1960-06-10

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2959681A (en) * 1959-06-18 1960-11-08 Fairchild Semiconductor Semiconductor scanning device
US3211971A (en) * 1959-06-23 1965-10-12 Ibm Pnpn semiconductor translating device and method of construction
US3097335A (en) * 1959-10-14 1963-07-09 Siemens Ag Electric current inverter
US3175934A (en) * 1960-01-19 1965-03-30 Hitachi Ltd Semiconductor switching element and process for producing the same
US3164500A (en) * 1960-05-10 1965-01-05 Siemens Ag Method of producing an electronic semiconductor device
US2993154A (en) * 1960-06-10 1961-07-18 Bell Telephone Labor Inc Semiconductor switch
US3210563A (en) * 1961-10-06 1965-10-05 Westinghouse Electric Corp Four-layer semiconductor switch with particular configuration exhibiting relatively high turn-off gain

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3832709A1 (de) * 1988-09-27 1990-03-29 Asea Brown Boveri Thyristor

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Publication number Publication date
SE301192B (en, 2012) 1968-05-27
NL290680A (en, 2012)
DE1209660B (de) 1966-01-27
GB1037804A (en) 1966-08-03
DE1209660C2 (en, 2012) 1966-10-13
CH396229A (de) 1965-07-31
FR1415513A (fr) 1965-10-29

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