US3387118A - Static counter having main and aluxiliary stores and controlled by staggered counting and auxiliary counting signals - Google Patents

Static counter having main and aluxiliary stores and controlled by staggered counting and auxiliary counting signals Download PDF

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Publication number
US3387118A
US3387118A US327585A US32758563A US3387118A US 3387118 A US3387118 A US 3387118A US 327585 A US327585 A US 327585A US 32758563 A US32758563 A US 32758563A US 3387118 A US3387118 A US 3387118A
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Prior art keywords
counter
counting
signal
auxiliary
signals
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US327585A
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English (en)
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Petzold Dieter
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LICENTIAS PATENT VERWALTUNGS G
LICENTIAS PATENT-VERWALTUNGS-GMBH
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
    • H03K23/665—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by presetting

Definitions

  • ABSTRACT OF THE DISCLOSURE A multiple-digit static counter each of whose stages has main and auxiliary stores and which is controlled by counting signals and auxiliary counting signals, the latter being staggered with respect to and timely spaced from the former.
  • the instants at which the main stores, at whose outputs there appears the count of the respective digit, are set and erased, are controlled by the respective auxiliary store which has different circuit conditions at the two instants and, in addition, by the counter stage of the preceding digit and/or by the counting and/ or auxiliary counting signals.
  • there is built into the counter a tolerance for differences in the characteristics of the semiconductor elements forming part of the counter, in that differences in the switching times of the individual circuit components will not cause errors.
  • the present invention relates to a static counter.
  • the object of the present invention to provide a counter which overcomes the abovementioned drawbacks, and the present invention therefore resides in a trouble-free static counter incorporating Patented June 4, 1968 galvanically coupled counter stages, which counter has no discontinuities, and which counter is, moreover, substantialy proof against external interference.
  • the present invention relates to a static counter which is able to count forward or backward and is capable of being preset to a desired binary number, which counter can be converted to a decimal counter which is able to count forward or backward and can, if desired, be made capable of being preset to a desired decimal number, which counter, moreover, can have applied to it counting signals and auxiliary counitng signals of any shape, the auxiliary counting signals being displaced, with respect to time, relative to the counting signals, i.e., the counting signals and the auxiliary counting signals are timely spaced from each other.
  • the main storage unit of each binary digit changes its circuit condition during the counting operation only at the instant of a counting signal (t and the corresponding auxiliary storage unit changes its condition at the instant of an auxiliary counting signal (t or a counting signal (13 but not at the same instant as the main storage unit.
  • the main and auxiliary storage units will each have at least two logic circuits, and according to a further feature of the present invention, the input stages of the auxiliary and main storage units are AND-circuits.
  • the auxiliary storage unit has at least two input AND-circuits and the main storage unit has at least three input AND-circuits each of which controls an OR/NOT-circuit whose output, in turn, is connected to a NOT-circuit.
  • A the output signal of a main storage unit
  • an erase or reset signal is applied to the counter stages. It is advantageous if this erase signal is composed of at least two erase signals, for example, according to.
  • the main storage units of the counter stages have the logical function (t C QH98CT)l (A ?A Q (t &H &F v (A di-L811) v (A,,&7 &1) :A n and the auxiliary storage unit of the counter have the logical function It is advantageous if there is introduced into the counter stage of the lowest order binary digit a counting command signal with the help of which it is decided whether the counter is to count the counting signals.
  • the main storage unit of the counter stage of the lowest binary digit has the logical switching function and the corresponding auxiliary storage unit has the logical switching function It is, furthermore, advantageous, if a clear for counting signal is applied to the counter stage of the lowest binary digit, which clear for counting signal is so synchronized by a counting command signal that may appear at any instant as to appear and disappear at the start of an auxiliary signal.
  • the main storage units have the logic functions
  • the main storage units of the counter stages are controlled, following an erase command, by presetting signals in order to obtain a presetting of the counter to a given binary number. Therefore, each of the main storage units has associated with it a logic circuit which is controlled by the presetting si nal and a clear for presetting signal.
  • This logic circuit preferably has the function (k &f)n:O, l, 2
  • the preset clearin signal appears after the erasing and disappears with the clearing for counting, and reappears only after a further erasing.
  • a storage unit is provided for producing the clear for presetting signal, which storage unit has the logic function 11101185 :m and forms a signal which controls a logic stage connected to the output of the storage unit which has a further in-- put for the erase signal and itself has the logic function fed back from the fourth counter stage to the third counter stage, or a signal from the fourth counter stage is fed back to the second counter Stage and a signal of the first counter stage is applied to the fourth counter stage.
  • the signals needed for the decimal conversion replace the signals controlling the binary counter, or the signals needed for the decimal conversion are combined with the signals which, up to now, have controlled the binary counter, in separate logic circuits whose output signals replace the control signals used up to now, with the arrangement being such that the construction of the binary counter stages remains unchanged.
  • the auxiliary storage units of the second and third counter stages have applied to them a further signal from the fourth counter stage. It is of advantage to provide the auxiliary storage units of the second and third counter stages each with a logic input stage, for the (i-l-lfi decade (value lO has the logic function According to a further feature, the manner in which the auxiliary storage units of the second and third counter stages are controlled is modified, in comparison to the binary counter, in that the signal which, up to now, has controlled each counter stage is replaced by the output signal of a separate logic circuit in which the signal which up to now was the controlling signal is combined with a signal from the fourth counter stage.
  • the main storage unit of the second counter stage has applied to it a signal from the fourth counter stage and the auxiliary storage unit of the fourth counter stage has applied to it a signal from the first counter stage. It is of advantage if there is additionally applied to the input stage of the main storage unit of the second counter stage of the decade (value a signal from the auxiliary storage unit of the fourth counter stage, and if, in an input stage of the auxiliary storage unit of the fourth counter stage, the signal of the auxiliary storage unit of the preceding counter stage is replaced by the signal of the auxiliary storage unit of the first counter stage.
  • one of the two signals which, up to now, have controlled the main storage unit of the second counter stage is replaced by the output signal of a separate logic circuit in which the signal which, up to now, has controlled, is combined with a signal from the fourth counter stage, and the signal which controls the auxiliary storage unit of the fourth counter stage is replaced by a signal from the first counter stage.
  • presetting signals are applied to the main storage units of the counter stages.
  • each of the main storage units has associated with it a supplementary component for the presetting, which component has the logic function (new) It is advantageous if the clear for presetting signal is the clear for presetting signal of the binary counter.
  • the outputs of the counter stages are connected to a converter. It is of advantage if the outputs of the converter put out the complement to the number 9.
  • FIGURE 1 having sections a, b and c, is a time plot showing various examples of the timed relationship of counting signals and auxiliary counting signals.
  • FIGURES 2a and 2b are pulse diagrams of the binary counter according to the present invention (except for FIGURE 12), leaving out of consideration any presetting.
  • FIGURE 3 is a circuit diagram of an arrangement for producing the clear for counting signal.
  • FIGURES 4a, 4b and 4c are circuit diagrams of different embodiments of main storage units for use with a counter according to the present invention.
  • FIGURE 5 is a circuit diagram of a non-presettable binary counter which incorporates main storage units according to FIGURE 4a.
  • FIGURE 6 is a circuit diagram of a modification of the circuit of FIGURE 5 in which the binary counter uses counter stages all having the same construction.
  • FIGURE 7 is a circuit diagram of an arrangement for producing a signal (2 which is formed from the counting and erasing signals.
  • FIGURE 8 is a circuit diagram of an arrangement for producing a signal e from the clear for counting signal, an output signal of the main storage unit of the lowest order binary digit, and the auxiliary counting signal.
  • FIGURE 9 is a circuit diagram of a non-presettable binary counter which incorporates main storage units according to FIGURE 4b.
  • FIGURE 10 is a circuit diagram of a non-presettable binary counter which incorporates main storage units according to FIGURE 4c.
  • FIGURE 11 is a pulse diagram for a non-presettable binary counter according to FIGURE 12.
  • FIGURE 12 is a circuit diagram of a non-presettable binary counter.
  • FIGURES 13a and 1312 are pulse diagrams for a presettable binary counter.
  • FIGURES 14a and 14b show circuit diagrams for arrangements for producing the clear for presetting signals.
  • FIGURE 15 is a circuit diagram of a presettable binary counter all of whose counter stages are similarly constructed.
  • FIGURE 16 is a pulse diagram showing the operation of the static counters, with particular reference being had to the presettable binary counter of FIGURE 15.
  • FIGURES 17a and 17b are pulse diagrams for a decimal counter developed from the binary counters of the preceding figures, without taking any presetting into consideration.
  • FIGURE 18 is a circuit diagrarn showing the first decade of a non-presettable decimal counter.
  • FIGURE 19 is a circuit diagram of another embodiment of a non-presettable decimal counter all of whose counter stages are similarly constructed.
  • FIGURE 20 is a circuit diagram showing an arrangement for producing the signals which are needed for the counter of FIGURE 19.
  • FIGURE 21 is a pulse diagram for a presettable decimal counter which has also been derived from the binary counters of the preceding figures.
  • FIGURE 22 is a circuit diagram of the first decade of a presettable decimal counter.
  • FIGURE 23 is a circuit diagram showing anot er embodiment of the first decade of a presettable decimal counter all of whose counter stages are similarly constructed.
  • FIGURES 24a and 2411 are circuit diagrams of arrangements for producing signals which are needed for the counter of FIGURE 23.
  • FIGURE 25 contains a Table 1 representing the counting steps for a decimal counter and a Table 2 showing the possible signal combinations of the outputs of the main storage units of the counter stages of one decade.
  • FIGURES 26, 27a and 2712 are circuit diagrams of arrangements which are controlled by a decimal counter and which produce signals for the backward counting.
  • FIGURES 28a and 2812 are circuit diagrams of con verters for the decimal counters.
  • FIGURE 29a shows, schematically, the arrangement of luminous elements by means of which numerals, as illustrated in FIGURE 2%, can be represented, while FIG- URE 290 contains a table showing the possible output combinations of a decade and the corresponding converted combinations according to FIGURE 2%.
  • FIGURES 30a and 30b are circuit diagrams of converters for the decimal counter of FIGURE 29.
  • FIGURE 31a contains a table showing the combination of signals within one decade.
  • FIGURES 31b and 310 are circuit arrangements for forming error signals.
  • a reliably operating static counter requires, besides the signals t; which are to be counted, auxiliary counting signals t which, as shown, for example, in FIGURE 1, are staggered or time-shifted with respect to the signals t i.e., the signals t do not appear at the same time as the signals t
  • the binary counter requires a counter stage for each binary digit.
  • Each counter stage requires two storage units, namely, a main storage unit and an auxiliary storage unit, which are set and erased by si nals, i.e., which store signals and which clear the signals, only when cer tain conditions are met.
  • the storage units are coupled galvanically. The storage units are set or erased only when the amplitude of the control signals applied to the storage units exceeds a predetermined value, the shape of the flanks of the signal pulses being of non consequence.
  • FIGURE 2a is a pulse diagram which shows the signals needed for controlling the counter, as well as the out put signals of four counter stages.
  • the pulses are shown as square wave pulses.
  • the signals can have the value or L.
  • the zero line or abscissa will be deemed to represent the value 0 while the lines overlying this abscissa line will be considered as representing the value L.
  • the signals to be counted are indicated as t while the further, auxiliary signals needed to control the counter are indicated as t These signals are staggered, and there are time intervals between them, as shown.
  • the signal Z2 is so synchronized that it can change only with the leading ilank of an auxiliary counting signal t
  • the output of the main storage unit of the counter stage for the lowest order binary digit is indicated at A the output for the main 8 storage unit of higher order digits at A A and so on.
  • the outputs of the auxiliary storage units are indicated at H H H and so on.
  • the indices 0, l, 2 represent the digital value 2, 2 2 of the binary digits.
  • auxiliary signals t are needed in addition to the signals I which signals t are used for producing further signals H.
  • the instants at which the H signals are stored and erased are so selected that, with the help of these signals, there will appear at the outputs A of the main storage units signal combinations corresponding to the natural binary code, and that the switching functions for the main as well as the auxiliary storage units will be as simple as possible.
  • the signal H shown in the diagram fulfills these conditions.
  • the signal H is equal to L during the time intervals indicated at b b
  • the switching function for the auxiliary storage unit which produces this signal is particularly simple.
  • the switching function for the output signal of the main storage unit and the auxiliary storage unit of the binary digit 2 without taking into consideration the erasing signal 1, is thus:

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US327585A 1962-11-28 1963-11-29 Static counter having main and aluxiliary stores and controlled by staggered counting and auxiliary counting signals Expired - Lifetime US3387118A (en)

Applications Claiming Priority (1)

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DEL43577A DE1170001B (de) 1962-11-28 1962-11-28 Statischer Impulszaehler mit Voreinstellung auf eine gegebene Zahl

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US (1) US3387118A (de)
CH (1) CH424864A (de)
DE (1) DE1170001B (de)
FR (1) FR1533901A (de)
GB (1) GB1072554A (de)
NL (3) NL143767B (de)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3511977A (en) * 1966-09-12 1970-05-12 Ibm Electronic counter
US3940596A (en) * 1973-06-11 1976-02-24 International Business Machines Corporation Dynamic logic counter
US20040009882A1 (en) * 1996-02-08 2004-01-15 Huntsman Petrochemical Corporation Structured liquids made using LAB sulfonates of varied 2-isomer content

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3308384A (en) * 1964-08-31 1967-03-07 Rca Corp One-out-of-n storage circuit employing at least 2n gates for n input signals

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2745006A (en) * 1952-08-18 1956-05-08 Jeffrey C Chu Binary counter
US2843320A (en) * 1956-12-21 1958-07-15 Beckman Instruments Inc Transistorized indicating decade counter
US3105897A (en) * 1959-02-10 1963-10-01 Philips Corp Binary parallel adder utilizing sequential and simultaneous carry generation
US3114883A (en) * 1961-08-29 1963-12-17 Ibm Reversible electronic counter
US3145293A (en) * 1961-06-05 1964-08-18 Ibm Bi-directional binary counter
US3193667A (en) * 1960-11-15 1965-07-06 Ferranti Ltd Error checking circuit for electronic counters
US3196258A (en) * 1960-06-02 1965-07-20 Ibm Counter step checking
US3234371A (en) * 1962-03-29 1966-02-08 Sperry Rand Corp Parallel adder circuit with improved carry circuitry
US3234373A (en) * 1962-03-07 1966-02-08 Ibm Fully checkable adder
US3264455A (en) * 1962-01-09 1966-08-02 Licentia Patents Verwaltungs G Binary counter

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2745006A (en) * 1952-08-18 1956-05-08 Jeffrey C Chu Binary counter
US2843320A (en) * 1956-12-21 1958-07-15 Beckman Instruments Inc Transistorized indicating decade counter
US3105897A (en) * 1959-02-10 1963-10-01 Philips Corp Binary parallel adder utilizing sequential and simultaneous carry generation
US3196258A (en) * 1960-06-02 1965-07-20 Ibm Counter step checking
US3193667A (en) * 1960-11-15 1965-07-06 Ferranti Ltd Error checking circuit for electronic counters
US3145293A (en) * 1961-06-05 1964-08-18 Ibm Bi-directional binary counter
US3114883A (en) * 1961-08-29 1963-12-17 Ibm Reversible electronic counter
US3264455A (en) * 1962-01-09 1966-08-02 Licentia Patents Verwaltungs G Binary counter
US3234373A (en) * 1962-03-07 1966-02-08 Ibm Fully checkable adder
US3234371A (en) * 1962-03-29 1966-02-08 Sperry Rand Corp Parallel adder circuit with improved carry circuitry

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3511977A (en) * 1966-09-12 1970-05-12 Ibm Electronic counter
US3940596A (en) * 1973-06-11 1976-02-24 International Business Machines Corporation Dynamic logic counter
US20040009882A1 (en) * 1996-02-08 2004-01-15 Huntsman Petrochemical Corporation Structured liquids made using LAB sulfonates of varied 2-isomer content

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FR1533901A (fr) 1968-07-26
DE1170001B (de) 1964-05-14
NL143767B (nl) 1974-10-15
NL301059A (de)
GB1072554A (en) 1967-06-21
NL301115A (de)
CH424864A (de) 1966-11-30

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