US2643820A

US2643820A - Circuit for adding binary numbers

Info

Publication number: US2643820A
Application number: US132581A
Authority: US
Inventors: Frederic C Williams; Arthur A Robinson; Kilburn Tom
Original assignee: National Research Development Corp UK
Current assignee: National Research Development Corp UK
Priority date: 1948-12-23
Filing date: 1949-12-12
Publication date: 1953-06-30
Anticipated expiration: 1970-06-30
Also published as: CH292119A; NL79243C; DE830119C; BE492883A; GB692853A; NL150648B; FR1003997A

Description

June 30, 1953 F. c. WILLIAMS ET AL 2,643,820

CIRCUIT FOR ADDING BINARY NUMBERS Filed Dec. 12, 1949 4 Sheets-Sheet 1 a 4 |ono| J I 10'0" Iotoobu OW IQO Q L ;I1 LL Co p resent two state circuit, 4

No CD or gate, 5

. I l not device, 6

k 1 gate 8 I F. 0. Williams I q A. A. Robinson T. Kilburn lnvenlom By 14 i l A Horneys June 30, 1953 F. c. WILLIAMS ETAL 2,643,820

CIRCUIT FOR ADDING BINARY NUMBERS Filed Dec. 12, 1949 4 Sheets-Sheet 2 l L A-B-O 0,0 CARRY STATE r- FLIP- FLOP A= B=O 5 7'7 one 9 B '1' OR OR 6 NOT GATE A-B =O F I 2 A-B =O OUTPUT ace: 'l ma R 24 man +70 V. AM, PULsEs B R 34 LDPG +70 W F. c. Williams A. A. Robinson T T. Kilburn C 34 Inventor s F I 4 -|sov Ff "w Attorneys June 30, 1953 i 'F, c. WILLIAMS ET AL 2,643,820

cmcun FOR ADDING BINARY NUMBERS Filed Dec. 12, 1949 4 Sheets-Sheet 3 DASH 'PULSES r I ig.6.

F. C. Williams ILA. Robinson 'rl Kilburn nvenfors Attorney;

June 30, 1953 F. c. WILLIAMS ETAL 2,643,820

CIRCUIT FOR ADDING BINARY NUMBERS Filed Dec. 12, 1949 4 Sheets-Sheet 4 ISOV -H.T.

I50 V H-T.

Fig.

F. S. Williams A. A. Robinson r. Knbum Inventors y I' M Attorneys Patented June 30, 1953 UNITED STATES ATENT OFFICE 2,643,820 I CIRCUIT FOR ADDING BINARY NUMBERS London, England Application December 12, 1949, Serial N 0. 132,581 In Great Brita-in December 23, 1948 14 Claims. (01. 235-41) This invention relates to circuit arrangements 7 for performing the process of addition of two numbers existing in binary-digital form in the series mode, i. e. each number being expressed dynamicallyas a temporal series of electrical pulse signals in its respective channel.

In circuit arrangements for performing the addition of two binary-digital numbers in the series mode, the addition process proceeds stepby-step, each step comprising the computation involved in adding the corresponding digits of like significance in the two numbers and any digit to be carried over from the addition of the preceding digits; the digits'of lowest significance: occurring first in the temporal series of pulses representing each number.

The rules governing the addition of binary numbers are set out in Table 1 which indicates the answer and carry digit to be carried to the next step of computation for the eight possible combinations of the

coeflicients

0 and 1 of the digits A, B to be added and the digit C carried from the preceding step of computation.

Table 1 A B or, A+B o The occurence of a carry digit in the process of addition of the corresponding digits of two binary-digital numbers requires that the coefficient of the carry digit must be retained during the period between the occurrence of adjacent digits in the numbers. In some forms of binarydigital adding circuits, such as that described in patent specification No. 19,967/48, the carry digit is produced in dynamic form, during the process of addition of two digits as a pulse which is then delayed by the interdigit period so that it is available simultaneously with the next digits in the numbers being added.

According to the present invention an electrical adding circuit arranged to receive successive pairs of coincident pulses A1 B1, A2 B2 etc. each pulse having either a first state representing the binary coeflicient 0 or 'a second state representing the binary coeflicient 1,? comprises separate input lines for receiving the A pulses andthe B pulses, comparison means including coincidence circuits connected thereto, control connections between said comparison means and an electronic switch and separate output circuits from said comparison means arranged to be selected by said switch, the arrangement being such that a control pulse produced by said comparison means when the pulses of one pair A1B1 fed thereto have like states sets the switch into a carry or no-carry condition in time for the arrival of the next pair A2132, the condition dependin upon whether pulses A1B1 have the second or first states respectively, and that one output circuit (selected by the switch when in the carry condition) is fed with a pulse having the second state each time a pulse pair of like states.

arrives at the comparison means, and another output circuit (selected by the switch when in the no-carry condition) is fed with a pulse having the second state each time a pulse pair of unlike states arrives at the comparison means.

It is thus a feature of the present inventionthat the carry digit arising as a result of a step,

of addition of two or more simultaneously occurring digits is not produced dynamically as an electrical-pulse but is represented by the condition of an electronic switch such as a two-state circuit forming part of the circuit arrangement} for the addition of the numbers comprising the Thus, on the: occurrence of any two simultaneously occurring digits which are to be added the condition of the I .switch is representative of the digit to be carried from the preceding step of addition, and enables the process-of addition of the two digits to be I performed, taking into account the coefficient of simultaneously occurring. digits.

the carry digit.

The digits to be added are represented dynami- I cally by electrical pulseshaving one or the otherof two states and of some finite duration (one state preferably being represented by the absence of a pulse) andiinaccuracy of timing of these spulses and alsovariations in the waveform at their leading edges are responsible for the uncertainty asto the result of the addition process during the initial stages of the digit pulses. I-Iowever, the result of an addition process, and thus the formation of a pulse-representing the result will be determined well before the ends of the pulses being added. The coehicient of the digit which is being carried from the preceding step of addition must remain undisturbed until any uncertainty in the current step ofaddition is resolved and also, if change during the digit period of the coefficient of the carry digit stored in the electronic switch would result in a simultaneous change in the coefiicient of the answer digit pulse, the coefficient of the carry digit must remain unchanged until the end of the answer digit pulse. It is a further feature of the invention therefore, that the electronic switch which stores the coefiicient of a carry digit developed during an, addition process is set to the appropriate condition by the trailing edge of a pulseproduced during the addition process.

In order that the nature of the invention may be more clearly understood, the rules of Table 1 may be recast in the form indicated in Table 2 which shows the coefiicient of the result A +,B' and the coefficient of the digit C to be carried,jfor the four possible combinations of the coefiicients of two binary digits, A, B, to be added for the two pre-existing conditions of the adding circuit, significant of'no carry digit and carry digit present.

Consideration of Table 2 will show that at the end of a step of the adding operation the adding circuit must be set, in preparation for the next step of addition, and irrespective of the preexisting carry condition, into the no carry digit condition if the coefficient of both digits A and B is and into the carry digit present condition if the coefficient of both digits A and B is 1. If the digits A and B have difiering coefficients (A=0, B=1 or vice versa) it can be seen that the carry condition of the adding circuit must be left undisturbed.

A further simplification in the form of Table 3 may be derived from Table 2 in order to indicate the coefficient of the answer (A-i-B) digit corresponding to the four combinations of the two possible pre-existing carry conditions of the adding circuit and the two conditions of the difference between the coeflicients of the digits A and B to be added. The coefficient of the difference between the digits A and B may be "0 or 1, expressed symbolically as A-B=0 and A-B=l,'the condition A-B=.0 existing when the coemcients of A and B are similar, i. e. both 0 or 1 and the condition A-B=1 existing when the coeflicients of A and B are dissimilar.

In order that the invention may be more clearly understood and readily carried into effect ref erence will now be made to the accompanying drawings in which:

1.2 +0.2 +1.2 1.2 +0.2%+in anity-five) as a train of negative-going pulses in the form it would be applied to the adding circuit shown in Fig. 2. The number is represented by four pulses representing the digits having the binary coefficient 1, the digits having the ccefiicient 0" being'represented by the absence of a pulse. In the following description these pulses will be called digit pulses whilst the term digit signal will be used to mean either a digit pulse (coefficient 1) or the absence of such pulse (coeffi-.

cientflo). Fig. 1(1)) shows the binary number 101011 (fifty-three) as it would be applied to the adding circuit of Fig. 2 and Fig. 1(c) shows the sum of the two numbers i. e. 0100011 (ninety-eight) as it would be obtained from the output of the adding circuit. There is utilised in the adding circuit of Fig. 2 regularly recurring positive pulses, hereinafter referred to as dash pulses, which are shown in Fig. 1(a). These dash pulses have the same duration as the digit pulses and one occurs in each digit period simultaneously with a digit pulse (if present).

An adding circuit according to this invention will now be described with reference to Fig. 2. The two trains of pulses representing the two numbers to be added (Figs. 1(a) and 1(b)) are fed simultaneously to

coincidence circuits

2 and 3, the timing being such that corresponding digit signals A and B (representing digits of the same significance in the two numbers) occur together. The circuit 2 is arranged to produce a negative output pulse if both the digit signals A and B represent 0. This negative output pulse is arranged to have the same timing and duration as the dash pulse occurring in the same digit period as the digit signals A and B. The circuit 3 is arranged'to give a negative output pulse if both the digit signals A and B are digit pulses representing 1. This negative output pulse also is arranged to have the same timing as the dash pulse occurring in the same. digit period as the digit signals A and B, i. e. it is'of the same duration, timing and polarity as the digit pulses -A and B. The outputs of the

circuits

2 and 3 when fed with the two pulse trains shown in Figs. 1(a) and 1(b) are shown respectively in Figs. 1(e) and 10).

The outputs of the

circuits

2 and 3 feed respectively the two inputs of a two-state device 4 (e. g. a double stability multivibrator circuit) which stores the carry digit C. An output pulse from the circuit 2 is arranged to set the twostate device Q into a no-carry condition, while anoutput pulse from the circuit 3 is arranged to set the two state devised into a carry condition. The two-state circuit 4 is arranged to be set up by the trailing edge of the pulses applied to it, so that its condition during the applied A and B digit signals is determined by previous A and B signals. The condition of the two-state circuit 4 when the two pulse trains shown in Fig. 1(a) and 10) are applied respectively to its two inputs is represented diagrammatically in Fig. 1(9), the lower level repre-.

Fig. 1(i).

senting the no carry conditionand'theupper level representing the carry condition.

The

circuits

2 and 3 also feed abuffer circuit' 5 (marked OR in Fig. 2) arranged to give an output negative pulse if it receives a pulse from either of them. This output pulse is arranged to be coincident with the input pulse. Thus an output pulse from the buffer circuit '5 during a digit period is significant of the condition A-B= while the absence of a pulse'from the buffer circuit during a digit periodis significant of the condition A-B=1. The output of the buffer circuit 5 when it receives pulses from the circuit 2 shown in Fig. 1(6) and from the circuit 3 shown in Fig. is shown in'Fig. 1(h) The buffer circuit 5 feeds a gate circuit 1 which is also fed with one output of the two-state circuit 4. The gate circuit 1 is held conducting when'the two-state circuit' l is in the carry condition and non-conducting when the two-' state circuit 5 is in the no-carry condition.' The output from the gate circuit 1 when it re-' ceives the output from the buffer circuit 5 shown in Fig. 1(h) with the two-state circuit 4 in a condition as represented in Fig. 1(9) is shown in cuit 9.

The buffer circuit 5 also feeds a negator device B (marked NOT in Fig. 2) which gives an output negative dash pulse if it does not receive a pulse from the buffer circuit 5 during a digit period; if it doe receive a pulse it gives no out- The gate circuit 1 feeds a buffer cirput pulse. Thus an output pulse from the negator 6 is significant of the condition A-B=1i The output from the negator 6 when it receives the output from the buffer circuit 5 shown in Fig. 1 '(h) is shown in Fig. 1(1). The negator 5 feeds a gate circuit 8 which is also fed with a second output of the two-state circuit 4. The gate cirwit 8 is held conducting when the two-state circuit is in the no carry condition and non-conducting when the two-stat circuit 4 is in the carry condition. The output of the gate ciri cuit 8 when it receives the pulses from the negator 6 shown in Fig. 1(9') with the two-state circuit in a condition as represented in Fig.'l.(g)- is .1

shown in Fig. 1(k). buifer circuit 9.

The buffer circuit 9 gives a negative output Th gate circuit 8 feeds the puls if it receives a pulse either from the gate circuit 1 or the gate circuit 8, and its output pulses represent the sum of thetwo numbers apthe buffer circuit 9 receives a pulse from the gate circuit 1 significant of the condition A-B=o plied to the input of the adding circuit. Thus when there is a carrydigit Co to be taken into account and it gives an output pulse representing 1 as required by Table 3. It also'receivesa pulse from th gate circuit 8 significant of the condition A-B=l when there i no carry digit CD to be taken into account and gives an output pulse representing 1 as required by Table .3.

' A circuit diagram of a preferred form of coincidence circuit} of Fig. 2 will now be described with reference to Fig. of the accompanying drawings. The circuit comprises a pentodevalve Vl3 having a resistance Rl3 in its cathode circuit whereby it operates as a cathode-follower. The control grid of the valve is connected to the cathodeof two diodes Dl3 and D23 and through a grid leak resistance R23 to a source of volts. The signals representing the two digits A and B are applied respectively to the anodes of the diodes Dl3 and D23 from a resting level of +70 volts, the negative-going pulses. represent;

ing 1's being of 55 volts amplitude. When A and B digit signals representing 1- occur simultaneously,i. e. both are pulses, both of the diodes DI3 and D23 are'rendered non-conducting and a negative output pulse, of duration equal to that of the digit pulses A and B, is developed across the cathode load resistance RI3. output pulse will b representative of the condition A=B=1. across the resistance R|3 if either the A or the B digit signal represent 0 since one of the diodes is then conducting and the potential on. the grid of the valve W3 is maintainedpositive.

A circuit diagram of a preferred form of coincidence circuit 2 of Fig. 2 will now be described with reference to Fig. 4 of the accompanying drawings. The circuit comprises a pentode valve Vl4 the control grid of which is connected The anode of the valve W4 is connected to the anode of a diode D14 the cathode of which is connected to a source of +70 volts, so that the.

potential on the anode of the valve Vl4 cannot rise above +70 volts. Positive-going dash pulses, Fig. 1(d) derived from a source DPG, are applied to the suppressor grid of th valve VM from a resting level of 60 volt which is sufficient to prevent the valve current reaching the anode. When both the A and B digit signals represent 0, the valve current remains turned on at its control grid and'a positive dash pulse on the suppressor grid will produce a negative output pulse at the anode of the valve which comes from a resting level of '70 volts. This negative output pulse is representative of the condition A=B=0. If either or both the A and B digit signals represent 1; i. evone or both is a negative pulse,

the valve current is cut off at the control grid and no negative pulse will be produced at the anode of the valv due to a dash pulse. Condensers C24 and 034 having a small capacity are inserted "in parallel respectively with the resistances R24 and R34 in order to improve the high frequency responseof the circuit. .Thus the time rate of fall of the potential on the control grid of the ,valve V14 du to the leading edge of a digit pulse will be made quicker.

A circuit diagram of a preferred form of bufier circuit 5 of Fig. 2 will now be described with reference to Fig. 5 of the accompanying drawings. The circuit comprises a pentode valve Vl5 having a resistance Rl5 in its cathode load 1 whereby it operates as a cathode follower. The" control grid of the valve W5 is connected through a grid leak, resistance R25 to a source of 2()0 volts' and also to the anodes of two diode Dl5 and D25. Negative pulses from the circuit 2 (Fig. 4) and thecircuit 3 (Fig. 3) are. applied respectively to the cathodes of the diodes 15 and p25, the pulses being off55 volts amplitude and coming froma resting level of '70 volts. On the occurrenc of a negative pulse the potential on the control grid of thevalve V15 falls and a negative output pulse of-approximately 55 volts amplitude is; developed across the cathod load resistance This negative No negative pulse is developed The resistances RM,

R15; This negative output pulse will be reprepotential divider RIB, R26, one end of which is.

connected to a potential of l50 volts and the other end of which is connected to the butler circuit' (Fig.5). .Negative pulses from the bnfier circuit 5 (Fig. 5) representative. of the condition A-B=O are applied to the control grid of the valve V16 via the resistance R26. and from a resting level of +70 volts. The resistances R116 and R26 are so proportioned, that the valve current is normally turned on at its control grid. Positive-going dash pulses, Fig. 1(d) are. fed to the suppressor grid of the valveVHi from a resting, level of 60 volts and. these will, in the absence of a negative pulse applied to the control grid from the buffer circuit 5 (Fig. 5), produce negative pulses across the anode load resistance R36 of the valve Vic. These: pulses will be representative of the conditions A-B=l. However if there is a negative pulse representative of A-B=0. applied to the control grid of V16,'the valve current is cut oil at the control grid for the duration 'of this pulse and the simultaneously occurring dash pulse applied to the suppressor grid will produce no effect at the anode of V56.

A circuit diagram of a preferred form of twostate device 4 of Fig. 2 will now be described with reference to Fig. 7 of. the accompanying drawings. The'circuit comprises two pentodevalves V1! and V2! which have their anodes and control grids cross-connected to form a conventional two-state trigger circuit, the valve Vi'l being conducting when the valve V2] is -non-conduct ing and vice-versa. The valves V1! and V2? have grid leak resistances RH and R21: respectively eachof which is connected to a. potential of l50 vol-ts. Negative pulses from the coincidence circuit 2 (Fig. 4) are applied to a. differentiating circuit C11, R31 which is connected to the anode of a diode DIT which is also con.- nected through a resistance R31 to a potential of -l(] volts. is connected to the control grid of the valve Vi? and thus to the anode of the valve V21. 'The diode DH is thus held non-conducting when the anode potential of the valve V21 isihigh (i. e. valve V2? is non-conducting) and is held con.- ducting when the anode potential of the. valve V2? is low (i. e. valve V21 is conduotingl A negative pulse from the circui-tl2. is difierentiated by the differentiating. circuit C11, R31. which produces a sharp negative pulse coincidently with the leading edge of the pulse and a sharp positive pulse coincidently with the trailing edge of the pulse. When the diode D11 is conducting (i. e.

valve V11 is non-conducting) these sharp pulses will be applied to the control grid of the valve V1 1. The sharp negative pulse will not affect the conductivity of the valve V11, but the sharp positive pulse will render the valve Vii conducting and thus the valve V21 non-conducting. Negativegoing pulses from the coincidence circuit 3 (Fig. 3) are similarly fed to a differentiating circuit 021, R21 which is connected to the valve v21 via a diode D21. Thus a negative pulse from the circuit 3 will render the valve V21 conducting and the valve V11 non-conducting. It can thus be seen that when the trigger circuit has been triggered by a pulse from the circuit 2, ile. has

The cathode of the diode: D1!

circuit (Fig. '7)

been triggered into the no carry condition, the

potential at the point a: at the anode of the valve Vl'1 will be low while the potential at the point y at the anode of the valve V21 will be high.

. When the trigger circuit has been triggered by a circuit 1 of Fig. 2 will now be described with reference to Fig. 8 of the accompanying drawings. The circuit comprises a pentode valve V18 and two diodes DlB and D28 connected in the same manner as the valve V13 and diode D13 and D23 'of Fig. 3. The anode of the diode D18 has negative pulses representing the condition A-B=O applied. to it from the bufier circuit 5. (Fig. 5)

while the anode of the diode D28 is connected to the anode: circuit of the valve V2! in the trigger Thus the-diode D28 is rendered non-conducting when the trigger circuit is in the-carry condition and any negative pulse applied to the diode D18 from the buffer circuit (Fig. '5). in this condition'will be developed across the cathode load resistance R18. If the trigger circuit: is in the no carry condition the diode D28 is conducting and a negative pulse applied to the diode D18 from the buffer circuit (Fig. 5) will not be developed across the cathode load resistanceRlB. a

The circuit diagram of a preferred form of gate circuit 8 of Fig. 2 will now be described with reference to Fig. 9 of the accompanying drawings.- The circuit comprises a pentode valve V19 and two diodes D19 and D29 similarly connected to the valve V18 and diodes D18 and D28 of Fig. 8. Negative pulses from the negator device 6 (Fig. 6) representative of the condition A-B=1 are applied to the anode of the diode D19 while the anode of the diode D29 is connected to the anode circuit of the valve V11 in'the trigger circuit of. Fig. '7. Thus the diode D29 is renderd non-conducting when the trigger circuit is in the no carry condition and any pulse applied to the anode of the diode D19 when the diode D29 is non-conducting will be developed across the cathode load resistance.

The buffer circuit 9 of Fig. 2 is preferably similar to the buffer circuit described with reference to Fig. 5 of the accompanying drawings.

It will be understood that the adding circuit senting the binary coefficient 1, said circuit comprising input lines for receiving signals of said pairs of signals, first and second comparison means each including coincidence circuits connected to said input lines, switch means, control connections between said comparison means and said switch means and separate output circuits from said comparison means arranged to be selected by said switch, said first comparison means including means responsive to the states of said input signals and including further means producing an output potential when said input signals are both of the representing state, said second comparison means including means responsive to the states of said input signals and including further means producing an output potential when said input signals are both of the 1 representing state, said switch means including means responsive to the output potentials of said first and second comparison means and being so arranged and constructed that it assumes a carry mode when an output potential is producedby said further means of said second comparison means and assumesa no-carry mode when an output potential is produced by said further means of said first comparison means, signal producing means coupled to said output circuits and producing signals of said first and second states, and means coupling said switch means to said output circuits, said output circuits including means responsive to the modes ofsaid switch means and permitting asignal ofwsaidfirst state from said signal producing means to pass when said switch means is in said fcarry mode and no output potential is produced by either of said first and second comparison means or when said switch means is in said no-carry mode and an output potential is produced by either of said first and second'comparison means and permitting a sighail of said second state from said signal producing means to pass when said switch means in it its no-carry mode'and' no outputpotential is produced'by either of said first and second'corm pari'sbn means 'or when said switch means is'in its carry mode and an output potential is produced by'either o'fsaid first and second comparis'onmeansl" 2. An'electrical adding circuit according to claim 1 wherein saidfirst and second comparison means are arranged to'provide output signals of saidsecond state and wherein said signal producing means comprises'a bufier circuit connected to the output of both'of said comparison means, separate output circuits from said buffer circuitand a-negator device in one of said output circuits so arranged and constructed that it produces an output signal'of'said second'state in the absence of an'output fromsaidbufier circuit'and vice-versa; '3."An electrical "adding circuit' according to claim 1 wherein'said switch means "comprises a two=statetrigger circuit connected to each of said coincidence circuits and adapted to supply switching pulses on changing itscondition from one mode totheother,-and two gate circuits responsive to such switching pulses, one con nected in each of said output circuits. a

"'4. An electrical adding circuit according to claim 1 wherein each connection between a coincidence circuit andthe trigger circuit includes adifierentiating network which servesto' enable the trailing edge of-a control pulse to be utilized to change the trigger circuit fromone state to the other;-- Y e r Y 5. 'Acircuit arrangement for producing, from two input pulse trains (A) and (B) each representing by its succession of pulses the digits of a binary number and fed thereto on separate input lines simultaneously digit by digit, a final output pulse train (A+B) representing by its succession of pulses the'digits of the binary sum of-the two numbers, said circuitlaarrangement comprising a first coincidence circuit supplied with each input pulse train for producing at its output a voltage pulse whenever the signalrepresenting the digit? occurs simultaneously in 10 each of the input pulse. trains .(A) and (B), a second coincidence circuit also supplied with. each input pulse train for producing at its output a voltage pulse whenever the signal representing the digit 0 occurs, simultaneously in each of the input pulse trains (A) and (B), a first gate circuit, a circuit means connecting the outputs of said first and second coincidence circuits to the input of said first gate circuit, an output line, circuit means connecting the output of c said first gate to said output line, a negator device producing an output signal representing the digit 1 in the absence of an input pulse thereto, circuit means connecting the outputs of said first and second coincidence circuits to the input of said negator device, a second gate circuit, circuit means connecting the output of said negator device to the input of said second gate, circuit means connecting the output of said second gate to said output line, electronic two-state switching means connected to said coincidence circuits so arranged and constructed as to be set by the output signals from said first or second coincidence circuits into a carry or a no-carry state respectively in time for the arrival of the next pair of digit signals in the input trains (A) and (B), circuit connections between the output of said electronic switching means and said first gate circuit, whereby said first gate circuit is placed in a condition to pass signals from its input to its output when said electronic switching means is in its "carry state, and circuit connections, between the output of said electronic switching means and said second gate circuit whereby said second gate circuit is placed in a condition to pass signals from its input to its output when said electronic switching means is in its no-carry state.

6. A circuit arrangement for producing, from two input pulse trains (A) and (B), each representing by its succession of pulses the digits of a binary number and fed thereto on separate input lines simultaneously digit by digit, a final output pulse train (A+B) representing by its succession of pulses the digits of the binary sum of the two numbers, said circuit arrangement comprising a first coincidence circuit supplied with each of said input pulse trains and producing at its output a separate signal representing ;the digit 1 whenever input signals 1 occurs simultaneously in each of the input pulse trains (A) and (B), a second coincidence circuit also supplied with each input pulse train for producing at its output a separate signal representing the digit 1 whenever the input signals 0 occur simultaneously in each of the input pulse trains (A) and (B), a first double input bufier circuit having its input connected respectively to the outputs ofboth first and second coincidence circuits, a first gate circuit, circuit means connecting the output of said first buffer circuit to the input of said first gate circuit, a second double input buffer circuit, circuit means connecting the output of said first gate circuit to one input of said second bufier circuit, an output line, circuit means connecting the output of said sec-- ond buffer circuit to said output line, a negator device producing a separate output signal representing the digit 1 in the absence of any input thereto, circuit means connecting the output of said first buffer circuit as a controlling input to said negator device, a second gate circuit, circuit means connecting the output of said negator device to the input of said second gate circuit, circuit means connecting the output of i1 saidsecond gate circuit to the second input of said'second buffer circuit, two-state electronic switching means connected to said first and said second coincidence circuits so arranged and constructed as to be set by the output signals of said coincidence circuits into a carry or no-carry state respectively in time for the arrival of the next pair of digit signals in the input trains (A) and (B), said switching means producing alternative output switching voltages on changing condition from one state .to the other, circuit connections betweenone output of said switching means and saidflfirst gate circuit whereby said first gate circuit is placed in a condition to pass signals from its input to its output when said switching means is in its carry state, and circuit connections between the other output of said switching means and said second gate circuit whereby said second gate circuit is placed in a'condition to pass signals from its input to its output when said switching means is in its nocarry state.

7'. A circuit arrangement for producing, from two input pulse trains (A) and (B) each representing by its succession of pulses the 1 digits of a binary number and fed thereto on separate input lines simultaneously digit by digit, a final output pulse train (A-l-B) representing by its succession of pulses the 1 digits of the binary sum of the. two numbers, said'circuit arrangement comprising a first-coincidence circuit supplied with each input pulse train for producing at its output a self-generated pulse representing the digit 1 whenever pulses representing the digit 1 occur simultaneously in the input pulse trains.(A) and (B), a second coincidence circuit also supplied with each input pulse train for producing at its output a self-generated pulse representing the digit 1 whenever pulses representing the digit 1 are absent simultaneously from both of the input pulse trains (A) and (B), a first buffer'circuit having input terminals connected to the outputs of said first and second coincidence circuits, a first gate circuit, circuit means connecting the output of said bufier circuit to the input of said first gate circuit, a second buffer circuit, circuit means connecting the output of said first gate circuit to the input of said second buffer circuit, an output line,=circuit means connecting the output of said second buffer circuit to said output line, a negator device producing a selfgenerated output pulse representing the digit 1 in the absence of an input pulse thereto, circuit means connecting the output f said first buiier circuit to the input of said negator device,

a second gate circuit, circuit means connecting the output of said negator device to the input of said second gate circuit, circuit means connecte ing the output of said second gate to the. input ofsaid second buffer circuit, an electronic twostateitrigger circuit having separate input ter-. minals connected respectively tolthe outputs of said first and second coincidence circuits so arranged and constructed as to be triggered by the output pulses from said first or said second coincidence circuits into a carry or a no-carry state respectively in time for thearrival 0f the next pair of digit signals in the input trains (A) and (B), said trigger circuit being adapted to produce at separate output terminals switching voltages representing its carry and no-carry state respectively, circuit connections between the carry pulse output terminals of said trigger circuit and the control terminals oi said first gate circuit for placing said first gate circuit in a condition to pass signals from its input to its out put when said trigger circuit is changed from its no-carry to its carry state, and circuit connections between the no-carry pulse output terminals of said trigger circuit and the control'terminals of said second gate circuit for placing said second gate circuit in a condition to passsignals from its input to its output when said trig-i ger circuit is changed from its carry to its no-' carry state. v

8. A circuit .arrangement'according to claimr'l in which each circuit connection betweena 00-.- incidence circuit and'said two-state trigger circuit includes a differentiating network for ens abling the trailing edges of the output pulses from said coincidence circuits to be utilized to effect triggering of said trigger circuit from one state to the other.

9. A circuit arrangement according to claim 7 in which said negator device comprises a thermionic tube having a cathode, an anode and at least three grid electrodes between said cathode and said anode, the output of said first bufier circuit being connected to that grid electrode nearest the cathode, and a source of regularly recurring positive pulses, having the same duration as digit representing pulses and timed to occur one in each digit period simultaneously with the digit pulse periods of said trains (A) and (B), connected to that grid nearest the anode, the ampli-' tude and polarity of the output pulses from said bufier circuit being such as to cut ofi the cathode current of said tube.

10. A circuit arrangement for producing an output train of pulses representative of the sum of two input trains Of pulses each ofwhich is representative of a number in the binary digital code and consists of a plurality of sequential digit-representing intervals wherein the binary digit value 1 is represented by the presence of a pulse of predetermined polarity and the binary digit value 0 is represented by the absence of such a pulse, said arrangement comprising separate input circuits respectively receiving the signal content of corresponding digit intervals of said input trains, a comparison circuit coupled to. said input circuits including pulse providing means operating when the signal contents of corresponding digit intervals are representative of the same binary digit value to produce a first out-- put pulse together with either a firstl control pulse in response to like input signal contents of one binary digit value or a second control pulse in response to like input signal contents of the other binary digit value, switching means coupled to said comparison means including means respon sive to said first and second control pulses and assuming a first switching mode in response td the termination of said first control pulses and assuming a second switching mode in responseto the termination of said second control pulses, a first output circuit coupled to said comparisoncircuit and to said switching means, a second output circuit coupled to said comparison circuit and to said switching means including pulsing means generating a second output pulse when said corresponding input signal contents are of different states, said first and second output circuits including meansresponsive to themodes or said switching means to permit said first output pulse to pass through said first output circuit only when said switching means is of said first mode and to permit said second output pulse to pass through said second output circuit only when said switching means is of said second mode.

11. A circuit arrangement for producing an output train of pulses representative of the sum of two input trains of pulses, each of said trains consisting of a predetermined number of sequential time intervals representing respectively the digit values of a binary number in ascending order of significance, the binary digit value "1 bein represented by the presence or a pulse of predetermined polarity during a digit-interval and the binary value being represented by the absence of such a pulse during a digit-interval, said arrangement comprising an input circuit simultaneously receiving the signal content of corresponding digit intervals of said input trains, pulse providing means coupled to said input circuit and responsive to the signal content states of corresponding digit intervals therein and produring a first output pulse when said corresponding signal content states are the same, switching means, having two possible modes, coupled to said input circuit, said switching means including means responsive to the signal content states of corresponding digit intervals in said input circuit and assuming one of said modes when both of said signal content states are representative of one of the two binary digit values and assuming the other of said modes when both of said signal content states are representative of the other of the two binary digit values, pulsing means coupled to said input circuit including means responsive to the signal content states of corresponding digit intervals in said input circuit and producing a second output pulse when said corresponding signal content states in said input differ, a first output circuit coupled to said pulse providing means, a second output circuit coupled to said pulsing means, and gating means in each of said output circuits coupled to said switching means, said gating means including means responsive to the modes of said switching means for selectively opening one of said gating means in response to one of said modes and opening the other of said gating means in response to the other of said modes.

12. A circuit as claimed in claim 11 in which said switching means is a bi-stable multivibrator. 13. A circuit as claimed in claim 12 in which said multivibrator produces control potentials in each of its modes of operation, said gating means each including a thermionic valve having a grid and an anode, said control potentials being coupled respectively to said grids and said output pulses being coupled respectively to said anodes. 14. An electrical binary adding circuit for providing an output pulse signal train representing the sum of two numbers each represented by an input pulse signal train, said signal trains each being characterised by the presence of either a 0 representing signal or a 1 representing signal in each of a plurality of sequential time intervals representative respectively of the component digits of the binary numbers concerned in ascending order of binary power and significance and the digit time intervals of each of the number representing signal trains being coincident and representative of the same binary power, said circuit comprising signal comparing means supplied with each of said input pulse signal trains and providing an output potential Whenever the coincident signals of said input trains are representative of the same binary digit value; together with a first control pulse while said coincident signals are each representative of the binary value 0 or a second control pulse while said coincident signals are each representative of the binary value 1, switching means operated by said first and second control pulses to assume a first switching mode upon termination of any first control pulse and to assume a second switching mode upon termination of any second control pulse, controlled signal providing means for providing output signals representative of either of said binary 0 and binary 1 digit values, an output circuit and control connections between said signal producing means, said switching means and said signal comparing means to cause supply to said output circuit of a 0 representing signal whenever said output potential occurs in time coincidence with said first mode of said switching means or when said second mode of said switching means occurs in the absence of said output potential and to cause the supply of a 1 representing signal to said output circuit whenever said output potential occurs in time coincidence with said second mode of said switching means or when said first switching inode occurs in the absence of said output potenial.

FREDERIC C. WILLIAMS.

ARTHUR A. ROBINSON.

TOM KILBURN.

References Cited in the file of this patent UNITED STATES PATENTS Number Name Date 2,404,250 Rajchman July 16, 1946 2,425,131 Snyder Aug. 5, 1947 2,429,227 Herbst Get. 21, 1947 2,429,228 Herbst Oct. 21, 1947 2,445,215 Flory July 13, 1948