US3387118A - Static counter having main and aluxiliary stores and controlled by staggered counting and auxiliary counting signals - Google Patents

Static counter having main and aluxiliary stores and controlled by staggered counting and auxiliary counting signals Download PDF

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US3387118A
US3387118A US327585A US32758563A US3387118A US 3387118 A US3387118 A US 3387118A US 327585 A US327585 A US 327585A US 32758563 A US32758563 A US 32758563A US 3387118 A US3387118 A US 3387118A
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counter
counting
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Petzold Dieter
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
    • H03K23/665—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by presetting

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  • ABSTRACT OF THE DISCLOSURE A multiple-digit static counter each of whose stages has main and auxiliary stores and which is controlled by counting signals and auxiliary counting signals, the latter being staggered with respect to and timely spaced from the former.
  • the instants at which the main stores, at whose outputs there appears the count of the respective digit, are set and erased, are controlled by the respective auxiliary store which has different circuit conditions at the two instants and, in addition, by the counter stage of the preceding digit and/or by the counting and/ or auxiliary counting signals.
  • there is built into the counter a tolerance for differences in the characteristics of the semiconductor elements forming part of the counter, in that differences in the switching times of the individual circuit components will not cause errors.
  • the present invention relates to a static counter.
  • the object of the present invention to provide a counter which overcomes the abovementioned drawbacks, and the present invention therefore resides in a trouble-free static counter incorporating Patented June 4, 1968 galvanically coupled counter stages, which counter has no discontinuities, and which counter is, moreover, substantialy proof against external interference.
  • the present invention relates to a static counter which is able to count forward or backward and is capable of being preset to a desired binary number, which counter can be converted to a decimal counter which is able to count forward or backward and can, if desired, be made capable of being preset to a desired decimal number, which counter, moreover, can have applied to it counting signals and auxiliary counitng signals of any shape, the auxiliary counting signals being displaced, with respect to time, relative to the counting signals, i.e., the counting signals and the auxiliary counting signals are timely spaced from each other.
  • the main storage unit of each binary digit changes its circuit condition during the counting operation only at the instant of a counting signal (t and the corresponding auxiliary storage unit changes its condition at the instant of an auxiliary counting signal (t or a counting signal (13 but not at the same instant as the main storage unit.
  • the main and auxiliary storage units will each have at least two logic circuits, and according to a further feature of the present invention, the input stages of the auxiliary and main storage units are AND-circuits.
  • the auxiliary storage unit has at least two input AND-circuits and the main storage unit has at least three input AND-circuits each of which controls an OR/NOT-circuit whose output, in turn, is connected to a NOT-circuit.
  • A the output signal of a main storage unit
  • an erase or reset signal is applied to the counter stages. It is advantageous if this erase signal is composed of at least two erase signals, for example, according to.
  • the main storage units of the counter stages have the logical function (t C QH98CT)l (A ?A Q (t &H &F v (A di-L811) v (A,,&7 &1) :A n and the auxiliary storage unit of the counter have the logical function It is advantageous if there is introduced into the counter stage of the lowest order binary digit a counting command signal with the help of which it is decided whether the counter is to count the counting signals.
  • the main storage unit of the counter stage of the lowest binary digit has the logical switching function and the corresponding auxiliary storage unit has the logical switching function It is, furthermore, advantageous, if a clear for counting signal is applied to the counter stage of the lowest binary digit, which clear for counting signal is so synchronized by a counting command signal that may appear at any instant as to appear and disappear at the start of an auxiliary signal.
  • the main storage units have the logic functions
  • the main storage units of the counter stages are controlled, following an erase command, by presetting signals in order to obtain a presetting of the counter to a given binary number. Therefore, each of the main storage units has associated with it a logic circuit which is controlled by the presetting si nal and a clear for presetting signal.
  • This logic circuit preferably has the function (k &f)n:O, l, 2
  • the preset clearin signal appears after the erasing and disappears with the clearing for counting, and reappears only after a further erasing.
  • a storage unit is provided for producing the clear for presetting signal, which storage unit has the logic function 11101185 :m and forms a signal which controls a logic stage connected to the output of the storage unit which has a further in-- put for the erase signal and itself has the logic function fed back from the fourth counter stage to the third counter stage, or a signal from the fourth counter stage is fed back to the second counter Stage and a signal of the first counter stage is applied to the fourth counter stage.
  • the signals needed for the decimal conversion replace the signals controlling the binary counter, or the signals needed for the decimal conversion are combined with the signals which, up to now, have controlled the binary counter, in separate logic circuits whose output signals replace the control signals used up to now, with the arrangement being such that the construction of the binary counter stages remains unchanged.
  • the auxiliary storage units of the second and third counter stages have applied to them a further signal from the fourth counter stage. It is of advantage to provide the auxiliary storage units of the second and third counter stages each with a logic input stage, for the (i-l-lfi decade (value lO has the logic function According to a further feature, the manner in which the auxiliary storage units of the second and third counter stages are controlled is modified, in comparison to the binary counter, in that the signal which, up to now, has controlled each counter stage is replaced by the output signal of a separate logic circuit in which the signal which up to now was the controlling signal is combined with a signal from the fourth counter stage.
  • the main storage unit of the second counter stage has applied to it a signal from the fourth counter stage and the auxiliary storage unit of the fourth counter stage has applied to it a signal from the first counter stage. It is of advantage if there is additionally applied to the input stage of the main storage unit of the second counter stage of the decade (value a signal from the auxiliary storage unit of the fourth counter stage, and if, in an input stage of the auxiliary storage unit of the fourth counter stage, the signal of the auxiliary storage unit of the preceding counter stage is replaced by the signal of the auxiliary storage unit of the first counter stage.
  • one of the two signals which, up to now, have controlled the main storage unit of the second counter stage is replaced by the output signal of a separate logic circuit in which the signal which, up to now, has controlled, is combined with a signal from the fourth counter stage, and the signal which controls the auxiliary storage unit of the fourth counter stage is replaced by a signal from the first counter stage.
  • presetting signals are applied to the main storage units of the counter stages.
  • each of the main storage units has associated with it a supplementary component for the presetting, which component has the logic function (new) It is advantageous if the clear for presetting signal is the clear for presetting signal of the binary counter.
  • the outputs of the counter stages are connected to a converter. It is of advantage if the outputs of the converter put out the complement to the number 9.
  • FIGURE 1 having sections a, b and c, is a time plot showing various examples of the timed relationship of counting signals and auxiliary counting signals.
  • FIGURES 2a and 2b are pulse diagrams of the binary counter according to the present invention (except for FIGURE 12), leaving out of consideration any presetting.
  • FIGURE 3 is a circuit diagram of an arrangement for producing the clear for counting signal.
  • FIGURES 4a, 4b and 4c are circuit diagrams of different embodiments of main storage units for use with a counter according to the present invention.
  • FIGURE 5 is a circuit diagram of a non-presettable binary counter which incorporates main storage units according to FIGURE 4a.
  • FIGURE 6 is a circuit diagram of a modification of the circuit of FIGURE 5 in which the binary counter uses counter stages all having the same construction.
  • FIGURE 7 is a circuit diagram of an arrangement for producing a signal (2 which is formed from the counting and erasing signals.
  • FIGURE 8 is a circuit diagram of an arrangement for producing a signal e from the clear for counting signal, an output signal of the main storage unit of the lowest order binary digit, and the auxiliary counting signal.
  • FIGURE 9 is a circuit diagram of a non-presettable binary counter which incorporates main storage units according to FIGURE 4b.
  • FIGURE 10 is a circuit diagram of a non-presettable binary counter which incorporates main storage units according to FIGURE 4c.
  • FIGURE 11 is a pulse diagram for a non-presettable binary counter according to FIGURE 12.
  • FIGURE 12 is a circuit diagram of a non-presettable binary counter.
  • FIGURES 13a and 1312 are pulse diagrams for a presettable binary counter.
  • FIGURES 14a and 14b show circuit diagrams for arrangements for producing the clear for presetting signals.
  • FIGURE 15 is a circuit diagram of a presettable binary counter all of whose counter stages are similarly constructed.
  • FIGURE 16 is a pulse diagram showing the operation of the static counters, with particular reference being had to the presettable binary counter of FIGURE 15.
  • FIGURES 17a and 17b are pulse diagrams for a decimal counter developed from the binary counters of the preceding figures, without taking any presetting into consideration.
  • FIGURE 18 is a circuit diagrarn showing the first decade of a non-presettable decimal counter.
  • FIGURE 19 is a circuit diagram of another embodiment of a non-presettable decimal counter all of whose counter stages are similarly constructed.
  • FIGURE 20 is a circuit diagram showing an arrangement for producing the signals which are needed for the counter of FIGURE 19.
  • FIGURE 21 is a pulse diagram for a presettable decimal counter which has also been derived from the binary counters of the preceding figures.
  • FIGURE 22 is a circuit diagram of the first decade of a presettable decimal counter.
  • FIGURE 23 is a circuit diagram showing anot er embodiment of the first decade of a presettable decimal counter all of whose counter stages are similarly constructed.
  • FIGURES 24a and 2411 are circuit diagrams of arrangements for producing signals which are needed for the counter of FIGURE 23.
  • FIGURE 25 contains a Table 1 representing the counting steps for a decimal counter and a Table 2 showing the possible signal combinations of the outputs of the main storage units of the counter stages of one decade.
  • FIGURES 26, 27a and 2712 are circuit diagrams of arrangements which are controlled by a decimal counter and which produce signals for the backward counting.
  • FIGURES 28a and 2812 are circuit diagrams of con verters for the decimal counters.
  • FIGURE 29a shows, schematically, the arrangement of luminous elements by means of which numerals, as illustrated in FIGURE 2%, can be represented, while FIG- URE 290 contains a table showing the possible output combinations of a decade and the corresponding converted combinations according to FIGURE 2%.
  • FIGURES 30a and 30b are circuit diagrams of converters for the decimal counter of FIGURE 29.
  • FIGURE 31a contains a table showing the combination of signals within one decade.
  • FIGURES 31b and 310 are circuit arrangements for forming error signals.
  • a reliably operating static counter requires, besides the signals t; which are to be counted, auxiliary counting signals t which, as shown, for example, in FIGURE 1, are staggered or time-shifted with respect to the signals t i.e., the signals t do not appear at the same time as the signals t
  • the binary counter requires a counter stage for each binary digit.
  • Each counter stage requires two storage units, namely, a main storage unit and an auxiliary storage unit, which are set and erased by si nals, i.e., which store signals and which clear the signals, only when cer tain conditions are met.
  • the storage units are coupled galvanically. The storage units are set or erased only when the amplitude of the control signals applied to the storage units exceeds a predetermined value, the shape of the flanks of the signal pulses being of non consequence.
  • FIGURE 2a is a pulse diagram which shows the signals needed for controlling the counter, as well as the out put signals of four counter stages.
  • the pulses are shown as square wave pulses.
  • the signals can have the value or L.
  • the zero line or abscissa will be deemed to represent the value 0 while the lines overlying this abscissa line will be considered as representing the value L.
  • the signals to be counted are indicated as t while the further, auxiliary signals needed to control the counter are indicated as t These signals are staggered, and there are time intervals between them, as shown.
  • the signal Z2 is so synchronized that it can change only with the leading ilank of an auxiliary counting signal t
  • the output of the main storage unit of the counter stage for the lowest order binary digit is indicated at A the output for the main 8 storage unit of higher order digits at A A and so on.
  • the outputs of the auxiliary storage units are indicated at H H H and so on.
  • the indices 0, l, 2 represent the digital value 2, 2 2 of the binary digits.
  • auxiliary signals t are needed in addition to the signals I which signals t are used for producing further signals H.
  • the instants at which the H signals are stored and erased are so selected that, with the help of these signals, there will appear at the outputs A of the main storage units signal combinations corresponding to the natural binary code, and that the switching functions for the main as well as the auxiliary storage units will be as simple as possible.
  • the signal H shown in the diagram fulfills these conditions.
  • the signal H is equal to L during the time intervals indicated at b b
  • the switching function for the auxiliary storage unit which produces this signal is particularly simple.
  • the switching function for the output signal of the main storage unit and the auxiliary storage unit of the binary digit 2 without taking into consideration the erasing signal 1, is thus:

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Description

June 4, 1968 D. PETZOLD 3,387,118
STATIC COUNTER HAVING MAIN AND AUXILIARY STORES AND CONTROLLED BY STAGGERED COUNTING AND AUXILIARY COUNTING SIGNALS Filed Nov. 29, 1963 16 Sheets-Sheet 1 IIIF Tnl Jnvenlar: Duder Petzold.
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STATIC COUNTER HAVING MAIN AND AUXILIARY STORES AND CONTROLLED BY STAGGERED COUNTING AND AUXILIARY COUNTING SIGNALS Filed Nov. 29, 1963 16 Sheets-Sheet 2 WW 2 *2 Fi 3 I I Fig.4a FIgAb Fi .4-,,
Jnven/on Dialer PeizoLcL JJW W51" RUORNEVS June 4, 1968 D. PETZOLD 3,387,118
STATIC COUNTER HAVING MAIN AND AUXILIARY STORES AND CONTROLLED BY STAGGERED COUNTING AND .AUXILIARY COUNTING SIGNALS Filed Nov. 29, 1963 16 Sheets-Sheet 5 Fly. 5
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Jnrenfor' tDleier Qbsld RTI'ORNBIS June 4, 1968 PETZOLD 3,387,118
sTATIC COUNTER HAV MAIN AND AUXILIARY STORES AND CONTROLLED BY STAGGERED COUNTING AND AUXILIARY CoUNTINC SIGNALS Filed Nov. 29, 1963 16 Sheets-Sheet 4 Fig.9
Jnrenfan Dial: a! Pztzoli June 4, 1968 D. PETZOLD 3,337,118
STATIC COUNTER HAVING MAIN AND AUXILIARY STORES AND CONTROLLED BY STAGGERED COUNTING AND AUXILIARY COUNTING SIGNALS Filed Nov. 29, 1963 16 Sheets-Sheet 5 Jnremor: :Dieier Pdzo BTW b" AT ORNEYS J 4, 1968 D. PETZOLD STATIC COUNTER HAVING MAIN AND AUXILIARY STORES AND CONTROLLED BY STAGGERED COUNTING AND AUXILIARY COUNTING SIGNALS l6 Sheets-Sheet 6 Filed Nov. 29, 1963 Dig-$135M 5W June 4, 1968 D, PETZOLD 3,387,118
STATIC COUNTER HAVING MAIN AND AUXILIARY STORES AND CONTROLLED BY STAGGERED COUNTING AND AUXILIARY COUNTING SIGNALS Filed Nov. 29, 1963 16 Sheets-Sheet '7 Fl:g./4a Fig/4b Jm/e for- ID u'ete r RFORNEYS June 4, 1968 D. PETZOLD 3,387,118
STATIC COUNTER HAVING MAIN AND AUXILIARY STORES AND CONTROLLED BY STAGGERED COUNTING AND AUXILIARY COUNTING SIGNALS Filed Nov. 29, 1963 16 Sheets-Sheet 8 1n nlor- Diem mu RTI'OFWEY June 4, 1968 PETZOLD 3,387,118
STATIC COUNTER HAVING MAIN AND AUXILIARY STORES AND CONTROLLED BY STAGGERED COUNTING AND AUXILIARY COUNTING SIGNALS Filed Nov. 29, 1963 16 Sheets-Sheet 9 ATTORNEYS June 4, 1968 0. PETZOLD 3,387,118
STATIC COUNTER HAVING MAIN AND AUXILIARY STORES AND CONTROLLED BY STAGGEHED COUNTING AND AUXILIARY COUNTING SIGNALS Filed Nov. 29, 1963 l6 Sheets-Sheet 10 Fig. /8
Jnrentan inter Petzou Amman June 4, 1968 PETZOLD 3,387,118
STATIC COUNTER HAVING MAIN AND AUXILIARY STORES AND CONTROLLED BY STAGGERED COUNTING AND AUXILIARY COUNTING SIGNALS Filed Nov. 29, 1963 16 Sheets-Sheet ll Fig.2!) If A; 25'
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Dieter 'Palzohi ByMQ K ATTORNEYS June 4. 1968 D. PETZOLD STATIC COUNTER HAVING MAIN AND AUXILIARY STORES AND CONTROLLED BY STAGGERED COUNTING AND AUXILIARY COUNTING SIGNALS l6 Sheets-Sheet 12 Filed Nov. 29, 1963 Jnrenfon :Duater Pa? B ENEVT.
June 4, 1968 D. PETZOLD 3,387,118
STATIC COUNTER HAVING MAIN AND AUXILIARY STORES AND Filed NOV. 29, 1963 CONTROLLED BY STAGGERED COUNTING AND AUXILIARY COUNTING SIGNALS l6 Sheets-Sheet 1 5 Fig.23
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June 4, 1968 D. PETZOLD 3,387,118
STATIC COUNTER HAVING MAIN AND AUXILIARY STORES AND CONTROLLED BY STAGGERED COUNTING AND AUXILIARY COUNTING SIGNALS Filed Nov. 29, 1963 16 Sheets-Sheet l4 a /4 9 a 3 TABLE! OOOL OLLL LLLO L000 L000, UOLO 7 l4 8 8 0 0 0L L 000 LLL O OLL L L 000 OUUL I 8 l4 '7 8 I OOIOL LOgOL LLILO OL6LU L0600 00000 0 0 L 0 0 000 L LOL L L L L ULLL L 00L 2 0 1% l5 7 9 U 0 L U UUOL L L 0L L L L 0 0L LL L 000 2 I 13 I4 7 a it..iiiii A3 A2 A? A0 B3 B2 5780 2 09232 6 OLOULLL U LLOLLO 01.00 OLOL 0LULOL00 ULLOUULL 50503 30? g- LO0L000-0 A 434435436130 5 z a i z 6 9 5 :3
.7nrem0/=- flleluPelzo l ArroRNEYs June 4, 1968 D. PETZOLD STATIC COUNTER HAVING MAIN AND AUXILIARY STORES AND CONTROLLED BY STAGGERED COUNTING AND AUXILIARY COUNTING SIGNALS l6 Sheets-Sheet 15 Filed NOV. 29, 1963 LOLOOOLOLO LLL LUOLLL LOOOLLLOLL LDLLOLLOLL OOLLLLLOLL LOLLOLLLLL OLOLOLOLOL OOLLOOLLUO OOOOLLLLUO OOUOOOOOLL Fig.3lc
OLOLOLOLULOLOLO-L OOLLOnULLOOLLOOLL OOOOLLILLOOOOLLLL OOUUOOOOLLLLLLLL Jnrenlar: Dakar I) eizokl B3: )1 mi??? June 4, 1968 PETZOLD 3,387,118
STATIC COUNTER HAVING MAIN AND AUXILIARY STORES AND CONTROL ED BY STAGGERED COUNTING AND AUXILIARY COUNTING SIGNALS Filed Nov. 29, 1963 16 Sheets-Sheet l6 Jm tor- Di. eter etZOlll AMA w I flrroausvs United States Patent "ice 3,387,118 STATIC COUNTER HAVING MAIN AND AUX- ILIARY STORES AND CONTROLLED BY STAGGERED COUNTING AND AUXILIARY COUNTING SIGNALS Dieter Petzold, Berlin-Nenkolln, Germany, assignor to Licentia Patent-Verwaltungs-GmbH, Frankfurt am Main, Germany Filed Nov. 29, 1963, Ser. No. 327,585 Claims priority, application Germany, Nov. 28, 1962, 43,577, 43,578 25 Claims. (Cl. 235-92) ABSTRACT OF THE DISCLOSURE A multiple-digit static counter each of whose stages has main and auxiliary stores and which is controlled by counting signals and auxiliary counting signals, the latter being staggered with respect to and timely spaced from the former. The instants at which the main stores, at whose outputs there appears the count of the respective digit, are set and erased, are controlled by the respective auxiliary store which has different circuit conditions at the two instants and, in addition, by the counter stage of the preceding digit and/or by the counting and/ or auxiliary counting signals. As a result, there is built into the counter a tolerance for differences in the characteristics of the semiconductor elements forming part of the counter, in that differences in the switching times of the individual circuit components will not cause errors.
The present invention relates to a static counter.
In recent years, electronic counting has become increasingly more important and is used, to a very large extent, in the measuring, controlling and regulating arts. The hardware involved is in the nature of electronic counters whose function it is to count serially, i.e., successively, applied signals, generally in the form of pulses, and to put out the count in parallel representation. That is to say, the incoming pulses arrive one after the other, or serially, while all of the digits of the counted result appear simultaneously at the output of the counter. i.e., in timed parallel relationship. In the case of binary counters, for example, each binary digit has a counter stage associated with it.
Most of the electronic counters which have been developed operate on the dynamic principle. The individual counter stages of dynamic counters consist of bistable circuits which are capacitatively coupled with each other. The input signals which excite these stages have to meet certain requirements, particularly insofar as the steepness of the flanks is concerned. In addition to requiring pulses of special configuration, dynamic counters have the additional drawback that they are susceptible to external disturbances.
There exist other counters which incorporate galvanically coupled step-down stages, whose first stage is controlled by the counting signal and its negate, and which puts out signals which have been stepped down in a 2:1 ratio. The output signals are applied to further stages where they are again stepped down in a ratio of 2:1. Such counters have the drawback that the changeover from one circuit condition to the other does not always take place reliably, due to the presence of discontinuities. Instead the counter stages may assume the incorrect circuit condition.
It is, therefore, the object of the present invention to provide a counter which overcomes the abovementioned drawbacks, and the present invention therefore resides in a trouble-free static counter incorporating Patented June 4, 1968 galvanically coupled counter stages, which counter has no discontinuities, and which counter is, moreover, substantialy proof against external interference.
It is another object of the present invention to provide a counter which can readily be so modified that it can be preset to a given binary number.
It is still another object of the present invention to provide a counter which, with few additional components, can be converted into a decimal counter, it being another object of the present invention that such a decimal counter, too, can be modified so as to enable it to be preset to any desired decimal number.
It is a further object of the present invention to provide counters of the above type, all of which are adapted to count forward or backward, and, moreover, are suscep tible to being so arranged that all of the counter stages are alike, thereby enabling use of simple modular units.
With the above objects in view, the present invention relates to a static counter which is able to count forward or backward and is capable of being preset to a desired binary number, which counter can be converted to a decimal counter which is able to count forward or backward and can, if desired, be made capable of being preset to a desired decimal number, which counter, moreover, can have applied to it counting signals and auxiliary counitng signals of any shape, the auxiliary counting signals being displaced, with respect to time, relative to the counting signals, i.e., the counting signals and the auxiliary counting signals are timely spaced from each other. More particularly, the present invention resides in the fact that the counter stage of each binary digit comprises (l) a main storage unit which puts out the counted result of the respective binary digit and (2) an auxiliary storage unit; the two instants at which the setting (i.e., storing) and the resetting (i.e., erasing) of the main storage unit occur are fixed by the respective auxiliary storage unit which, at these instants of time, has different circuit conditions (i.e., either 0 or L, where L=binary 1) and by at least one counter stage of the preceding binary stages or a counting signal or an auxiliary counting signal.
According to a further feature of the invention, the main storage unit of each binary digit changes its circuit condition during the counting operation only at the instant of a counting signal (t and the corresponding auxiliary storage unit changes its condition at the instant of an auxiliary counting signal (t or a counting signal (13 but not at the same instant as the main storage unit. In practice, the main and auxiliary storage units will each have at least two logic circuits, and according to a further feature of the present invention, the input stages of the auxiliary and main storage units are AND-circuits. It is of advantage if the auxiliary storage unit has at least two input AND-circuits and the main storage unit has at least three input AND-circuits each of which controls an OR/NOT-circuit whose output, in turn, is connected to a NOT-circuit.
According to a further feature, the output of the cooperating auxiliary storage unit changes its condition only once While the output signal of the main storage unit is L. It is advantageous if the number of times which the output signal of the corresponding auxiliary storage unit changes its state is an odd number of times, and is equal to at least 2 -l(n=0, 1, 2 while the output signal of the main storage unit of the n counter stage (whose digital value is 2 -1) is L.
According to a further feature, the auxiliary storage unit of the lowest order binary digit produces signals in dependence on the count (0 or L) of the main storage unit of the same binary digit, and the auxiliary storage units in the following binary digits produce signals in deand if the auxiliary storage units of the counter stages having logical functions where t =the counting signal which controls the main storage units,
t =the auxiliary counting signal which controls the auxiliary storage units,
A=the output signal of a main storage unit,
H=the output signal of an auxiliary storage unit, and
According to yet another feature of the present invention, an erase or reset signal is applied to the counter stages. It is advantageous if this erase signal is composed of at least two erase signals, for example, according to.
the logic function 1 vl =l, so that counters which are a part of an arrangement to which further storage units belong, can be erased independently of the storage units which do not belong to the counters. This can be done, for example, by applying to the storage units of the counter the composite erase reset signal 1 or I, depending on the formation of the signal, while, for example 1 or T is applied to the other storage units of the arrangement.
According to a further feature, the main storage units of the counter stages have the logical function (t C QH98CT)l (A ?A Q (t &H &F v (A di-L811) v (A,,&7 &1) :A n and the auxiliary storage unit of the counter have the logical function It is advantageous if there is introduced into the counter stage of the lowest order binary digit a counting command signal with the help of which it is decided whether the counter is to count the counting signals. According to a further feature of the present invention, therefore, the main storage unit of the counter stage of the lowest binary digit has the logical switching function and the corresponding auxiliary storage unit has the logical switching function It is, furthermore, advantageous, if a clear for counting signal is applied to the counter stage of the lowest binary digit, which clear for counting signal is so synchronized by a counting command signal that may appear at any instant as to appear and disappear at the start of an auxiliary signal.
According to a further feature of the present invention, there is formed, from a counting command signal appearing at any time and with the help of a storage unit, a signal which, when 1:0, is produced when the first counting signal following the counting command signal=L appears, and which disappears when the erase command 1=L or when the first counting signal following the disappearance of the counting command signal appears; this signal controls a further storage unit which is set with the first auxiliary counting signal appearing after the signal Z =L, this storage unit being erased with the erase command. signal 1=L or with the first auxiliary counting signal following the disappearance of the 2;, signal. It is of advantage if the storage unit for the signals has the logical function r l (Z &z&T)v(z &? 'tl):z 1 2) 2 1) 2 2 2 According to a further feature of the present invention, the main storage unit of the lowest order binary digit has the logic function and the corresponding auxiliary storage unit has the logic function (2285A 0) v l-l az a/r 0) v n az ar =H0 It is of advantage if the counter stage of the lowest order binary digit is divided into two parts one of which corresponds to the remaining counter stages and the other of which is an input part, According to a further feature, therefore, the auxiliary storage unit of the lowest order binary digit has the logic function (r &A )v(H &e) =H where e is formed from the switching function it is of advantage if at least two signals which, up to now, have been applied to all of the main or auxiliary storage units of the counter stages, are combined in a special supplementary circuit whose output signal replaces the control signals. According to a further feature of the present invention, therefore, the main storage units have the logic functions According to a further feature, the main storage units of the counter stages are controlled, following an erase command, by presetting signals in order to obtain a presetting of the counter to a given binary number. Therefore, each of the main storage units has associated with it a logic circuit which is controlled by the presetting si nal and a clear for presetting signal. This logic circuit preferably has the function (k &f)n:O, l, 2
According to a further feature, the preset clearin signal appears after the erasing and disappears with the clearing for counting, and reappears only after a further erasing. Preferably, a storage unit is provided for producing the clear for presetting signal, which storage unit has the logic function 11101185 :m and forms a signal which controls a logic stage connected to the output of the storage unit which has a further in-- put for the erase signal and itself has the logic function fed back from the fourth counter stage to the third counter stage, or a signal from the fourth counter stage is fed back to the second counter Stage and a signal of the first counter stage is applied to the fourth counter stage. In practice, the signals needed for the decimal conversion replace the signals controlling the binary counter, or the signals needed for the decimal conversion are combined with the signals which, up to now, have controlled the binary counter, in separate logic circuits whose output signals replace the control signals used up to now, with the arrangement being such that the construction of the binary counter stages remains unchanged.
According to a further feature, the auxiliary storage units of the second and third counter stages have applied to them a further signal from the fourth counter stage. It is of advantage to provide the auxiliary storage units of the second and third counter stages each with a logic input stage, for the (i-l-lfi decade (value lO has the logic function According to a further feature, the manner in which the auxiliary storage units of the second and third counter stages are controlled is modified, in comparison to the binary counter, in that the signal which, up to now, has controlled each counter stage is replaced by the output signal of a separate logic circuit in which the signal which up to now was the controlling signal is combined with a signal from the fourth counter stage. It is of advantage if the separate logic circuit for the second counter stage has the function 1 s )=q1 or 1 s 1 and if the logic circuit for the third counter stage has the function According to a further feature, the main storage unit of the second counter stage has applied to it a signal from the fourth counter stage and the auxiliary storage unit of the fourth counter stage has applied to it a signal from the first counter stage. It is of advantage if there is additionally applied to the input stage of the main storage unit of the second counter stage of the decade (value a signal from the auxiliary storage unit of the fourth counter stage, and if, in an input stage of the auxiliary storage unit of the fourth counter stage, the signal of the auxiliary storage unit of the preceding counter stage is replaced by the signal of the auxiliary storage unit of the first counter stage. According to a further feature of the present invention, therefore, one of the two signals which, up to now, have controlled the main storage unit of the second counter stage, is replaced by the output signal of a separate logic circuit in which the signal which, up to now, has controlled, is combined with a signal from the fourth counter stage, and the signal which controls the auxiliary storage unit of the fourth counter stage is replaced by a signal from the first counter stage. It is of advantage if the separate logic circuit for the second counter stage has the function H 8aH =p or H vH =p According to a further feature, the purpose of which is to allow presetting of the counter to any desired decimal number, presetting signals are applied to the main storage units of the counter stages. It is of advantage if the main storage-units of the counter stages of the (i+1) decade have associated with them a logic circuit which is controlled by a clear for presetting signal and a presetting signal. According to a further feature of the present invention, therefore, each of the main storage units has associated with it a supplementary component for the presetting, which component has the logic function (new) It is advantageous if the clear for presetting signal is the clear for presetting signal of the binary counter.
According to a further feature, the purpose of which is to permit the decimal counter to count backwards as well as forward, the outputs of the counter stages are connected to a converter. It is of advantage if the outputs of the converter put out the complement to the number 9.
Additional objects and advantages of the present invention will become apparent upon consideration of the following description when taken in conjunction with the accompaying drawings in which:
FIGURE 1, having sections a, b and c, is a time plot showing various examples of the timed relationship of counting signals and auxiliary counting signals.
FIGURES 2a and 2b are pulse diagrams of the binary counter according to the present invention (except for FIGURE 12), leaving out of consideration any presetting.
FIGURE 3 is a circuit diagram of an arrangement for producing the clear for counting signal.
FIGURES 4a, 4b and 4c are circuit diagrams of different embodiments of main storage units for use with a counter according to the present invention.
FIGURE 5 is a circuit diagram of a non-presettable binary counter which incorporates main storage units according to FIGURE 4a.
FIGURE 6 is a circuit diagram of a modification of the circuit of FIGURE 5 in which the binary counter uses counter stages all having the same construction.
FIGURE 7 is a circuit diagram of an arrangement for producing a signal (2 which is formed from the counting and erasing signals.
FIGURE 8 is a circuit diagram of an arrangement for producing a signal e from the clear for counting signal, an output signal of the main storage unit of the lowest order binary digit, and the auxiliary counting signal.
FIGURE 9 is a circuit diagram of a non-presettable binary counter which incorporates main storage units according to FIGURE 4b.
FIGURE 10 is a circuit diagram of a non-presettable binary counter which incorporates main storage units according to FIGURE 4c.
FIGURE 11 is a pulse diagram for a non-presettable binary counter according to FIGURE 12.
FIGURE 12 is a circuit diagram of a non-presettable binary counter.
FIGURES 13a and 1312 are pulse diagrams for a presettable binary counter.
FIGURES 14a and 14b show circuit diagrams for arrangements for producing the clear for presetting signals.
FIGURE 15 is a circuit diagram of a presettable binary counter all of whose counter stages are similarly constructed.
FIGURE 16 is a pulse diagram showing the operation of the static counters, with particular reference being had to the presettable binary counter of FIGURE 15.
FIGURES 17a and 17b are pulse diagrams for a decimal counter developed from the binary counters of the preceding figures, without taking any presetting into consideration.
FIGURE 18 is a circuit diagrarn showing the first decade of a non-presettable decimal counter.
FIGURE 19 is a circuit diagram of another embodiment of a non-presettable decimal counter all of whose counter stages are similarly constructed.
FIGURE 20 is a circuit diagram showing an arrangement for producing the signals which are needed for the counter of FIGURE 19.
FIGURE 21 is a pulse diagram for a presettable decimal counter which has also been derived from the binary counters of the preceding figures.
FIGURE 22 is a circuit diagram of the first decade of a presettable decimal counter.
FIGURE 23 is a circuit diagram showing anot er embodiment of the first decade of a presettable decimal counter all of whose counter stages are similarly constructed.
FIGURES 24a and 2411 are circuit diagrams of arrangements for producing signals which are needed for the counter of FIGURE 23.
FIGURE 25 contains a Table 1 representing the counting steps for a decimal counter and a Table 2 showing the possible signal combinations of the outputs of the main storage units of the counter stages of one decade.
FIGURES 26, 27a and 2712 are circuit diagrams of arrangements which are controlled by a decimal counter and which produce signals for the backward counting.
FIGURES 28a and 2812 are circuit diagrams of con verters for the decimal counters.
FIGURE 29a shows, schematically, the arrangement of luminous elements by means of which numerals, as illustrated in FIGURE 2%, can be represented, while FIG- URE 290 contains a table showing the possible output combinations of a decade and the corresponding converted combinations according to FIGURE 2%.
FIGURES 30a and 30b are circuit diagrams of converters for the decimal counter of FIGURE 29.
FIGURE 31a contains a table showing the combination of signals within one decade.
FIGURES 31b and 310 are circuit arrangements for forming error signals.
Reference will now be made to the drawings.
Structure and operation of a binary counter A reliably operating static counter requires, besides the signals t; which are to be counted, auxiliary counting signals t which, as shown, for example, in FIGURE 1, are staggered or time-shifted with respect to the signals t i.e., the signals t do not appear at the same time as the signals t The binary counter requires a counter stage for each binary digit. Each counter stage requires two storage units, namely, a main storage unit and an auxiliary storage unit, which are set and erased by si nals, i.e., which store signals and which clear the signals, only when cer tain conditions are met. The storage units are coupled galvanically. The storage units are set or erased only when the amplitude of the control signals applied to the storage units exceeds a predetermined value, the shape of the flanks of the signal pulses being of non consequence.
FIGURE 2a is a pulse diagram which shows the signals needed for controlling the counter, as well as the out put signals of four counter stages. In order to keep FIGURE 20 reasonably simple, only the affirmed signals are shown (for example, only t is shown, but not its negate t Also for the sake of simplicity, the pulses are shown as square wave pulses. The signals can have the value or L. In this as Well as all other diagrams, the zero line or abscissa will be deemed to represent the value 0 while the lines overlying this abscissa line will be considered as representing the value L.
Upon the appearance of an erase signal 1=L, the outputs A of the main storage units, as they are shown for example in FIGURE at S and the outputs H of the auxiliary storage units, shown in FIGURE 5 at S are set to 0. When, after erasing, 1:0, the counter is ready for operation.
The signals to be counted are indicated as t while the further, auxiliary signals needed to control the counter are indicated as t These signals are staggered, and there are time intervals between them, as shown.
The clear for counting signal 2 the signals t being counted only when z =L. In practice, the signal Z2 is so synchronized that it can change only with the leading ilank of an auxiliary counting signal t One embodiment of this will be explained below. The output of the main storage unit of the counter stage for the lowest order binary digit is indicated at A the output for the main 8 storage unit of higher order digits at A A and so on. Similarly, the outputs of the auxiliary storage units are indicated at H H H and so on. The indices 0, l, 2 represent the digital value 2, 2 2 of the binary digits.
It will be seen that with each counting step 1, 2, 3 the count indicated at the outputs A increases by one unit, i.e., the combination of 0 and L signals changes in accordance with the natural binary code. Thus, with the first signal t (c to be counted, the signal at output A is L while the signals at outputs A A and so on, will each be 0. With the second counting signal t (c the output at A becomes 0, the signal at A becomes equal to L, and the signals at the outputs A A etc., remain at 0. The diagram shows the progress made up to and including the 23rd counting step, it being assumed that the count will not change during such durations as Z2 is equal to 0.
As already stated, auxiliary signals t are needed in addition to the signals I which signals t are used for producing further signals H. The instants at which the H signals are stored and erased are so selected that, with the help of these signals, there will appear at the outputs A of the main storage units signal combinations corresponding to the natural binary code, and that the switching functions for the main as well as the auxiliary storage units will be as simple as possible.
In order that the main storage unit of the lowest order binary digit having the output A will be set (stored) upon the appearance of the first counting signal t (c and reset (erased) upon the appearance of the second counting signal t (c the two instants of time are distinguished by a second signal H which is produced by an auxiliary storage unit which thus is in different circuit condition at the start and end of the signal A This auxiliary storage unit is set upon the appearance of the first auxiliary signal t (d while the output A =L, and erased with the following auxiliary signal t (d when A is again equal to 0. There is thus obtained the following switching function (the erasing signal 1 and the clear for counting signal 1 being, for the time being not considered):
The output A of the main storage unit of the binary digit 2 has to become L upon the eppearance of the second counting signal(c and 0 upon the appearance of the fourth counting signal (c At these instants H =L. These two instants of time are, in accordance with the present invention, distinguished from each other by a further signal H which is formed by means of a further auxiliary storage unit H =0 at the beginning of A and is equal to L at the end of A in which case it is advantageous, insofar as simplicity of switching function for the counter stage is concerned, if, for the duration of the third counting signal t (c the signal H =0.
The signal H shown in the diagram fulfills these conditions. The signal H is equal to L during the time intervals indicated at b b The switching function for the auxiliary storage unit which produces this signal is particularly simple. The auxiliary storage units for H becomes, dorninatingly, set upon the appearance of a counting signal t when A =L, and is erased with H, (this being the negate of H which is not shown). The switching function for the output signal of the main storage unit and the auxiliary storage unit of the binary digit 2 without taking into consideration the erasing signal 1, is thus:
In the response condition for A the t, in the first bracketed term can be replaced by A1,- The switching
US327585A 1962-11-28 1963-11-29 Static counter having main and aluxiliary stores and controlled by staggered counting and auxiliary counting signals Expired - Lifetime US3387118A (en)

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US3940596A (en) * 1973-06-11 1976-02-24 International Business Machines Corporation Dynamic logic counter
US20040009882A1 (en) * 1996-02-08 2004-01-15 Huntsman Petrochemical Corporation Structured liquids made using LAB sulfonates of varied 2-isomer content

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US3308384A (en) * 1964-08-31 1967-03-07 Rca Corp One-out-of-n storage circuit employing at least 2n gates for n input signals

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NL301115A (en)
GB1072554A (en) 1967-06-21
DE1170001B (en) 1964-05-14
NL301059A (en)
FR1533901A (en) 1968-07-26
NL143767B (en) 1974-10-15

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