US3383526A - Current driver circuit utilizing transistors - Google Patents

Current driver circuit utilizing transistors Download PDF

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Publication number
US3383526A
US3383526A US419050A US41905064A US3383526A US 3383526 A US3383526 A US 3383526A US 419050 A US419050 A US 419050A US 41905064 A US41905064 A US 41905064A US 3383526 A US3383526 A US 3383526A
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US
United States
Prior art keywords
current
line
amplitude
voltage source
impedance
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US419050A
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English (en)
Inventor
Andrew R Berding
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
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International Business Machines Corp
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Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US419050A priority Critical patent/US3383526A/en
Priority to FR40761A priority patent/FR1457866A/fr
Priority to DE1965J0029579 priority patent/DE1248711B/de
Priority to SE16105/65A priority patent/SE323418B/xx
Priority to GB52763/65A priority patent/GB1097919A/en
Priority to NL656516295A priority patent/NL152417B/xx
Priority to CH1747965A priority patent/CH437418A/de
Application granted granted Critical
Publication of US3383526A publication Critical patent/US3383526A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • A—HUMAN NECESSITIES
    • A21—BAKING; EDIBLE DOUGHS
    • A21C—MACHINES OR EQUIPMENT FOR MAKING OR PROCESSING DOUGHS; HANDLING BAKED ARTICLES MADE FROM DOUGH
    • A21C5/00—Dough-dividing machines
    • A21C5/02—Dough-dividing machines with division boxes and ejection plungers
    • A21C5/06—Dough-dividing machines with division boxes and ejection plungers with division boxes in a revolving body with axially-working pistons
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F11/00—Indicating arrangements for variable information in which the complete information is permanently attached to a movable support which brings it to the display position
    • G09F11/30—Indicating arrangements for variable information in which the complete information is permanently attached to a movable support which brings it to the display position the display elements being fed one by one from storage place to a display position
    • G09F11/34—Indicating arrangements for variable information in which the complete information is permanently attached to a movable support which brings it to the display position the display elements being fed one by one from storage place to a display position the feeding means comprising electromagnets
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/06—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element
    • G11C11/06007—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element using a single aperture or single magnetic closed circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J29/00—Details of cathode-ray tubes or of electron-beam tubes of the types covered by group H01J31/00
    • H01J29/46—Arrangements of electrodes and associated parts for generating or controlling the ray or beam, e.g. electron-optical arrangement
    • H01J29/70—Arrangements for deflecting ray or beam
    • H01J29/708—Arrangements for deflecting ray or beam in which the transit time of the electrons has to be taken into account
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/26—Time-delay networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/26—Time-delay networks
    • H03H11/265—Time-delay networks with adjustable delay
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/28—Impedance matching networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H2/00—Networks using elements or techniques not provided for in groups H03H3/00 - H03H21/00
    • H03H2/005—Coupling circuits between transmission lines or antennas and transmitters, receivers or amplifiers
    • H03H2/008—Receiver or amplifier input circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
    • H03K19/01806—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H03K5/06—Shaping pulses by increasing duration; by decreasing duration by the use of delay lines or other analogue delay elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/44—Arrangements for feeding power to a repeater along the transmission line
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/10—Arrangements for reducing cross-talk between channels

Definitions

  • a low impedance voltage source is coupled to drive a current pulse down a line terminated by an impedance element shunted by a second termination comprising a current sink coupled to normally forward bias a diode.
  • the voltage source is turned on to produce an initial current wave on the line and the forward biased diode appears as a short circuit to this initial current wave on the line.
  • the current wave is reflected sucessively between the shorted termination and the voltage source, and the reflected current adds to the incident current to produce a higher current,
  • this current amplitude reaches the current accepted by the current sink, the diode becomes reverse biased and the line is then terminated by the impedance element.
  • the result is a current pulse having the fastest rise time to the final line current from a given voltage source.
  • This invention relates to driver circuits and, more particularly, to current driver circuits useful for driving inductive loads such as magnetic cores.
  • High speed transistor logic circuits are characterized by the use of small signal swings so that only a relatively small voltage is required by such circuitry.
  • current drivers are utilized in a system with only the low voltage available, a problem is encountered in obtaining a current drive pulse having a sufficiently fast rise time in applications where an inductive load is driven, such as in drivers for a magnetic core memory, for example. It is therefore a principal object of this invention to provide an improved driver circuit having the ability to deliver a current pulse having the fastest possible rise time to a predetermined culrent from a given supply voltage.
  • a current sensitive device having a nonlinear impedance is provided to terminate a line to obtain the fastest possible rise time to a predetermined current from a given supply voltage.
  • the initial driving current pulse is propagated down the line and reflected from the nonlinear termination due to the low impedance state of the termination.
  • the reflected wave is in phase with the incident wave and adds thereto.
  • the wave is again reflected at the input end of the line due to the low impedance of the driving source.
  • the wave is continually reflected from the input end of the line to the termination end until the current on the line reaches the predetermined value.
  • the nonlinear termination changes to the high impedance state so that the line is then terminated by an impedance element.
  • FIG. 1 is a diagrammatic, schematic diagram of a drive system embodying the invention.
  • FIG. 2 is a specific embodiment of a circuit employing the invention.
  • FIG. 3 is a schematic diagram of a magnetic core memory drive circuit embodying the invention.
  • FiG. 4a is a plot of current amplitude versus time at the input end of the line.
  • FIG. 4b is a plot of current amplitude versus time at the output end of the line.
  • a voltage source V is coupled to drive a current pulse down a line terminated by an impedance element 16 shunted by a current sensitive device 18 comprising a current sink 14 coupled to normally forward bias a diode 12.
  • a current sensitive device 18 comprising a current sink 14 coupled to normally forward bias a diode 12.
  • the forward biased diode 12 appears as a short circuit to the current wave on the line so that, when the current wave front approaches the termination end of the line, the current is refiected, and the reflected current adds to the incident current since they are in phase.
  • the amplitude of the resultant current is then 2V/Z0. If this current amplitude is less than the current I accepted by current sink 14, then diode 12 remains forward biased and the reflected current travels back to the input end of the line.
  • the reflected current again reflects off the low impedance voltage source, and at this time the resultant current amplitude of SV/Zo exists on the line.
  • the current wave continues to reflect back and forth until the current at the terminating end of the line exceeds 1.
  • diode 12 becomes reverse biased and thus changes to the high impedance state.
  • the resulting termination is current sink 14- shunted by R0.
  • R0 current sink 14- shunted by R0.
  • FIG. 2 A specific circuit embodying the invention is shown in FIG. 2.
  • the voltage source is provided by a transistor 29 which is saturated when a positive voltage pulse is applied to the base electrode.
  • the output of the voltage source is coupled from the emitter to the input end of the line 28 to be driven, and the termination of the line to be driven comprises a resistor 22 returned to the signal reference potential of ground potential.
  • the current sensitive device comprises a diode 24 connected to the line and returned to ground and a current sink comprising a transistor 3i) connected in a grounded base circuit so that diode 24 is normally forward biased due to the current flow from ground through the diode and the current sink.
  • Line 28 comprises any suitable device whose characteristics resemble a transmission line.
  • the invention is especially suitable for applications wherein a current pulse is driven to an inductive load such as the drive lines of a magnetic core memory, for example.
  • the incident current wave on line 28 is reflected by the substantially short circuit termination comprising forward biased diode 24.
  • the current wave then doubles in amplitude, and the wave is reflected back toward the input.
  • the low impedance of conducting transistor 20 causes the current wave to be reflected again toward the load end of line 28.
  • the reflections continue with each reflection adding a unit of current equal to the incident current wave until the current value exceeds the current accepted by current sink transistor 30.
  • diode 24 is back biased so that the line is then terminated in resistor 22, which is chosen equal to the characteristic resistance of line 28, in series with a a voltage I R as stated above.
  • resistor 22 which is chosen equal to the characteristic resistance of line 28, in series with a a voltage I R as stated above.
  • FIG. 3 shows the invention embodied in a magnetic core memory drive system.
  • a cross section of the drive system is shown.
  • a plurality of array lines 40 are provided, and each array line is coupled for driving a plurality of magnetic cores 41.
  • a driver and a gate are simultaneously selected by their respective address lines.
  • the write gate 46 and the write driver 44 must be turned on to cause current flow through the array line in the write direction.
  • the read driver 48 and read gate 50 must be active.
  • the array diodes 52 are necessary to insure that there are no paths for the current through the array other than the one desired.
  • write driver 44 and write gate 46 are turned on by the corresponding address lines 42 being positive and the positive Write timing pulse being present. These input pulses cause transistors 54 to turn on, thereby turning on transistors 56, which conduct heavily.
  • a predetermined current determined by the voltage transition and the characteristic impedance of the line, is driven down the array line 58. The current is reflected from the termination of the line comprising diode 60 forward biased by the current source 62. The reflected pulse is again reflected by the low impedance driver 44, which appears as a short circuit to the reflected pulse. The pulse is continually reflected, and at each reflection an increment i of current is added to the current on the line until the current on the line equals or exceeds the current I supplied by the current source.
  • the line is then terminated in resistor 70', which is preferably equal to the characteristic impedance of the line.
  • the sum of the currents supplied by the driver and the current sink is the current required to switch the cores.
  • current in the read direction is obtained by actuating read driver 48 and read gate 50.
  • the termination comprising current source 64, diode 66 and resistor 68 then causes buildup of the current on the line by successive reflections as described above.
  • the final current I on the line may be chosen as onehalf the current required to change the remanent state of magnetic cores 41 in cases where a coincident current selection technique is used.
  • the final current may be chosen as the full select current necessary to change the remanent state of the cores when a word selection .scheme is used. Any desired number of reflections may be used to obtain the desired final current.
  • a circuit for supplying a current pulse of a predetermined amplitude to a line comprising:
  • a line having a determinable characteristic impedance with respect to a reference potential said line having an input end and a termination end;
  • voltage source means having an impedance low with respect to said characteristic impedance coupled to the input end of said line;
  • first terminating means presenting an impedance low with respect to said characteristic impedance in response to a current pulse on the line having an amplitude less than said predetermined current to thereby cause said current pulse having an amplitude less than a predetermined termination current to be reflected toward the input end of said line, said first terminating means presenting a high impedance to a current pulse on said line having an amplitude equal to or greater than said predetermined termination current;
  • said second terminating means comprising an impedance element coupled between the termination end of said line and said reference potential
  • said first terminating means comprises a current sink coupled to said termination end of saidline and a current sensitive device coupled between said termination end of said line and said reference potential.
  • a line having a determinable characteristic impedance with respect to a reference potential said line having an input end and a termination end;
  • a first terminating means comprising a current sink and a current sensitive device coupled across the termination end of said line, said first terminating means presenting an impedance low with respect to said characteristic impedance in response to a current pulse on the line having an amplitude less than the current produced by said current sink to thereby cause said current pulse having an amplitude less than said sink current to be reflected toward the input end of said line, said first terminating means presenting a high impedance to a current pulse on said line having an amplitude equal to or greater than said sink current;
  • a second terminating means comprising an impedance element coupled between the termination end of said line and said reference potential
  • a circuit for supplying a current pulse of a predetermined amplitude to a line comprising:
  • a line having a determinable characteristic impedance with respect to a reference potential said line having an input end and a termination end;
  • voltage source means having substantially zero impedance coupled to the input end of said line;
  • a first terminating means comprising a current sink coupled to the termination end of said line and a diode coupled from the termination end of said line to said reference potential, said first terminating means presenting substantially zero impedance in response to a current pulse on the line having an amplitude less than said current sink output to thereby cause said current pulse having an amplitude less than said sink current to be reflected toward the input end of said line, said first terminating means presenting a substantially infinite impedance to a current pulse on said line having an amplitude equal to or greater than said sink current;
  • a second terminating means comprising an impedance element coupled between the termination end of said line and said reference potential
  • said current sink comprises a second transistor having emitter, base and collector, a resistor and a voltage source having a second polarity with respect to said reference potential;
  • said second terminating means comprises a resistor substantially equal to the characteristic impedance of said line.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Nonlinear Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Electromagnetism (AREA)
  • Food Science & Technology (AREA)
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US419050A 1964-12-17 1964-12-17 Current driver circuit utilizing transistors Expired - Lifetime US3383526A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
US419050A US3383526A (en) 1964-12-17 1964-12-17 Current driver circuit utilizing transistors
FR40761A FR1457866A (fr) 1964-12-17 1965-12-03 Générateur de courant
DE1965J0029579 DE1248711B (de) 1964-12-17 1965-12-11 Übertragungsleitung fur lmpulsformige Signale
SE16105/65A SE323418B (de) 1964-12-17 1965-12-13
GB52763/65A GB1097919A (en) 1964-12-17 1965-12-13 Current driver circuit
NL656516295A NL152417B (nl) 1964-12-17 1965-12-15 Drijverschakeling.
CH1747965A CH437418A (de) 1964-12-17 1965-12-17 Einrichtung mit einer Übertragungsleitung für impulsförmige Signale

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US419050A US3383526A (en) 1964-12-17 1964-12-17 Current driver circuit utilizing transistors

Publications (1)

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US3383526A true US3383526A (en) 1968-05-14

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US419050A Expired - Lifetime US3383526A (en) 1964-12-17 1964-12-17 Current driver circuit utilizing transistors

Country Status (7)

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US (1) US3383526A (de)
CH (1) CH437418A (de)
DE (1) DE1248711B (de)
FR (1) FR1457866A (de)
GB (1) GB1097919A (de)
NL (1) NL152417B (de)
SE (1) SE323418B (de)

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3444483A (en) * 1966-02-23 1969-05-13 Bell Telephone Labor Inc Pulse bias circuit utilizing a half-wavelength section of delay line
US3544978A (en) * 1968-03-18 1970-12-01 Gen Motors Corp Method and apparatus for driving memory core selection lines
US3546487A (en) * 1966-04-15 1970-12-08 Rca Corp Drive circuit for digit lines
US3568170A (en) * 1968-05-21 1971-03-02 Electronic Memories Inc Core memory drive system
US3585399A (en) * 1968-10-28 1971-06-15 Honeywell Inc A two impedance branch termination network for interconnecting two systems for bidirectional transmission
US3656009A (en) * 1970-09-04 1972-04-11 Sperry Rand Corp Non-linear transmission line current driver
US3660675A (en) * 1970-05-05 1972-05-02 Honeywell Inc Transmission line series termination network for interconnecting high speed logic circuits
US3997843A (en) * 1975-06-20 1976-12-14 Calspan Corporation Monocycle pulse generator
US4367415A (en) * 1979-02-24 1983-01-04 Hewlett-Packard Gmbh Pulse generator circuit
US4812689A (en) * 1987-08-28 1989-03-14 Hypres, Inc. Incremental time delay generator
US5534812A (en) * 1995-04-21 1996-07-09 International Business Machines Corporation Communication between chips having different voltage levels
US20070044037A1 (en) * 2005-07-08 2007-02-22 Nissan Motor Co., Ltd. Menu display device and method
US20090207641A1 (en) * 1999-07-30 2009-08-20 Leonard Forbes Novel transmission lines for cmos integrated circuits
WO2010074617A1 (en) * 2008-12-22 2010-07-01 Telefonaktiebolaget L M Ericsson (Publ) Sub sampling electrical power conversion
US7829979B2 (en) 2002-03-13 2010-11-09 Micron Technology, Inc. High permeability layered films to reduce noise in high speed interconnects

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2805541C2 (de) * 1978-02-10 1982-06-03 Telefonbau Und Normalzeit Gmbh, 6000 Frankfurt Schaltungsanordnung für eine störungssichere unsymmetrische Übertragung digitaler Signale
DE4037893A1 (de) * 1990-11-28 1992-06-04 Siemens Ag Hochspannungsleitung zur zufuehrung von hochspannungsimpulsen zu einer im wesentlichen induktiven last

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2829282A (en) * 1956-05-17 1958-04-01 Itt Pulse generator
CA603877A (en) * 1960-08-23 L. Glomb Walter Time delay circuit
US2995667A (en) * 1957-12-23 1961-08-08 Ibm Transmission line driver
US3054906A (en) * 1960-12-29 1962-09-18 Bell Telephone Labor Inc Negative resistance pulse regenerator with unidirectional reflector
US3141981A (en) * 1962-07-03 1964-07-21 Henebry William Michael Pulse generating circuit having a high repetition rate utilizing avalanche transistor-coaxial line combination
US3209171A (en) * 1962-11-21 1965-09-28 Rca Corp Pulse generator employing minority carrier storage diodes for pulse shaping
US3252100A (en) * 1963-10-07 1966-05-17 James E Webb Pulse generating circuit employing switch-means on ends of delay line for alternately charging and discharging same
US3302035A (en) * 1963-04-30 1967-01-31 Electronic Associates Transmission system

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA603877A (en) * 1960-08-23 L. Glomb Walter Time delay circuit
US2829282A (en) * 1956-05-17 1958-04-01 Itt Pulse generator
US2995667A (en) * 1957-12-23 1961-08-08 Ibm Transmission line driver
US3054906A (en) * 1960-12-29 1962-09-18 Bell Telephone Labor Inc Negative resistance pulse regenerator with unidirectional reflector
US3141981A (en) * 1962-07-03 1964-07-21 Henebry William Michael Pulse generating circuit having a high repetition rate utilizing avalanche transistor-coaxial line combination
US3209171A (en) * 1962-11-21 1965-09-28 Rca Corp Pulse generator employing minority carrier storage diodes for pulse shaping
US3302035A (en) * 1963-04-30 1967-01-31 Electronic Associates Transmission system
US3252100A (en) * 1963-10-07 1966-05-17 James E Webb Pulse generating circuit employing switch-means on ends of delay line for alternately charging and discharging same

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3444483A (en) * 1966-02-23 1969-05-13 Bell Telephone Labor Inc Pulse bias circuit utilizing a half-wavelength section of delay line
US3546487A (en) * 1966-04-15 1970-12-08 Rca Corp Drive circuit for digit lines
US3544978A (en) * 1968-03-18 1970-12-01 Gen Motors Corp Method and apparatus for driving memory core selection lines
US3568170A (en) * 1968-05-21 1971-03-02 Electronic Memories Inc Core memory drive system
US3585399A (en) * 1968-10-28 1971-06-15 Honeywell Inc A two impedance branch termination network for interconnecting two systems for bidirectional transmission
US3660675A (en) * 1970-05-05 1972-05-02 Honeywell Inc Transmission line series termination network for interconnecting high speed logic circuits
US3656009A (en) * 1970-09-04 1972-04-11 Sperry Rand Corp Non-linear transmission line current driver
US3997843A (en) * 1975-06-20 1976-12-14 Calspan Corporation Monocycle pulse generator
US4367415A (en) * 1979-02-24 1983-01-04 Hewlett-Packard Gmbh Pulse generator circuit
US4812689A (en) * 1987-08-28 1989-03-14 Hypres, Inc. Incremental time delay generator
US5534812A (en) * 1995-04-21 1996-07-09 International Business Machines Corporation Communication between chips having different voltage levels
US20090207641A1 (en) * 1999-07-30 2009-08-20 Leonard Forbes Novel transmission lines for cmos integrated circuits
US7869242B2 (en) * 1999-07-30 2011-01-11 Micron Technology, Inc. Transmission lines for CMOS integrated circuits
US7829979B2 (en) 2002-03-13 2010-11-09 Micron Technology, Inc. High permeability layered films to reduce noise in high speed interconnects
US20070044037A1 (en) * 2005-07-08 2007-02-22 Nissan Motor Co., Ltd. Menu display device and method
WO2010074617A1 (en) * 2008-12-22 2010-07-01 Telefonaktiebolaget L M Ericsson (Publ) Sub sampling electrical power conversion
EP2368324A1 (de) * 2008-12-22 2011-09-28 Telefonaktiebolaget L M Ericsson (publ) Unterabtastende elektrische leistungsumsetzung
EP2368324A4 (de) * 2008-12-22 2012-11-07 Ericsson Telefon Ab L M Unterabtastende elektrische leistungsumsetzung
CN102265496B (zh) * 2008-12-22 2014-05-07 爱立信电话股份有限公司 二次取样电力转换
US8803367B2 (en) 2008-12-22 2014-08-12 Telefonaktiebolaget L M Ericsson (Publ) Sub sampling electrical power conversion

Also Published As

Publication number Publication date
CH437418A (de) 1967-06-15
DE1248711C2 (de) 1968-03-14
NL6516295A (de) 1966-06-20
SE323418B (de) 1970-05-04
NL152417B (nl) 1977-02-15
FR1457866A (fr) 1966-01-24
GB1097919A (en) 1968-01-03
DE1248711B (de) 1967-08-31

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