US3283171A - Semiconductor switching device and circuit - Google Patents
Semiconductor switching device and circuit Download PDFInfo
- Publication number
- US3283171A US3283171A US255496A US25549663A US3283171A US 3283171 A US3283171 A US 3283171A US 255496 A US255496 A US 255496A US 25549663 A US25549663 A US 25549663A US 3283171 A US3283171 A US 3283171A
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- Prior art keywords
- collector
- base
- region
- transistor
- sink
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- 239000004065 semiconductor Substances 0.000 title description 9
- 229920006395 saturated elastomer Polymers 0.000 claims description 14
- 238000004353 relayed correlation spectroscopy Methods 0.000 claims 1
- 239000000969 carrier Substances 0.000 abstract description 10
- 238000003860 storage Methods 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 239000012535 impurity Substances 0.000 description 14
- 229910052710 silicon Inorganic materials 0.000 description 14
- 239000010703 silicon Substances 0.000 description 14
- 238000009792 diffusion process Methods 0.000 description 12
- 239000000758 substrate Substances 0.000 description 11
- 239000000463 material Substances 0.000 description 8
- 235000012431 wafers Nutrition 0.000 description 8
- 238000013461 design Methods 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 230000007480 spreading Effects 0.000 description 2
- 238000010408 sweeping Methods 0.000 description 2
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000009931 harmful effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/098—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using thyristors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0817—Thyristors only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
Definitions
- the present invention relates to a semiconductor device and to circuits utilizing same. More particularly, it relates to such a device capable of simulating relay type operation and which includes an excess base current collecting region.
- the first electric computers used in industry utilized electromagnetic relays for their various logic and switching functions.
- the relay was and still is theoretically an ideal switching device since a signal applied to a control element gives an absolute switching function to a controlled circuit, thus, the various problems of fan-in fanout noise and so forth could be practically eliminated since a closed relay is virtually a zero resistance device and there are no noise sources which would tend to complicate designs.
- the advent of the electronic computer initially using electron tubes for switching and logic constituted a considerable improvement in speed and general reliability -over the old or original electromagnetic or relay type of computers.
- the modern trend towards solid state, and in particular transistorized computers has led to many problems in the development of switching and logic circuits.
- the transistor is inherently only a fraction of the size of either the electromagnetic relay or the electron tube and requires far less power for operation, many circuit compromises must be made to allow for the peculiarities of the transistor itself.
- the inputs and outputs are not isolated in the same way that an electromagnetic relay or even a vacuum tube may be isolated, thus, base current in the transistor flows in the emitter circuit adding to the collector currents.
- the various emitter currents are different depending upon the location of the transistor in the string relative to ground. Thus, in a saturated string of four such transistors one would have an emitter current equal to I +4I for the bottom transistor.
- circuit design considerations are so extremely involved when building a simulated relay type logic configuration from conventional three layer transistors and the device tolerances are so narrow that such circuitry has never received serious consideration in spite of the many attractive logic configurations possible.
- FIGURE 1 is a schematic diagram of a simplified switching circuit utilizing a single semiconductor element constructed in accordance with the present invention and illustrating in a general way the various current paths in such a circuit.
- FIGURE 2 is a diagram illustrating minority carrier distribution and the junction currents in the device of FIGURE 1.
- FIGURES 3a and 3b are schematic diagrams respectively of an AND-INVERT and an AND circuit utilizing devices of the present invention.
- FIGURE 4 is a cross-sectional view showing actual construction details of a portion of a module utilizing the teachings of the present invention.
- a transistor having at least an emitter, base and collector wherein there is provided adjacent the collector region and forming a rectifying junction therewith a fourth region of opposite conductivity type to said collector region, said junction being sufiiciently close to the base-collector junction to function as an excess base current trap and means provided for directly connecting said region to the emitter or some point of potential that will maintain the collector-sink junction reverse biased.
- excess base current refers to that current due to minority carrier injection from the base to the collector when the transistor is biased to saturation. In saturation, this current is relatively large while in the unsaturated condition it is negligible. Also, the excess base current collector region will be referred to as the base current sink for simplicity in the remainder of the specification.
- This junction may be created in any number of ways well known in the art, such for example, as by diffusion from an alloy dot or by epitaxial growth, etc.
- the result is a four layer device of alternately doped regions which differs considerably from the well known four layer Shockley hook transistor.
- the primary physical differences are in the doping levels, collector widths, injection efiiciencies and the device alphas (a).
- the standard Shockley transistor intends to give a two terminal negative resistance characteristic and does so by employing the two extreme junctions in a forward biasing mode of operation. It injects minority carriers toward the center junction which acts as a collector for both requiring high alphas and injection efiiciencies for these two common collector junction transistors.
- the device of this invention employs one extreme junction as emitter and the other as a collector and the center junction as a collector for the former and an emitter for the latter.
- To optimize alphas for this type of operation requires entirely different relative doping levels as well as junction geometry and, in fact, results in a structure which probably would not exhibit a negative resistance characteristic if used as a two terminal device.
- the collector region of the device of this invention will also be several times thicker than the base region to allow for minimizing the collector spreading resistance. In the Shockley device, these regions would be of the same thickness.
- the transistor of FIGURE 1 constructed in accordance with the present invention comprises an emitter 10, a base 12, a collector 14 and base current sink region 16 adjacent the collect-or.
- the Figure illustrates the currents which flow in the external circuitry and the way in which the terminals are connected in order for the transistor to operate in saturated circuitry. Constructing a transistor in the fashion to be more fully set forth and described below and connecting it in the manner illustrated in FIGURE 1 significantly reduces the amount of base current which will flow in the emitter circuitry of the transistor when saturated and will significantly reduce the time for said saturated transistor to be cut off.
- the amount of base current which flows out of the emitter is only that required to sustain the collector current and is normally a very small fraction of said collector current.
- the excess base current which corresponds to minority carriers injected into the collector flows out a terminal marked S and then directly to ground and need not mix with the emitter current, as will be seen subsequently.
- FIGURE 2 shows the minority carrier distributions in the device and the junction currents which help to explain the principles of operation.
- the lower portion of the base and collector regions 12 and 14 respectively indicate the relative quantity of minority carriers injected into these regions and will be seen to be greater near the base-collector junction in the collector region and near the base emitter junction in the base region respectively.
- the advantage of such devices is a cascaded emitter-follower AND circuit is that if transistor A is turned off, the base current drives of transistors B and C will flow in the sink circuit and will not cause noise in the output circuit.
- the sink region provides a path for base current during saturation of B and C when transistor A is not on.
- excess base current drive causes unpredictable results, such as noise, etc. If a great deal of branching above transistor C occurs, this is very important, since the amount of extraneous base current could easily exceed that required to give a true output indication.
- the transistor of the present invention including the base current sink region also has particular utility in the cascade AND-INVERT circuit of FIGURE 3a.
- FIGURES 3a and 3b both show cascaded transistors constructed in accordance with the invention cascaded in AND circuit configuration, it is to be understood that such transistors would have equal value in parallel connection as with an OR circuit, or for that matter, any other application where excess base current became a problem when the transistors are operating at saturated levels.
- the primary criteria in constructing a transistor according to the present invention is that the base region must be considerably more heavily doped than the collector region and the base current sink junction must be sufiiciently close to the base-collector junction in order to attract the injected minority carriers and sweep them out of the collector.
- the doping level of the sink region is not critical except that it should be kept as low as possible to reduce junction capacitance. Characteristic doping levels for typical transistors constructed in accordance with the invention are approximately 2 10 atoms of impurity material/cc. of semiconductor material in the base region and approximately 2X10 atoms of impurity material/cc. of semiconductor material in the collector region.
- Collector widths should be between 2 and 5 times the base width 'for optimum sweeping of the minority carriers from the collector.
- a single transistor may be fabricated according to the present invention in a number of ways including both diffusion and epitaxial deposition and/ or any combination of these, plus other well known methods of producing rectifying junctions well known in the semiconductor art.
- Example I In this example, a bar of highly doped p type silicon was placed in a conventional tubular vacuum furnace having heating coils provided at different locations therein as is well known in the art to vaporize the materials being used in the epitaxial deposition or diffusion steps of transistor fabrication. Next, a source of silicon containing 11 type conductivity type determining impurities therein was vaporized and caused to deposit an epitaxial layer on the p type substrate. The conductivity type determining impurity in this region was arsenic. Next, the base and the emitter areas were formed in the 11 type wafer by conventional double diffusion methods using fairly conventional masking techniques. Finally, a mesa etch was employed to limit the area of the epitaxial or collector sink junction. The p type base region was obtained with a boron diffusion and the n+ type emitter a,asa,171
- the n+ type conductivity type determining impurity in the emitter was phosphorus doped to a level of approximately 2 atoms of conductivity type determining impurity per cc. of silicon.
- the p type (boron diflfused) base region was doped to a level of approximately 2 10 atoms of conductivity type determining impurity per cc. of silicon.
- n type (arsenic doped) epitaxial layer or collector region was doped to a level of approximately 2 10 atoms of conductivity type determining impurity per cc. of semiconductor material and the p type silicon substrate was doped to a level of approximately 5 l0 atoms of p type conductivity deter mining impurity per cc. of silicon.
- Emitter, base, collector and sink contacts were connected to the npnp regions of the device respectively and the device was tested and found to have substantially reduced turn-oh times after a heavily saturating base current drive was applied to the base terminal and exhibited lower excess minority carrier storage or excess base currents in the emitter circuit path during saturation.
- Example 11 A second npnp four layer transistor structure embodying the teachings of the present invention was made in a manner very similar to that of Example I.
- the resultant structure had a total n type epitaxial layer thickness of approximately 6 microns.
- the base diffusion had a diameter of about 12 mils and was 2.8 microns deep.
- the emitter diffusion had a 4 mil diameter and was about 1.5 microns deep, giving a total collector width of 3.2 microns and a base width of 1.3 microns.
- the n type epitaxial layer was doped to a level of somewhat less than the 2X10 atoms of conductivity type determining impurity per cc. of silicon of Example I.
- Example II The same doping materials were used as in Example I and the doping densities were approximately the same with the exception of the collector doping level as stated above. Tests were run on this transistor and it was found to behave in the manner predicted, i.e., that a drain current flowed when the transistor was saturated. For example, with a collector current of 0.5 milliamp and a base current of 0.5 milliamp, a sink current of 0.23 milliamp was observed. This agreed precisely with the sink current predicted with the npn and pnp us which were measured on this device. With alphas close to unity the sink current would have been very nearly 0.5 millia-mp.
- collector widths W of 3.2 and 3.5 have been illustrated in the two examples, it is to be understood that the actual W which could be used, would depend upon a number of factors, but mainly on the trade-off between the pnp at desired and the npn collector spreading resistance that can be tolerated, and that the relative doping levels between the base and collector are also subject to a certain amount or design variation.
- the primary requirement is that the base be more heavily doped than the collector.
- this region must be sufficiently narrow that the reverse biasing effect of the collector-sink junction is enabled to sweep the injected minority carriers out of the collector and into said sink region.
- FIGURE 4 shows a further extension of the present invention in which a plurality of devices constructured in accordance with the present invention can readily be made, as a modular structure incorporating a fairly large number of such devices in a small area.
- a plurality of wafers of 11 type material are grown by epitaxial deposition of a p type silicon substrate. Subsequently, a double diffusion creates the emitters and bases on the respective 11 type wafers. It will be noted in the drawing that the emitters, bases and collectors on each wafer are marked respectively e, b, c and that the substrate, which is labeled cs for common sink, is common to all of the individual transistor waters.
- the p type substrate is, of course, the common sink region and constitutes a p type fourth layer on an npn transistor.
- this embodiment could also be constructed using an n type substrate and pnp transistors deposited on the top surface thereof.
- a modular device constructed in accordance with FIG- URE 4 would be made in substantially the same manner as the single devices of Examples I and 11 above.
- the primary dilference would be in the use of a larger starting substrate and utilizing plural masking and/or etching to produce a plurality of wafers on the substrate and then using plural masking for the subsequent double diffusion operations to form the base and emitter regions.
- a simulated relay type transistor switching element comprising a four layer transistor defining emitter, base, collector and base current sink regions in that order respectively, bias means for maintaining the base-collector and collector-base current sink junction reverse biased when said transistor is saturated,
- said collector region being between about 2 and 5 times the width of said base region whereby minority carriers injected into said collector by said base will be swept into said base current sink region by a drift field set up by the collector-base current sink bias, and
- a four layer transistor comprising:
- the sink region comprises high resistivity p type silicon
- the collector comprises an epitaxial layer of n doped silicon
- the base and emitter electrodes comprise boron and phosphorous diifused regions respectively in said n type wafer wherein the n type epitaxial collector wafer is arsenic doped to a level of approximately 2 10 atoms of conductivity type determining impurity per cc. of silicon
- the base region is boron doped to a level of approximately 2 10 atoms of conductivity type determining impurity per cc.
- the emitter is heavily doped with n+ type phosphorous to a level of approximately 2 10 atoms of conductivity type determining impurity per cc. of silicon
- the base current sink region is doped to a level of approximately 5X10 atoms of p type conductivity determining impurity per cc. of silicon
- each of said emitter, base and collector regions means to connect each of said emitter, base and collector regions to external circuitry to operate said regions as a conventional transistor, and potential means connected to said sink region to maintain the collector-sink junction in a condition of reverse bias.
- a transistor simulated relay type logic circuit comprising a plurality of four layer transistors each comprising:
- transistors being connected in a series string such that the emitter of the first transistor is connected to ground and the collector and emitter of subsequent transistors are connected together and the collector region of the last transistor in the string is connected to a source of potential for reverse biasing the base-collector junction of that transistor,
- a modular transistor structure comprising:
- a plurality of four layer transistors each comprising emitter, base, collector and base current sink regions wherein said sink region is located adjacent to the collector region, is of opposite conductivity type thereto and forms a junction therewith opposite from the base-collector junction, said sink region being common to the plurality of transistors and comprising a high resistivity substrate having a plurality of discrete epitaxial wafers deposited upon discrete areas of the surface thereof forming collector regions for each of the plurality of transistors and wherein base and emitter regions are diffused into said collector regions by suitable means, and
- each of the emitter, base and collector electrodes and also to the common sink electrode are provided for making ohmic contacts to each of the emitter, base and collector electrodes and also to the common sink electrode, and wherein each of the base regions is more heavily doped than its respective collector region and the respective collector widths are sufficiently narrow so that minority carriers injected from the base region into the collector region will be swept across said collector region and into the sink region during satrated operation of each of said devices.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1053834D GB1053834A (it) | 1963-02-01 | ||
US255496A US3283171A (en) | 1963-02-01 | 1963-02-01 | Semiconductor switching device and circuit |
DEJ25186A DE1207010B (de) | 1963-02-01 | 1964-01-28 | Flaechentransistor mit einem Halbleiterkoerper mit vier Zonen abwechselnd entgegengesetzten Leitungstyps, Verfahren zum Herstellen und Schaltung solcher Flaechentransistoren |
FR961894A FR1388172A (fr) | 1963-02-01 | 1964-01-29 | Dispositif semi-conducteur et montage de circuits |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US255496A US3283171A (en) | 1963-02-01 | 1963-02-01 | Semiconductor switching device and circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
US3283171A true US3283171A (en) | 1966-11-01 |
Family
ID=22968584
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US255496A Expired - Lifetime US3283171A (en) | 1963-02-01 | 1963-02-01 | Semiconductor switching device and circuit |
Country Status (4)
Country | Link |
---|---|
US (1) | US3283171A (it) |
DE (1) | DE1207010B (it) |
FR (1) | FR1388172A (it) |
GB (1) | GB1053834A (it) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040144999A1 (en) * | 1995-06-07 | 2004-07-29 | Li Chou H. | Integrated circuit device |
US6849918B1 (en) | 1965-09-28 | 2005-02-01 | Chou H. Li | Miniaturized dielectrically isolated solid state device |
US6979877B1 (en) | 1965-09-28 | 2005-12-27 | Li Chou H | Solid-state device |
US7038290B1 (en) | 1965-09-28 | 2006-05-02 | Li Chou H | Integrated circuit device |
US11490947B2 (en) | 2015-05-15 | 2022-11-08 | Clear Intradermal Technologies, Inc. | Tattoo removal using a liquid-gas mixture with plasma gas bubbles |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19703780A1 (de) * | 1997-02-01 | 1998-08-06 | Thomas Frohberg | Trinom-Transistor |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2655610A (en) * | 1952-07-22 | 1953-10-13 | Bell Telephone Labor Inc | Semiconductor signal translating device |
US2809135A (en) * | 1952-07-22 | 1957-10-08 | Sylvania Electric Prod | Method of forming p-n junctions in semiconductor material and apparatus therefor |
US2851594A (en) * | 1956-05-09 | 1958-09-09 | Rca Corp | Frequency converter using four-zone transistor as oscillator-mixer |
US2938130A (en) * | 1957-09-27 | 1960-05-24 | Itt | Semi-conductor device for heat transfer utilization |
US3151254A (en) * | 1960-03-04 | 1964-09-29 | Siemens Ag | Transistor for high frequency switching |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2623105A (en) * | 1951-09-21 | 1952-12-23 | Bell Telephone Labor Inc | Semiconductor translating device having controlled gain |
DE1041163B (de) * | 1955-03-02 | 1958-10-16 | Licentia Gmbh | Elektrisch steuerbares Halbleitersystem, z. B. Flaechentransistor, aus einem einkristallinen Halbleiterkoerper |
DE1104071B (de) * | 1959-04-04 | 1961-04-06 | Siemens Ag | Vierschichten-Halbleiteranordnung mit einkristallinem Halbleiterkoerper und drei hintereinandergeschalteten pn-UEbergaengen mit abwechselnd entgegengesetzter Sperrichtung und Verfahren zu ihrer Herstellung |
-
0
- GB GB1053834D patent/GB1053834A/en active Active
-
1963
- 1963-02-01 US US255496A patent/US3283171A/en not_active Expired - Lifetime
-
1964
- 1964-01-28 DE DEJ25186A patent/DE1207010B/de active Pending
- 1964-01-29 FR FR961894A patent/FR1388172A/fr not_active Expired
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2655610A (en) * | 1952-07-22 | 1953-10-13 | Bell Telephone Labor Inc | Semiconductor signal translating device |
US2809135A (en) * | 1952-07-22 | 1957-10-08 | Sylvania Electric Prod | Method of forming p-n junctions in semiconductor material and apparatus therefor |
US2851594A (en) * | 1956-05-09 | 1958-09-09 | Rca Corp | Frequency converter using four-zone transistor as oscillator-mixer |
US2938130A (en) * | 1957-09-27 | 1960-05-24 | Itt | Semi-conductor device for heat transfer utilization |
US3151254A (en) * | 1960-03-04 | 1964-09-29 | Siemens Ag | Transistor for high frequency switching |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6849918B1 (en) | 1965-09-28 | 2005-02-01 | Chou H. Li | Miniaturized dielectrically isolated solid state device |
US6979877B1 (en) | 1965-09-28 | 2005-12-27 | Li Chou H | Solid-state device |
US7038290B1 (en) | 1965-09-28 | 2006-05-02 | Li Chou H | Integrated circuit device |
US20040144999A1 (en) * | 1995-06-07 | 2004-07-29 | Li Chou H. | Integrated circuit device |
US11490947B2 (en) | 2015-05-15 | 2022-11-08 | Clear Intradermal Technologies, Inc. | Tattoo removal using a liquid-gas mixture with plasma gas bubbles |
Also Published As
Publication number | Publication date |
---|---|
GB1053834A (it) | |
FR1388172A (fr) | 1965-02-05 |
DE1207010B (de) | 1965-12-16 |
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