US3256446A

US3256446A - Linearly-varying output voltage generation utilizing a transistorized, modified, miller integrator

Info

Publication number: US3256446A
Application number: US153381A
Authority: US
Inventors: Corney John Victor James
Original assignee: Ferguson Radio Corp Ltd
Current assignee: Ferguson Radio Corp Ltd
Priority date: 1960-11-23
Filing date: 1961-11-20
Publication date: 1966-06-14
Anticipated expiration: 1983-06-14
Also published as: GB955153A; DE1166253B

Description

June 14, 1966 J. v. J. CORNEY 3,256,446

LINEARLY-VARYING OUTPUT VOLTAGE GENERATION UTILIZING A TRANSISTORIZED, MODIFIED, MILLER INTEGRATOR Filed Nov. 20'. 1961 3 Sheets-Sheet 1 1 II o( e ,6 K|

ZO TR/GG PULSE "2 E VI June 14, 1966 J. v. J. CORNEY 3,256,446

LINEARLY-VARYING QUTPUT VOLTAGE GENERATION UTILIZING A TRANSISTORIZED, MODIFIED, MILLER INTEGRATOR Filed Nov. 20, 1961 5 Sheets-Sheet 2 fi TR/GGER C/RCU/T I7 CIOC L' J. V. J. CORNEY June 14, 1966 LINEARLY-VARYING OUTPUT VOLTAGE GENERATION UTILIZING A 5 Sheets-Sheet 5 J h W W mm. INK wv J mm s y 2 l1|/ Q R Q O mm/Nw EYW M M 'WS mm M mm mm a L a k on w L. m. R R vm An- 4 J .1 Cl i m RN mv om N Q N M A I. "ma mm B E 9 .2 a B 8 3 m 3 mm 8 8 ix @W K W mm w 1 R 3 M om H Q A? United States Patent 3 256 446 LINEARLY-VARYING bU'iPUT VOLTAGE GENER- ATION UTILIZING A TRANSISTORIZED, MODI- FIED, MILLER INTEGRATOR John Victor James Corney, London, England, assignor to Ferguson Radio Corporation Limited, London, England, a British company Filed Nov. 20, 1961, Ser. No. 153,381 Claims priority, application Great Britain, Nov. 23, 1960, 40,310/ 60 3 Claims. (Cl. 307-885) The present invention relates to voltage generation and is concerned with the generation of voltage which varies linearly with time.

A commonly known voltage generator for generating such voltages is usually referred to as a Miller integrator. The Miller integrator was devised before the advent of the transistor and in'its original form consisted basically of a thermionic valve (usually a pentode valve) with a resistive anode load, a capacitor connected between its anode and control grid and a resistor connected between the control grid and a source of positive grid potential.

On switching on such a circuit, current flows into the capacitance appearing at the control grid. The size of this capacitance is, however, dependent upon the gain of the valve circuit and can be expressed as (,u+1) C where p. is the magnification of the circuit and C is the total anode-to-control grid capacitance.

Thus by making ,u, C and the resistance in series with the control grid of suitable values the time constant of the circuit can readily be made such that only an initial fraction of the exponential fall in anode voltage need be used for a given purpose. It can be arranged that the circuit bottoms at the end of a selected initial fraction of the exponential fall.

Miller integrators have also been devised in which a transistor takes the place of the valve, the connections to the anode, cathode and control grid of the valve being replaced by connections to the collector, emitter and base electrodes of the transistor.

In both the valve and transistor versions of the Miller integrator although the initial fraction of the exponential fall of voltage is sufliciently linear for many purposes it is exponential nevertheless in form.

It is one object of the present invention to provide a modified Miller integrator employing a transistor in which the exponential variation in the output voltage can be avoided.

It is another object of the present invention to provide an improved method of generating a voltage which varies substantially linearly with time.

According to the present invention in a method of generating a voltage varying substantially linearly with time, a capacitor connected between the collector and base of a transistor is initially charged from a source of operating current connected to the collector electrode. This source is then isolated from the collector electrode and associated plate of the capacitor, and operating current is so applied to the base of the transistor as to produce a substantially linear variation of voltage at the collector electrode. Thus unlike the conventional transistor equivalent of the Miller integrator there is no resistor traversed by the collector current during generation of the linear voltage variation. Furthermore the source of collector current is isolated from the collector during generation of the linear voltage variation whereby the col- See lector current is during this time drawn solely from the said capacitor and any other capacitor connected to the collector. If there is only the first said capacitor connected to the collector electrode of the transistor and if the circuit through which operating current is applied to the base has resistance R in series therewith, provided solely or only partly by the internal resistance of the source, it can be shown that the rate at which the potential of the collector electrode changes is (V /R) (ct/C) where V is the voltage of the second source, on is the current gain of the transistor and C is the capacitance of the capacitor. Thus the variation in collector potential is linear until the circuit bottoms provided on is independent of collector potential down to the bottoming potential.

The invention also provides a circuit for generating a Voltage which varies linearly with time, the circuit comprising a transistor having a capacitor connected between the collector and base thereof, means for initially charging the capacitor from a source of operating current, means for isolating the said source from the collector and associated plate of the capacitor when the capacitor is charged, and further means for so applying current to the base of the transistor as to produce a substantially linear variation of voltage at the collector electrode of the transistor.

The invention will now be described, by way of example, with reference to the accompanying drawings, in which: I

FIG. 1 is a circuit diagram of apparatus for generating a substantially linear voltage variation,

FIG. 2 is an explanatory waveform diagram,

FIG. 3 is a circuit diagram of further apparatus for generating a linear voltage variation,

FIG. 4 is a circuit diagram of apparatus for producing a linear voltage variation of fixed duration commencing at a predetermined instant of time after the application of a triggering pulse to the apparatus, and

FIG. 5 is an explanatory waveform diagram.

Throughout the different figures of the drawings, like parts are given the same reference.

In FIG. 1 an NPN transistor 10 has its collector connected through a rectifier 11 to a terminal 12 and its emitter is grounded. Between the base and the emitter of the transistor two

rectifiers

13 and 14 are connected in series and arranged to have their directions of conduc tion to be the same as the base to emitter junction of the transistor. A capacitor 15 is connected between the collector of the transistor 10 and the wire connecting the two

rectifiers

13 and 14 to one another and a resistor 16 is connected between a terminal 17 and the base of the transistor. A trigger circuit 18 in the form of a flip-flop circuit has its two outputs of opposite polarity connected to the two

terminals

12 and 17 respectively, and a trigger pulse input terminal 19 is connected to the trigger circuit 18.

In operation, with the circuit in its quiescent state, the flip-flop circuit is arranged to provide an output of +V volts at the terminal 12 and substantially zero volts at the terminal 17. On the occurrence of a trigger pulse at the terminal 19 the flip-flop circuit 18 is triggered and is arranged to reduce the voltage at the terminal 12 to substantially zero and to raise the voltage at the terminal 17 to +V volts.

The triggering pulse and the changes in voltage at the

terminals

17 and 12 are shown by the

curves

20, 21 and 22 respectively in FIG. 2.

During the quiescent state the capacitor 15 is charged by current flowing from the flip-flop circuit 18 through the rectifier 11, the capacitor 15 and the rectifier 14 to ground. Thus by the incorporation of the rectifier 13 the heavy charging current of the capacitor 15 does not flow through the base-emitter junction of the transistor 10. The collector is at a potential of +V volts when the capacitor 15 is fully charged.

When the potential of the terminal 12 falls to zero and that of the terminal 17 rises to +V volts the rectifier 11 is rendered non-conducting and hence isolates the collector of the transistor from the source 18 of current. Thus the only source of collector current is the capacitor which starts to discharge.

Current flows from the terminal 17 through the resistor 16 into the circuit. Neglecting the forward base-toemitter volts drop, which is typically 0.1 volt, the current flowing through the resistor 16 is V /R where R is the resistance of the resistor 16.

The base current in the transistor 10 gives rise to an emitter current i and a collector current ai where u is the current gain of the transistor.

As previously described, the collector current, now defined as cci is drawn from the capacitor 15 and hence flows through the rectifier 13. The forward voltage drop across the rectifier 13 is substantially equal to the forward base-to-emitter voltage drop in the transistor and hence there is substantially zero potential difference across the rectifier 14 which does not, therefore, conduct.

The current flowing into the base of the transistor is (1(X)i and this current together with the current ui flowing into the capacitor 15 constitute the current flowing through the resistor 16.

Thus

i =V /R (i) The rate of change of potential of the collector electrode due to the discharge of the capacitor C is ai C where C is the capacitance of the capacitor 15.

From Equation i -ai /C=(-V/ /R)(d/C). Thus the fall of potential at the collector electrode is not exponential and is truly linear if on remains constant as the collector potential falls to the bottoming level. This linear fall is shown by the curve 23 in FIG. 2 and the duration t of the fall from +V volts to zero is (V /V (CR/a) seconds. Thus if V =V t=CR/a seconds.

The time t is substantially independent of variations between transistors since a varies but little from one transistor to another of the same type.

The initial conditions are restored if the terminal 17 is grounded and the terminal 12 is brought again to +V volts. The capacitor 15 then recharges through the diodes 11 and 14. The diode 13 prevents the flow of base current in the transistor due to the recharging of the capacitor and hence avoids the heavy collector current which would otherwise flow in the transistor.

Turning now to FIG. 3, this incorporates two modifications of FIG. 1. Firstly the diode 11 of FIG. 1 is replaced by a transistor 11' connected as shown with its base to the terminal 12, its emitter to the collector of the transistor 10 and its collector to a further terminal 12' to which a potential of at least +V volts is applied. Secondly a second capacitor 24 is connected between the collector and emitter of the transistor 10.

The transistor 11' acts as a switch between the collector electrode of the transistor 10 and the terminal 12' and is controlled by the flip-flop circuit 18.

In operation, during the fall of collector potential the collector current of transistor 10 is drawn from the two

capacitors

15 and 24. If their capacitances are C and C respectively it can be shown that the current in the capacitor 15 is (C ai )/(C +C and that the current in the 4 capacitor 24 is (C ai )/(C +C The duration 1 of the linear fall of collector potentials is 2 1) 1 2 B)l where fi=ot/(1oc). If V =V t=R [(C /a)+(C /B)].

Now if a lies between 0.9 and 1, C may be of the same order as C and may pass roughly the same current. Its value and presence have only a minor effect upon the time t however since C /fl will be small in comparison with C1/ (2.

Turning now to FIG. 4, this is a circuit arrangement embodying three generators as shown in FIG. 3, the three generators embodying the

transistors

10, 10' and 10 respectively. The aim of the circuit is, in response to a triggering pulse, to provide a linearly-varying output beginning at a predetermined period of time and then holding the output voltage for yet a further predetermined period of time at the value reached at the end of the linear variation.

An NPN transistor 25 functioning as an emitter-follower, between ground and an emitter supply bus 26, stabilizes the potential of the bus 26 at -v volts (say 1 volt) determined by a

potential divider

27, 28 connected between ground and a negative supply bus 29 and supplying control voltage to the base of the transistor 25. The bus 26 is decoupled by a capacitor 30.

A further transistor 31 connected between the stabilized bus 26 and the supply bus 29 is normally bottomed by base current supplied from the supply bus 29 through a resistor 32.

The collector electrode of the transistor 31 is connected through a diode 33 and an RC circuit 34 to the base of a further transistor 35. The base of this transistor is further connected through a resistor 36 to ground, and the cathode of the diode 33 is further connected through a resistor 37 to the supply bus 29.

It is arranged that when the transistor 31 is bottomed the transistor 35 is non-conducting by virtue of the feed to the base thereof through the diode 33 and the potential divider constituted by the resistors 36 and 37 in conjunction with the RC circuit 34.

It is further arranged that when the transistor 31 is rendered non-conducting, in a manner to be described later, this causes the transistor 35 to be bottomed.

It will be seen that the supply of operating potential to the collector electrodes of the

transistors

10, 10 and 10" is through the transistor 11' and then

diodes

38, 39 and 40 respectively whereby the three generators embodying the

transistors

10, 10 and 10" are controlled by the transistor 11' as in FIG. 3. This transistor is in turn switched on and oif by the transistor 35 in association with the transistor 31 whereby these latter two transistors with their associated circuit elements constitute the trigger circuit 18 of FIG. 3.

A transistor 42 connected as an emitter-follower has its base connected to the collector of the transistor 31 and when the latter is bottomed the emitter potential of the transistor 42 is substantially v volts. The emitter of the transistor 42 is connected through

resistors

43, 44 and 45 to the base electrodes of the

transistors

10, 10' and 10" respectively. Thus when the transistor 31 is bottomed and the emitter of the transistor 42 is at v volts no base current is fed to the

transistors

10, 10' and 10". With the transistor 31 bottomed the transistor 35 is cut off and the emitter of the transistor 11 is at substantially V volts and hence the

capacitors

15, 15 and 15" are charged through their associated

diodes

14, 14' and 14" to a voltage of (Vv) while the collectors of the

transistors

10, 10' and 10" are held at V volts. It will be seen that further capacitors 46 to 51 are also charged to -(Vv) volts through resistors 52 to 57 respectively.

The input terminal 19 is connected to the base of a transistor 58, the waveform of triggering signals applied to the input terminal 19 being as shown at 41 in FIG. 5. A diode 59 is connected between the base and the emitter of the transistor 58 and the emitter of the transistor 58 is connected through a capacitor 60 to the junction between two diodes 61 and 62 connected in series as shown between the emitter and base of the transistor 31.

The positive-going trigger pulse transmitted through the diode 59, the capacitor 60 and the diode 61 to the base of the transistor 31 is arranged to be such as to cut-oil the transistor 31. Thus the emitter voltage of the transistor 42 falls to substantially V volts as shown at 63 in FIG. 5 and base current is fed to the

transistors

10, and 10". The transistor 35 is bottomed whereby the base-to-emitter junction of the transistor 11' and the

diodes

38, 39 and 40 are reversed-biased by the charges in the capacitors 46 to 51 and 15, and 15", the potential of the emitter of the transistor 11' being at v volts as shown at 64 in FIG. 5.

The potential of the collector of the transistor 10 rises linearly, as shown by the waveform 65 in FIG. 5, until caught by an emitter-follower transistor 66 at a value determined by the setting of a potentiometer 67 connected to the base of the transistor 66. The elfect on the duration of the linear rise 65 of varying the setting of the potentiometer 67 as shown by the broken line extension of the rise 65 up to the limiting level of v volts.

It is arranged that the current in the capacitor 48 exceeds that in the resistor 32, and that the current in the capacitor 49 exceeds that in the resistor 44 and that the current in the capacitor 50 exceeds that in the resistor 45 during the rise of the collector potential of the tran sistor 10 whereby during this period the

transistors

31, 10 and 10" remain cut-off.

When the rise of the collector potential of the transistor 10 is caught as just described the transistor 10 is switched on by the current in the resistor 44 and the collector potential of the transistor 10 rises linearly as shown at 68 in FIG. 5 until the limiting value of v volts is reached. It is arranged that the current through the capacitor 47 exceeds that through the resistor 32, and the current through the capacitor 51 exceeds that through the resistor 45, whereby throughout the rise of the collector potential of the transistor 10 the transistors 31 and 10 remains cut-ofi.

When the transistor 10' bottoms the transistor 10" is switched on by the current flowing in the resistor 45 and the potential of the collector of the transistor 10" rises linearly as shown at 69 in FIG. 5.

By arranging that the time constant of the capacitor 46 and the resistor 32 is longer than the time taken for the linear rise (69 FIG. 5) of the collector potential of the transistor 10" to v'volts the transistor 31 remains cut-01f until this linear rise is completed.

When the transistor 10" bottoms the transistor 31 is switched on and the circuit conditions return to the initial state ready to receive the next triggering pulse.

The voltage appearing on the collector of the transistor 10' is applied through an RC circuit 70 to the base electrodes of two transistors 71 and 72 connected as emitterfollowers to an output terminal 73. Thus only the waveform 68 ('FIG. 5) appears at the output terminal 73.

It will be seen that the linear rise in this waveform begins at a time t after the leading edge of the triggering pulse 41 and determined by the duration of the linear rise of the potential of the collector electrode of the transistor 10. It will also be seen that'the linear rise occupies a time interval t determined by the constants of the generator embodying the transistor 10'. Finally the output voltage is held at the value v volts for a period i determined by the third generator embodying the transistor 10".

The transistor 58 and the diode 62 provide a path for the capacitor 60 to be recharged at the negative-going edge of the triggering pulse 41 ('FIG. 5). The diode 74 limits the reverse bias on the transistor 10 from the capacitor 49 so that the rise of the potential of the col lector of the transistor 10' begins rapidly when the col-' 'lector potential of the transistor 10 is caught by the transistor 66. The capacitor 75 in the RC circuit 34 improves the rate at which current in the transistor 35 is switched on and off.

The

diodes

38, 39 and 40 isolate the timing capacitors of each generator from the timing capacitors in the other generators. If desired, however, the diode 38 can be replaced by a short-circuit. The resistor 76 in the RC circuit 70 prevents damage to the diode 39 and to the transistors 10' and 11' should either of the transistors 71, 72 develop a base-to-collector short circuit.

The capacitor 77 in the RC circuit 70 reduces high-frequency loss at the output arising from the presence of the resistor 76. The capacitor 78 decouples the base of the transistor 66.

I claim:

1. A circuit for generating a voltage which varies substantially linearly with time comprising (a) a transistor having emitter, base and collector electrodes,

(-b) first and second series-connected rectifiers coupled between the base and emitter electrodes of said transistor, said first and second rectifiers being poled so that the direction of current flow therethrough is the same as that between the base and emitter electrodes within said transistor,

(c) a capacitor coupled between the junction of said series-connected rectifiers and the collector electrode of said transistor,

(d) means for coupling a source of operating current to the junction between said capacitor and the collector electrode of said transistor for initially charging said capacitor, said means isolating said source of operating current from said capacitor and the collector electrode of said transistor after said capacitor is charged, and

(e) resistive means coupling said source of operating current to the base electrode of said transistor, said circuit producing a substantially linear variation of voltage at the collector electrode of said transistor.

2. A circuit as defined by claim- 1 wherein said means for coupling a source of operating current to the junction between said capacitor and the collector electrode of said transistor is a rectifier, said rectifier being poled to permit current flow into said junction.

3. A circuit for generating a voltage which varies substantially linearly with time comprising (a) a hut transistor having emitter, base and collector electrodes,

(b) first and second series-connected rectifiers coupled between the base and emitter electrodes of said first transistor, said first and second rectifiers being poled so that the direction of current flow therethrough is the same as that between the base and emitter electrodes within said first transistor,

(c) a first capacitor coupled between the junction of said series-connected rectifiers and the collector electrode of said first transistor,

' (d) a trigger circuit having an input and first and second outputs,

(e) a second transistor having emitter, base and collector electrodes, the emitter electrode of said second transistor being coupled to the junction between said first capacitor and the collector electrode of said first transistor, the base electrode of said second transistor being coupled to the first output of said trigger circuit and the collector electrode of said second transistor being coupled to a voltage source,

(f) a resistor coupled between the base electrode of said second transistor and the second output of said trig ger circuit, and

(g) a second capacitor coupled between the collector and emitter electrodes of said first transistor, said circuit producing a substantially linear variation of 7 7 8 voltage at the collector electrode of said first tran- FOREIGN PATENTS 515m 209,959 8/1957 Australia. References Cited by the Examiner 1,090,717 10/1960 Germany.

UNITED STATES PATENTS 5 GEORGE N. WESTBY, Primary Examiner. 2,860,260 1 1/1958 Sykes. 2 372 09 2 1959 Smith 328 123 X LLOYD MCCOLLUM, A. SCHWARTZ, J. ZAZWOR- 2,897,453 7/1959 Mansford 328--185 X SKY, Examiners.

Claims

1. A CIRCUIT FOR GENERATING A VOLTAGE WHICH VARIES SUBSTANTIALLY LINEARLY WITH TIME COMPRISING (A) A TRANSISTOR HAVING EMITTER, BASE AND COLLECTOR ELECTRODES, (B) FIRST AND SECOND SERIES-CONNECTED RECTIFIERS COUPLED BETWEEN THE BASE AND EMITTER ELECTRODES OF SAID TRANSISTOR, SAID FIRST AND SECOND RECTIFIERS BEING POLED SO THAT THE DIRECTION OF CURRENT FLOW THERETHROUGH IS THE SAME AS THAT BETWEEN THE BASE AND EMITTER ELECTRODES WITHIN SAID TRANSISTOR, (C) A CAPACITOR COUPLED BETWEEN THE JUNCTION OF SAID SERIES-CONNECTED RECTIFIERS AND THE COLLECTOR ELECTRODE OF SAID TRANSISTOR, (D) MEANS FOR COUPLING A SOURCE OF OPERATING CURRENT TO THE JUNCTION BETWEEN SAID CAPACITOR AND THE COLLECTOR ELECTRODE OF SAID TRANSISTOR FOR INITIALLY CHARGING SAID CAPACITOR, SAID MEANS ISOLATING SAID SOURCE OF OPERATING CURRENT FROM SAID CAPACITOR AND THE COLLECTOR ELECTRODE OF SAID TRANSISTOR AFTER SAID CAPACITOR IS CHARGED, AND (E) RESISTIVE MEANS COUPLING SAID SOURCE OF OPERATING CURRENT TO THE BASE ELECTRODE OF SAID TRANSISTOR, SAID CIRCUIT PRODUCING A SUBSTANTIALLY LINEAR VARIATION OF VOLTAGE AT THE COLLECTOR ELECTRODE OF SAID TRANSISTOR.