US3102828A - Method of manufacturing semiconductor bodies - Google Patents

Method of manufacturing semiconductor bodies Download PDF

Info

Publication number
US3102828A
US3102828A US33291A US3329160A US3102828A US 3102828 A US3102828 A US 3102828A US 33291 A US33291 A US 33291A US 3329160 A US3329160 A US 3329160A US 3102828 A US3102828 A US 3102828A
Authority
US
United States
Prior art keywords
silicon
germanium
base
base member
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US33291A
Other languages
English (en)
Inventor
Courvoisier Jean
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
US Philips Corp
North American Philips Co Inc
Original Assignee
US Philips Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by US Philips Corp filed Critical US Philips Corp
Application granted granted Critical
Publication of US3102828A publication Critical patent/US3102828A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B11/00—Single-crystal growth by normal freezing or freezing under temperature gradient, e.g. Bridgman-Stockbarger method
    • C30B11/04—Single-crystal growth by normal freezing or freezing under temperature gradient, e.g. Bridgman-Stockbarger method adding crystallising materials or reactants forming it in situ to the melt
    • C30B11/06—Single-crystal growth by normal freezing or freezing under temperature gradient, e.g. Bridgman-Stockbarger method adding crystallising materials or reactants forming it in situ to the melt at least one but not all components of the crystal composition being added
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B19/00—Liquid-phase epitaxial-layer growth
    • C30B19/10—Controlling or regulating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/059—Germanium on silicon or Ge-Si on III-V
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/067—Graded energy gap
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/074—Horizontal melt solidification
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/936—Graded energy gap

Definitions

  • This invention relates to the manufacture of a semiconductor body consisting of two elements, for example silicon and germanium, which body contains at least one zone in which the ratio between the proportions of these elements shows a continuous variation.
  • a semiconductor body by depositing a semiconductor material, such as germanium or silicon, on a suitable base from vapour or by producing such material by the decomposition of a compound and precipitating it on a base layer.
  • a semiconductor material such as germanium or silicon
  • This method has a limitation in that it is diflicult to produce single crystal bodies in this manner.
  • At least one element is deposited on the surface of a base which contains the other element and has a melting point higher than that corresponding to the composition of the deposited material, while the temperature of the base is maintained at a value such that the surface is liquid.
  • the base layer is silicon and the deposited material is germanium; however, the deposited material may alternatively be a mixture of germanium and silicon.
  • the invention can also be employed for manufacturing bodies consisting at least partly of two elements forming a semiconductor compound.
  • the elements may contain impurities, which may be added deliberately.
  • FIGURE 1 shows schematically an apparatus for the deposition of semiconductor material.
  • FIGURE 2 is a constitutional diagram for mixtures of silicon and germanium
  • FIGURE 3 is a sectional view of a semiconductor body made by the method in accordance with the invention.
  • the apparatus shown in FIGURE, 1 comprises an annular cathode 1 of tungsten wire connected to a filament current supply.
  • a molybdenum screen 2 reflects parts of the electrons emitted from the cathode and protects a base 3, on which the material is deposited, against thermal radiation from the cathode.
  • the anodes are arranged on graphite supports 7 and 8.
  • the potentials of the anodes 5 and 6 can be adjusted independently by means of a double potentiometer 9, having two sliding contacts 10 and 11. As an alternative, however, these contacts may be coupled to one another so that, when one is at maximum potential, the other is at minimum potential, and conversely.
  • the supports 7 and 8 may be cooled in a manner not shown in the drawing, so that only the upper parts of the semiconductor bodies 5 and 6 are melted by the electron bombardment.
  • the base 3 which [comprises a single silicon crystal, can be heated by means of a filament 12.
  • the entire apparatus is arranged in an envelope adapted to be evacuated, which is not shown.
  • FIGURE 2 is a so-called phase diagram for mixtures of silicon and germanium, in which the ordinate represents the temperature in C. and the abscissae the silicon proportion of the mixture in atomic percent.
  • Both the solidus 2t and the liquidus 21 have a continuous variation from the melting point of silicon at 1420 C. to the melting point of germanium at 960 C. Owing to the fact that these elements can form a continuous series of mixed crystals but do not form an azeotropic system, there can be formed on the surface of the silicon base a layer in which the concentration of the silicon decreases gradually.
  • the process is initiated by heating the silicon base 3 to about 1400 C. Then a voltage of 5000 volts is applied to the silicon anode 5 and an appreciably lower voltage to the germanium anode 6.
  • the vapour produced will consist substantially of silicon. Gradually the first voltage is reducedand the second voltage is increased, until the vapour produced consists only of germanium.
  • the temperature of the base 3 is gradually reduced to the melting point of germanium, after which the entire heating system is switched out of circuit. Throughout the entire process, the temperature of the base is kept at a value such, depending upon the composition of the deposited material, that the surface layer is liquid.
  • the base can be heated to a temperature such that a liquid mixture of silicon and germanium is produced on the surface, and this mixture gradually contains less silicon in proportion as more germanium is deposited and the temperature is reduced.
  • a semiconductor body made in this manner is shown diagrammatically and greatly enlarged in FIGURE 3. It comprises a silicon layer 30, a layer 31 consisting of a mixture of silicon and germanium and a germanium layer 32. In the layer 31, the proportion of silicon gradually decreases towards the germanium layer 32. Obviously, the process can be stopped at an intermediate stage, for example, before the layer of pure germanium has been formed.
  • the invention can be employed in an analogous manner for manufacturing a body consisting at least in part of a semiconductor compound of two elements which should have a constitutional diagram similar to that of silicon and germanium, that is to say, a non-azeotropic diagram.
  • a method of making a semiconductive body containing an alloy portion of silicon and germanium comprising providing a single crystal base member of silicon,

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Exhaust Gas After Treatment (AREA)
  • Catalysts (AREA)
US33291A 1959-06-02 1960-06-01 Method of manufacturing semiconductor bodies Expired - Lifetime US3102828A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL239785 1959-06-02

Publications (1)

Publication Number Publication Date
US3102828A true US3102828A (en) 1963-09-03

Family

ID=19751761

Family Applications (1)

Application Number Title Priority Date Filing Date
US33291A Expired - Lifetime US3102828A (en) 1959-06-02 1960-06-01 Method of manufacturing semiconductor bodies

Country Status (3)

Country Link
US (1) US3102828A (ko)
DE (1) DE1446211A1 (ko)
NL (1) NL239785A (ko)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3267338A (en) * 1961-04-20 1966-08-16 Ibm Integrated circuit process and structure
US3271179A (en) * 1962-09-24 1966-09-06 Temescal Metallurgical Corp Method for the manufacture of an optical filter
US3275906A (en) * 1962-08-20 1966-09-27 Nippon Electric Co Multiple hetero-layer composite semiconductor device
US3322575A (en) * 1959-06-18 1967-05-30 Monsanto Co Graded energy gap photoelectromagnetic cell
US3338760A (en) * 1964-06-03 1967-08-29 Massachusetts Inst Technology Method of making a heterojunction semiconductor device
US3428474A (en) * 1964-06-24 1969-02-18 Bausch & Lomb Method for forming ceramic metallic bonds
DE1298512B (de) * 1964-03-13 1969-07-03 Telefunken Patent Einrichtung zum Aufdampfen einkristalliner Schichten auf Unterlagen
US3458368A (en) * 1966-05-23 1969-07-29 Texas Instruments Inc Integrated circuits and fabrication thereof
US3634149A (en) * 1966-10-25 1972-01-11 Philips Corp Method of manufacturing aluminium nitride crystals for semiconductor devices
US3766447A (en) * 1971-10-20 1973-10-16 Harris Intertype Corp Heteroepitaxial structure
US4165249A (en) * 1976-02-26 1979-08-21 Siemens Aktiengesellschaft Method of purifying germanium bodies
US4357183A (en) * 1980-08-13 1982-11-02 Massachusetts Institute Of Technology Heteroepitaxy of germanium silicon on silicon utilizing alloying control
US4861393A (en) * 1983-10-28 1989-08-29 American Telephone And Telegraph Company, At&T Bell Laboratories Semiconductor heterostructures having Gex Si1-x layers on Si utilizing molecular beam epitaxy
US5577642A (en) * 1994-05-06 1996-11-26 Nestec S.A. System for metering a product in powder form

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB737527A (en) * 1952-07-29 1955-09-28 Licentia Gmbh A method for the manufacture of semi-conductors having excess-conductive and deficitconductive regions with sharp borders
GB742237A (en) * 1951-10-24 1955-12-21 Ass Elect Ind Improvements in barrier layer cells
US2739088A (en) * 1951-11-16 1956-03-20 Bell Telephone Labor Inc Process for controlling solute segregation by zone-melting
US2780569A (en) * 1952-08-20 1957-02-05 Gen Electric Method of making p-nu junction semiconductor units
US2855334A (en) * 1955-08-17 1958-10-07 Sprague Electric Co Method of preparing semiconducting crystals having symmetrical junctions
GB805493A (en) * 1955-04-07 1958-12-10 Telefunken Gmbh Improved method for the production of semi-conductor devices of npn or pnp type
GB818564A (en) * 1954-10-29 1959-08-19 Telefunken Gmbh Improved method for the production of semiconductor bodies

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB742237A (en) * 1951-10-24 1955-12-21 Ass Elect Ind Improvements in barrier layer cells
US2739088A (en) * 1951-11-16 1956-03-20 Bell Telephone Labor Inc Process for controlling solute segregation by zone-melting
GB737527A (en) * 1952-07-29 1955-09-28 Licentia Gmbh A method for the manufacture of semi-conductors having excess-conductive and deficitconductive regions with sharp borders
US2780569A (en) * 1952-08-20 1957-02-05 Gen Electric Method of making p-nu junction semiconductor units
GB818564A (en) * 1954-10-29 1959-08-19 Telefunken Gmbh Improved method for the production of semiconductor bodies
GB805493A (en) * 1955-04-07 1958-12-10 Telefunken Gmbh Improved method for the production of semi-conductor devices of npn or pnp type
US2855334A (en) * 1955-08-17 1958-10-07 Sprague Electric Co Method of preparing semiconducting crystals having symmetrical junctions

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3322575A (en) * 1959-06-18 1967-05-30 Monsanto Co Graded energy gap photoelectromagnetic cell
US3267338A (en) * 1961-04-20 1966-08-16 Ibm Integrated circuit process and structure
US3275906A (en) * 1962-08-20 1966-09-27 Nippon Electric Co Multiple hetero-layer composite semiconductor device
US3271179A (en) * 1962-09-24 1966-09-06 Temescal Metallurgical Corp Method for the manufacture of an optical filter
DE1298512B (de) * 1964-03-13 1969-07-03 Telefunken Patent Einrichtung zum Aufdampfen einkristalliner Schichten auf Unterlagen
US3338760A (en) * 1964-06-03 1967-08-29 Massachusetts Inst Technology Method of making a heterojunction semiconductor device
US3428474A (en) * 1964-06-24 1969-02-18 Bausch & Lomb Method for forming ceramic metallic bonds
US3458368A (en) * 1966-05-23 1969-07-29 Texas Instruments Inc Integrated circuits and fabrication thereof
US3634149A (en) * 1966-10-25 1972-01-11 Philips Corp Method of manufacturing aluminium nitride crystals for semiconductor devices
US3766447A (en) * 1971-10-20 1973-10-16 Harris Intertype Corp Heteroepitaxial structure
US4165249A (en) * 1976-02-26 1979-08-21 Siemens Aktiengesellschaft Method of purifying germanium bodies
US4357183A (en) * 1980-08-13 1982-11-02 Massachusetts Institute Of Technology Heteroepitaxy of germanium silicon on silicon utilizing alloying control
US4861393A (en) * 1983-10-28 1989-08-29 American Telephone And Telegraph Company, At&T Bell Laboratories Semiconductor heterostructures having Gex Si1-x layers on Si utilizing molecular beam epitaxy
US5577642A (en) * 1994-05-06 1996-11-26 Nestec S.A. System for metering a product in powder form

Also Published As

Publication number Publication date
NL239785A (ko)
DE1446211A1 (de) 1969-02-06

Similar Documents

Publication Publication Date Title
US3102828A (en) Method of manufacturing semiconductor bodies
US3146123A (en) Method for producing pure silicon
US3047439A (en) Silicon carbide semiconductor device
US2789258A (en) Intrinsic coatings for semiconductor junctions
US2802759A (en) Method for producing evaporation fused junction semiconductor devices
US3615203A (en) Method for the preparation of groups iii{14 v single crystal semiconductors
US2909453A (en) Process for producing semiconductor devices
US2974072A (en) Semiconductor connection fabrication
US3278274A (en) Method of pulling monocrystalline silicon carbide
US3291657A (en) Epitaxial method of producing semiconductor members using a support having varyingly doped surface areas
US3370927A (en) Method of angularly pulling continuous dendritic crystals
US3121829A (en) Silicon carbide semiconductor device
US3573190A (en) Apparatus for depositing semiconductor material and forming semiconductor junctions
Shinozaki et al. Need of contamination for the epitaxial growth of iron on rocksalt
US2824269A (en) Silicon translating devices and silicon alloys therefor
US3966881A (en) Method of making a single crystal intermetallic compound semiconductor
US3753804A (en) Method of manufacturing a semiconductor device
US2841559A (en) Method of doping semi-conductive materials
US3058854A (en) Semiconductor alloys and method of preparing the same
US3226248A (en) Method of producing refractory monocrystalline boron structures
US3167512A (en) Method of controlling the distribution of doping substance in crucible-free zone-melting operations
US3152373A (en) Method of manufacturing semiconductor devices
US2997410A (en) Single crystalline alloys
JPH0645519B2 (ja) ｐ型ＳｉＣ単結晶の成長方法
US3141849A (en) Process for doping materials