US2930108A - Method for fabricating semiconductive devices - Google Patents

Method for fabricating semiconductive devices Download PDF

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Publication number
US2930108A
US2930108A US582723A US58272356A US2930108A US 2930108 A US2930108 A US 2930108A US 582723 A US582723 A US 582723A US 58272356 A US58272356 A US 58272356A US 2930108 A US2930108 A US 2930108A
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United States
Prior art keywords
solder
indium
semiconductive
metal
wafer
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Expired - Lifetime
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US582723A
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English (en)
Inventor
Richard A Williams
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Space Systems Loral LLC
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Philco Ford Corp
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Publication date
Priority to NL111786D priority Critical patent/NL111786C/xx
Priority to NL216978D priority patent/NL216978A/xx
Application filed by Philco Ford Corp filed Critical Philco Ford Corp
Priority to US582723A priority patent/US2930108A/en
Priority to FR1173399D priority patent/FR1173399A/fr
Priority to GB14161/57A priority patent/GB847628A/en
Priority to DEP18467A priority patent/DE1125551B/de
Application granted granted Critical
Publication of US2930108A publication Critical patent/US2930108A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor

Definitions

  • the aforementioned transit time shall be substantially the same for all of the minority carriers, thereby to obtain a constant phase shift between the emitter and collector elements for alternating signals whose periods are of the order of the transit time, it is necessary that the opposing surfaces of the emitter and collector ele-' ments be substantially plane and parallel to each other. Finally, to obtain optimum amplification at any frequency, it is necessary that the emitter element of the transistor have a high minority-carrier injection efficiency.
  • this transistor preferably comprises a body of semiconductive material containing a pair of opposed excavations, the bottom surfaces of which are substantially plane and parallel and separated by a distance substantially equal to the desired small distance between the emitter and collector elements.
  • a very high concentration of activator atoms is alloyed to an extremely small depth into the surface of the semiconductive material at the bottom of one of the excavations.
  • the desired alloy region has been formed by coating the latter surface with a metal, by applying the activator substance tothe metal coating, and by heating the coating and the activator with the underlying semiconductive material.
  • Another object of the invention is to provide an improved method of forming a rectifying junction in a body of semiconductive material and of bonding a conductive structure to said body.
  • An additional object of the invention is to provide an improved method of forming an emitter element on a semi-conductive body and of bonding a conductorto '70 substance sufiiciently to alloy the activator substance,
  • Yet another object of the invention is to provide an improved method of forming, on a semiconductive body, an emitter or collector element having a precisely deterposition, and to which a connecting lead is secured.
  • a further object of the invention is to provide an improved method for fabricating transistors which, be-
  • a specific object of the invention is to provide an' improved method for forming, on a semiconductive body, an exceptionally thin elementfor injecting minority carriers thereinto, and for bonding a conductor to said element
  • the method of my invention is utilized to form an emitter element on an ntype semiconductive body and to bond a conductive lead to this emitter element.
  • the metal coating applied to the semiconductive body is constituted of a metal of the acceptor type. applied between the conductive structure and the coating includes this metal as one component, and, as another component, includes a substance which is a ptype activator and which has a solubility, in the semiconductive body, substantially greater than that of the coating metal.
  • both the coating metal and the solder are heated above their respective melting points, thereby to melt together the c'oating'metal and the solder and to dissolve into this melt a portion ⁇ .of the semiconductive body contiguous thereto.
  • Patentedli/iar. 29, 1960 The solder The solder which .is
  • opposing surfaces of the semiconductive body are shaped to the desired configuration by electrolytic jet etching, and
  • the metal coating is applied to appropriate regions of these etched surfaces by electrolytic jet plating.
  • the activatorcontaining solder is coated onto one end of a conductive lead, and this end is abutted against one of the metal coatings. Heat is then applied to the solder in an amount just sufficient to melt the solder and the metal coating which it abuts.
  • the structure is then permitted to cool, thereby causing an extremely thin alloyed region to form beneath the surface of the semiconductive body adjoining the metal coating, and the conductive lead to be bonded to this region.
  • FIG 1 illustrates diagrammatically an electrochemical arrangement suitable for practicing certain steps of my novel method
  • Figure 2 depicts a transistor in an intermediate stage of its fabrication according to my method
  • Figure 3 is a diagram of an arrangement suitable for carrying out a further step of my method and;
  • Figure 4 illustrates diagrammatically a structure produced by practicing my method.
  • a high frequency transistor of the type described in the above-identified Rittmann application is fabricated in the following general manner: opposing surfaces of a wafer of n-type semi-' conductive material, e.g. n-type germanium, are electrolytically etched in a manner suchas to produce coaxial and opposing depressions whose bottom surfaces are spaced from one another by a predetermined small .dis-
  • the shape of the rectifying junction substantially a transistor will now be described in greater detail, with and additionally contains a small amount of a second p-type activator substance, e.g. gallium, having a solid solubility in germanium which is considerably greater than that of the indium.
  • Heat is then applied to the solder and the metal plating in an amount just suificient to melt them and to cause them to intermix and to dissolve a very small portion of the semiconductive material contiguous thereto.
  • the resultant mixture of the solder, the plating metal and the dissolved semiconductive material is then cooled below its freezing temperature, thereby to form a rectifying junction and simultaneously to bond the wire lead thereto.
  • the solid solubility in germanium of gallium is intrinsically very large and also is much greater than that of indium
  • the solid solution formed between the dissolved germanium and the mixture of plating metal and solder contains much more gallium than indium, and the gallium is present, in this solid solution, in a very high concentration, e.g. of the order of at least 10 atoms of gallium per cubic centimeter of germanium.
  • the rectifying junction formed by my process has a high injection efficiency and serves as an excellent emitter element.
  • theheating step is carried out at such a low temperature, e.g. 165 0., and-for such a short-time, e.g. of,the:0rder of 3-to 5 seconds, only a very thin layer beneath the surface of the semiconductiv'e body,
  • the process is eificient'in that it accomplishes, in one operation, both the formation of the rectifying junction and the bonding of the wire lead thereto.
  • the collector element of the transistor may be formed by carrying out steps similar to those used to form the emitter element.
  • the surface-barrier contact to the surface of the germanium, which is already provided by the indium electroplated thereon, may be utilized without further processing as a collector element.
  • a wire lead may be afiixcd thereto in a conventional manner, e.g. by utilizing a solder, such as an indium-cadmium eutectic mixture, having a melting point substantially lower than the melting point of indium.
  • a solder such as an indium-cadmium eutectic mixture
  • a nickel base tab 10 is first soldered, in a manner providing an ohmic contact, to one end of a wafer 12 of n-type germanium having a bulk resistivity in the range of 0.05 to 0.09 ohm-centimeters and a minority-carrier lifetime exceeding 50 microseconds.
  • wafer 12 may have a thickness of 0.002 inch, and a length and width of 0.100 inch and 0.050 inch respectively, and.
  • solder securing the base tab 10 thereto may be constituted primarily of tin.
  • the assembly consisting of wafer 12 and base tab 10 is then secured to a mounting structure 14 which comprises a cylindrical glass stem 16, in which are embedded three nickel-plated copper stem leads 18, 20 and 22, in parallel coplanar relationship to the axis of the stem, and a flanged metal shell 24 which tightly surrounds the glass stern.
  • the assembly is secured to the mounting structure by spot-welding base tab10 to the central stem lead 20 of structure 14.
  • the germanium wafer 12 is then positioned normal to and between a pair of opposing coaxial jets of electrolytic solution 26 and 28, respecwith light the surfaces to be etched.
  • the negative poteu-- tial is supplied to the jets by a source 34 via a doublepole, double-throw switch 36 and a current-limiting resistor 38.
  • switch 36 More particularly, the positive and negative terminals of source 34 are connected respectively to poles 40 and 42 of switch 36.
  • a first fixed contact 44 of switch 36 is connected by resistor 38 to inert electrodes 46 and 48 which are immersed in the streams of electrolytic solution supplying jets 26 and 28, respectively, while a second fixed contact 50 is connected to wafer 12 by way of stem lead 20.
  • Switch contact 50 also is connected directly to a third switch contact 52, while switch con tact 44 is connected, via a second current-limiting resistor 54, to a fourth switch contact 56. Accordingly, to produce electrolytic etching, switch 36 is closed to its upper pair of contacts, while to produce electrolytic plating,
  • the light for' irradiating the etched surfaces of wafer 12 is supplied by light sources 58 and 69, respectively,
  • each "of which comprises a housing 62, an electric bulb 64 and a condensing lens 66 for directing the light 'produced by bulb 64 onto the appropriate surface of wafer 12.
  • the bulbs 64 are energized by a source 68.
  • the electrolytic etching of wafer 12 is continued until the distance between the surfaces impinged by jets 26 and 28 has been reduced to approximately 0.0001 inch.
  • the value of the distance between the etched surfaces is continuously monitored during etching by arrangements such as the infra-red transmittance measuring system described and claimed in patent application Serial No. 449,347, now Patent No. 2,875,141, of Robert N. Noyce, filed August 12, 1954, and entitled Electrical Method and Apparatus, or by the punch-through voltage measuring system described and claimed in patent application Serial No. 575,159 of William E. Bradley and John Roschen, filed March 30, 1956 and entitled Electrochemical Method and Apparatus, both of which applications are assigned to the assignee of the present application.
  • electrolytic etching is discontinued by opening switch 36 from its upper contacts.
  • indium dots are causedto deposit electrolytically upon therespective etched surfaces of wafer 12 by closing switch 36 to its lower contacts, thereby applying to wafer 12 a negative potential which serves to discharge indium ions contained in the electrolytic solution which impinges the wafer.
  • the electroplating process is continued until a first dot approximately 0.003 inch in diameter and approximately 0.0005 inch thick at its thickest portion has deposited on the surface of wafer 12 impinged by jet 26, and a second dot approximately 0.006 inch in diameter and approximately 0.001 inch thick at itsthickest portion has deposited on the surface of wafer 12 im-. pinged by jet 28.
  • switch 36 is opened, discontinuing the electrolytic process.
  • Diameter of jet 26 at orifice of nozzle 30 Diameter of jet 28 at orifice of nozzle 32 Presure under which electro- -lyte is supplied to nozzle 30 0.003 inch.
  • the time required to etch germanium wafer 12 from an initial thickness of 0.002 inch to a final thickness of about 0.0001 inch is about one minute. Between 30 and 40 secondsv are then required to plate indiu'rn'dots' of appropriate sizeonto the etched:
  • the entire transistor assembly is rinsed in distilled water, thereby to remove the electrolytic solu tion, and is dried by means of an air jet.
  • Two wire leads for providing connections between stern leads 18 and 22 and the emitter and collector elements to be formed according to my invention, are now prepared by plating a globule of a special solder onto one end of each of two pure nickel wires, each having a diameter of approximately 0.001 inch, and by then bending each wire into an appropriate shape.
  • this special solder contains indium and, importantly, also contains a small amount of gallium.
  • the solder contains 99 percent by.weight of indium and 1 percent byweight of gallium, although it may contain as much as 2 percent, or as little as 0.5 percent, of gallium.
  • each salt is completely dissolved in the glycerol before the succeeding salt is added.
  • this solution is maintained at a.
  • the emitter element as finally formed, have a smaller diameter than that of the collector element so that, in operation, the collector element will intercept substantially all of those minority carriers injected by the emitter element which reach the surface to which the collector element is applied.
  • Figure 3 shows a greatly enlarged view, partially in cross-section, of the positioning of leads 7G and 76 with relation to a hairpin heater element 80.
  • heater element 80 is positioned closely to wire lead 70 which is itself oriented vertically upward from dot 74. In a typical case, heater element 80 may be spaced about a sixteenth of an inch from lead 70.
  • a source of alternating current 82 is connected to the primary winding 84 of a current step-up transformer 86 by way of a normally-open, momentarycontact switch 88, while the secondary winding 90 of transformer 86 is connected to the terminals of heater element 80.
  • a flux consisting of a saturated solution of zinc chloride in ethylene glycol is applied between solder globule 72 and indium dot 74.
  • the emitter element is formed within germanium wafer 12 beneath indium dot 74, and simultaneously wire lead 70 is bonded to this emitter element by heating indium dot 74 and solder globule 72 slightlyabove their respective melting points for a short time and then permitting the mixture of solder, indium and dissolved germanium so produced to cool below its melting point. More specifically, the globule and dot are heated radiatively by closing switch 88, thereby causing heater element 80 to be energized.
  • switch 88 may be closed intermittently over a period of approximately seconds.
  • Heater element 80 is de-energized as soon as globule 72 melts, a condition that is evidenced by a sagging of the .globule.
  • the transistor assembly is then allowed to cool, with the result that an alloy-junction.
  • emitter element forms just beneath the surface of wafer 12 upon which dot 74 initially was plated, and wire lead 70 becomes bonded to this emitter element. To assure strong bonding of lead 70 to the element, the transistor assembly is maintained stationary until the solder.
  • Figure 4 comprises a metallic mass 92 which consists primarily of indium and is firmly adherent to wire lead 70 and to the alloy region 94 formed just beneath the surface of germanium wafer. 12.
  • This alloyregion is constituted of a very high concentration of gallium in solid wafer 12 has substantially the same configurationas the surface to which indium dot 74 initially was applied, and the rectifying junction is spaced from the opposing etched surfaces of wafer 12 by substantially the original distance between the two etched surfaces.
  • the collector element is formed on the opposing surface of germanium wafer 12 by a technique sub: stantially identical to that used to form the emitter olement. Specifically the transistor assembly is rotated so that wire lead 76 associated with indium dot 78 extends vertically upward. therefrom and is positioned close to the heater element 89, and the aforedescribed fiuxing,
  • the collector junction. so produced is. also extremely thin, substantially conforming to the configuration of the surface to. which itis applied, and presents a highimpedance when reverse biased because of the .high concentration (Sf gallium atoms dissolved in the germanium of wafer 12.
  • a transistor is produced easily and quickly, whose emitter and collector elements have precisely predetermined sizes, shapes and positions relative to one another, and have wire leads attached thereto. Because such close control may be maintained over the geometry of the transistor elements, it is feasible to position the emitter and collector elements extremely close to each other without the danger that a short-circuit may occur therebetween. Consequently this process is especially useful for producing transistors designed to operate at high frequencies.
  • the assembly is first rinsed in distilled water, and is then air dried by a jet of air at room temperature.
  • base tab 10 and semiconductive Wafer 12 are next immersed for 3 seconds in a chemical etchant consisting of:
  • sistor assembly is potted in a plastic which, in a typical case, may be a thermosetting epoxy resin, and finally the assembly is hermetically sealed within a metal can (not shown) which is spot-welded to the flange 96 of shell 24.
  • the specific example of my novel method just described is merely exemplary, and that I do not intend to limit my invention thereto.
  • the depression formed in the semiconductive wafer 12 be produced by electrolytic etching.
  • wellknown sand-blasting techniques followed by chemical etching may be employed.
  • the metal plating applied to the excavated surfaces of the semiconductive body need not be electroplated thereon but, for example, may be evaporated thereon.
  • the indiumgallium solder need not be electroplated onto the'wire leads but alternatively may be introduced between the wire lead and the indium dot, at the appropriate time, in any 'they need not be electroplated thereon simultaneously from the same plating bath.
  • the indium is first electroplated onto the wire lead and thereafter the gallium is plated over the already-deposited indium.
  • the heat which is-utilized to melt the solder globule and the metal coating need not be applied radiatively, but may be applied by any one of a number of other well-known techniques. More specifically, such heat may be applied conductively via the wire lead, or alternatively, may be applied by directing a jet of hot gas in the vicinity of the solder globule, or by immersing semiconductive wafer 12 and its wire leads 70 and 76 in a bath of a fiuxing agent maintained at a temperature exceeding the melting point of the solder.
  • the bath may consist of either ethylene glycol or glycerol maintained at a temperature between 166 C. and C. and the semiconductive W iter and leads may be immersed therein'for 3 seconds.
  • the method is not limited to the fabrication of transistors comprising n-type germanium, waters, but may also be practiced in fabricating transistors comprising other n-type semiconductive bodies as well as p-type semiconductive bodies.
  • a method of fabricating a signal-translating device comprising a body of semiconductive material, the steps of: etching said semiconductive body so as to provide a pair of opposing surfaces having given configurations and separated by a given distance; coating metal over a portion of each of said surfaces; positioning, adjacent one of said metal coatings, a conductor and a solder containing an activator substance; heating said solder sufiiciently to melt it and to form a mixture be-' tween said activator substance and a portion of said semiconductive body contiguous said one metal coating, and cooling said mixture and said solder below their respective melting points, thereby to form a rectifying junction in said body and to bond said conductor to said body.
  • step of coating said body region with said activator metal includes the step of electroplating said activator metal onto said region.
  • said bod-y is composed of n-type germanium, wherein said solder consists essentially of indium and gallium, said gallium being present in said solder in a concentration between about 0.5 and about 2 percent by weight, and wherein said step of coating said body region with said activator metal comprises the step of electroplating indium onto said region.
  • solder consists essentially of said activator metal and a substance which is of said opposite impurity type and which has a solid solubility in said semiconductive body substantially greater than that of said activator metal.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Weting (AREA)
  • ing And Chemical Polishing (AREA)
US582723A 1956-05-04 1956-05-04 Method for fabricating semiconductive devices Expired - Lifetime US2930108A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
NL111786D NL111786C (xx) 1956-05-04
NL216978D NL216978A (xx) 1956-05-04
US582723A US2930108A (en) 1956-05-04 1956-05-04 Method for fabricating semiconductive devices
FR1173399D FR1173399A (fr) 1956-05-04 1957-03-28 Procédé de fabrication d'appareils semi-conducteurs
GB14161/57A GB847628A (en) 1956-05-04 1957-05-03 Improved method for fabricating semiconductive devices
DEP18467A DE1125551B (de) 1956-05-04 1957-05-03 Verfahren zur Herstellung eines legierten pn-UEbergangs sehr geringer Eindringtiefe in einem Halbleiterkoerper

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Application Number Priority Date Filing Date Title
US582723A US2930108A (en) 1956-05-04 1956-05-04 Method for fabricating semiconductive devices

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US2930108A true US2930108A (en) 1960-03-29

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US582723A Expired - Lifetime US2930108A (en) 1956-05-04 1956-05-04 Method for fabricating semiconductive devices

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US (1) US2930108A (xx)
DE (1) DE1125551B (xx)
FR (1) FR1173399A (xx)
GB (1) GB847628A (xx)
NL (2) NL111786C (xx)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3131454A (en) * 1959-11-12 1964-05-05 Philco Corp Semiconductor device and method for the fabrication thereof
US3154437A (en) * 1961-01-17 1964-10-27 Philco Corp Method for introducing an activator impurity substance into a portion of a body of crystalline semiconductive material and for bonding a lead member to said portion
US3197839A (en) * 1959-12-11 1965-08-03 Gen Electric Method of fabricating semiconductor devices
US3212160A (en) * 1962-05-18 1965-10-19 Transitron Electronic Corp Method of manufacturing semiconductive devices
US3264533A (en) * 1959-05-19 1966-08-02 Electrical Engineering Dept Three-electrode electrical translating device and fabrication thereof

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1199407B (de) * 1959-01-20 1965-08-26 Siemens Ag Verfahren zum Abtragen eines Halbleiterkoerpers mit pn-UEbergang eines Halbleiterbauelements durch AEtzen
US4966142A (en) * 1989-06-30 1990-10-30 Trustees Of Boston University Method for electrically joining superconductors to themselves, to normal conductors, and to semi-conductors

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2603693A (en) * 1950-10-10 1952-07-15 Bell Telephone Labor Inc Semiconductor signal translating device
US2750542A (en) * 1953-04-02 1956-06-12 Rca Corp Unipolar semiconductor devices

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE906955C (de) * 1952-03-28 1954-02-04 Licentia Gmbh Verfahren zur Erzeugung groesserer zusammenhaengender defektleitender Bereiche in den Aussenschichten von ueberschussleitenden Germaniumkristallen
GB761795A (en) * 1954-03-09 1956-11-21 Gen Electric Co Ltd Improvements in or relating to the manufacture of semi-conductor devices
FR1109512A (fr) * 1954-07-28 1956-01-30 Csf Perfectionnement aux transistors à jonctions et à leurs procédés de fabrication

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2603693A (en) * 1950-10-10 1952-07-15 Bell Telephone Labor Inc Semiconductor signal translating device
US2750542A (en) * 1953-04-02 1956-06-12 Rca Corp Unipolar semiconductor devices

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3264533A (en) * 1959-05-19 1966-08-02 Electrical Engineering Dept Three-electrode electrical translating device and fabrication thereof
US3131454A (en) * 1959-11-12 1964-05-05 Philco Corp Semiconductor device and method for the fabrication thereof
US3197839A (en) * 1959-12-11 1965-08-03 Gen Electric Method of fabricating semiconductor devices
US3154437A (en) * 1961-01-17 1964-10-27 Philco Corp Method for introducing an activator impurity substance into a portion of a body of crystalline semiconductive material and for bonding a lead member to said portion
US3212160A (en) * 1962-05-18 1965-10-19 Transitron Electronic Corp Method of manufacturing semiconductive devices

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Publication number Publication date
NL216978A (xx)
FR1173399A (fr) 1959-02-24
DE1125551B (de) 1962-03-15
GB847628A (en) 1960-09-14
NL111786C (xx)

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