US2772370A - Binary trigger and counter circuits employing magnetic memory devices - Google Patents

Binary trigger and counter circuits employing magnetic memory devices Download PDF

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Publication number
US2772370A
US2772370A US401674A US40167453A US2772370A US 2772370 A US2772370 A US 2772370A US 401674 A US401674 A US 401674A US 40167453 A US40167453 A US 40167453A US 2772370 A US2772370 A US 2772370A
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output
stage
input
core
winding
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US401674A
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English (en)
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George D Bruce
Joseph C Logue
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International Business Machines Corp
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International Business Machines Corp
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Priority to NL193550D priority Critical patent/NL193550A/xx
Priority to BE534549D priority patent/BE534549A/xx
Priority to US25262D priority patent/USRE25262E/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US401674A priority patent/US2772370A/en
Priority to GB37379/54A priority patent/GB766852A/en
Priority to FR1120525D priority patent/FR1120525A/fr
Priority to DEI9608A priority patent/DE1023613B/de
Application granted granted Critical
Publication of US2772370A publication Critical patent/US2772370A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
    • H03K3/30—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using a transformer for feedback, e.g. blocking oscillator
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/02—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements
    • G11C19/04—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using cores with one aperture or magnetic loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/76—Pulse counters comprising counting chains; Frequency dividers comprising counting chains using magnetic cores or ferro-electric capacitors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/45—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of non-linear magnetic or dielectric devices

Definitions

  • This invention relates to binary trigger circuits employing magnetic memory devices and counter circuits utilizing such binary trigger circuits.
  • a binary trigger circuit may be defined as a circuit which responds to two successive input pulses of the same polarity to produce a singl output pulse. Each output pulse may therefore be said to count a pair of input pulses.
  • a counter circuit may be defined as one which produces an output pulse corresponding to a given number of input pulses.
  • a binary trigger circuit is a sort of counter circuit.
  • Binary trigger circuits may be cascaded so that each stage in the cascade counts the output pulses from the preceding stage. If each stage is binary, then each succeeding stage provides a binary count of a higher order than the preceding stage. For example, the first stage counts by twos, the second by fours the third by eights, and so on.
  • a decimal counter circuit is one which produces an output pulse at the end of each series of ten successive input pulses.
  • decimal counter circuit comprising a number of binary stages coupled together.
  • Such a decimal counter is disclosed, for example, in the United States patent to Phelps, No. 2,584,811.
  • Transistors have recently become popular as electrical translating devices, especially in connection with high speed electrical computers, where their low power and low voltage requirements provide a tremendous advantage in installations which may employ thousands of such translating devices.
  • Such computers may employ many binary circuits and counters of the type described.
  • Binary trigger circuits have been proposed using transistors. Such circuits have been of the regenerative type, using a feedback from the output to the input, and have two stabl output states, separated substantially as to current and potential values, being triggered back and forth between their two output states in response to input signals.
  • the transistor is typically continuously conductive, either at a high or low current.
  • Such trigger circuits may be subject to difficulties due to hole storage" in the transistor, for example, an increased fall time or delay in reaching the low current state.
  • This continuous current may be considered as forming a memory of the last received signal and represents a substantial energy requirement which might be avoided by using pulse type signals and outputs and a memory device not requiring power.
  • transistors commonly have emitter input impedances much lower than their collector output impedances, so that special provisions are required for impedance matching between stages.
  • memory devices in current use, e. g., in the high speed computers previously mentioned, are magnetic memory devices Patented Nov. 27, 1956 ice which operate by magnetizing a core to the point of saturation in one direction. The state of polarization of the core is then utilized later to read the signal which was stored in the memory device by the polarizing action. The stored information is retained indefintely, until the 'stat (if magnetization of the core is changed by positively reversing it.
  • Such magnetic memory devices have been constructed having low power and voltage require 'ments of the same order as the corresponding requirements of transistors.
  • An object of 'the present invention is to provide a binary trigger circuit employing a magnetic memory device to retain the impression of the last received signal.
  • Another object of the invention is to provide a multiple stage counter circuit including in each stage a magnetic "memory device for retaining the impression of previously received signals.
  • a further object of the present invention is to provide circuits of the type described employing transistors.
  • Anot lrer object is to provide a binary trigger circuit employing transistors, and producing a pulse type output signal, rather than a steady output signal.
  • Another object is to provide a binary trigger circuit employing transistors and having improved impedance matching characteristics.
  • a binary trigger stage including a saturable magnetic core having two driving windings and two feedback windings.
  • Two amplifiers are provided for each stage, each amplifier having one driving Winding connected in its output circuit and one feedback Winding connected in its input circuit.
  • Each amplifier in the modifications shown and described, includes a transistor. Both amplifiers receive pulse signals from a common input.
  • the pulse output signals are derived from a special output winding on the saturable core. The design of this winding may be varied as required for impedance matching purposes.
  • the first three stages are binary stages so that the third stage counts eight input pulses.
  • the fourth stage is connected to count two additional input pulses after the eighth so that the output of the fourth stage provides a count of ten input pulses.
  • Figure 1 is a wiring diagram of a binary trigger circuit embodying the invention. h
  • Figure 2 is a wiring diagram of a modified form of binary trigger circuit embodying the invention.
  • Figure 3 is a wiring diagram of still another modified form of binary trigger circuit embodying the invention.
  • Figure 4 is a wiring diagram of a decimal counter circuit embodying the invention.
  • Figure 5 illustrates graphically the input signals and the signals at the outputs of the several stages in the circuit of Fig. 4.
  • FIGURE 1 There is shown in Figure l a binary trigger circuit ineluding a magnetic memory device generally indicated at 1 and having a saturable magnetic core 2, driving windings '3 and 4, feedback windings 5 and 6, and an output winding 7'.
  • the saturable core 2 is illustrated only diagrammatically in Fig. 1. It will be understood that a closed ring core is preferred, in accordance with the usual practice in such devices.
  • the amplifier 8 includes a transistor 10 of the PNP junction type, having an emitter electrode ltle, a collector electrode 10c and a base electrode 10b.
  • Amplifier 9 similarly include a PNP junction transistor 11 having an emitter electrode lle, a collector electrode 11c, and a base electrode 11b.
  • the input circuits of both amplifiers 8 and 9 receive signals from a pair of input terminals 12 and 13 through an input transformer 14 having a primary winding 15 and a secondary winding 16.
  • the input circuit of amplifier 8 may be traced from emitter electrode 10e through secondary winding 16, wires 17, 18 and 19, and feedback winding 5 to base electrode 10b.
  • the input circuit for amplifier 9 may similarly be traced from emitter electrode lle through secondary winding 16, wires 17 and 18, and feedback winding 6 to base electrode 11b.
  • the output circuit of amplifier 8 may be traced from collector electrode 100 through driving winding 3, battery 20, wires 18 and 19, and feedback winding 5 to base electrode 10b.
  • the output circuit of amplifier 9 may similarly be traced from collector electrode 110 through driving winding 4, battery 20, wire 18 and feedback winding 6 to base 11b.
  • Output winding 7 is connected to output terminals 22 and 23 through an asymmetric impedance device 24.
  • the driving windings 3 and 4 are connected so that currents of the same polarity flowing through them tend to magnetize the core 2 in opposite senses. Furthermore, the feedback windings 5 and 6 are connected so that the potentials induced in them by a change in current in their respectively associated driving windings 3 and 4, act on the input circuits of the respective transistors 10 and 11 in a sense to increase the emitter currents thereof, and thereby act cumulatively to increase the collector current flow in the winding 3 or 4, as the case may be. In other words, the windings 5 and 6 provide positive feed backs from windings 2 and 3, respectively, to the amplifiers 8 and 9 respectively.
  • Both amplifiers are normally connected to their re spective windings on the magnetic memory device, both are normally cut off and the core 2 is normally magnetically saturated in one direction or the other.
  • both amplifiers 8 and 9 respond by sending currents through the driving windings 3 and 4. Since the core 2 is already saturated in one direction, the current through one of the driving windings is substantially ineffective to change the magnetic condition of the core, and consequently the amplifier associated with that driving winding receives no feedback impulse and is cut olf. On the other hand, the current flowing in the other driving winding is effective to decrease the magnetization of the core.
  • This change in the magnetization of the core produces a potential in the associated feedback winding in the proper direction to amplify the current in the driving winding. This cumulative process continues until the polarity of the core 2 is reversed and the core is saturated in the opposite direction. The driving ampli bomb is then cut off.
  • the output signals are pulses of limited duration, and that after each output signal, the amplifiers are both restored to their cut off condition.
  • winding 7 may be varied as required for impedance matching purposes.
  • FIGURE 2 This figure illustrates a modified form of binary trigger circuit, in which the input circuits are connected in a somewhat ditferent manner than in the circuit of Fig. 1. Specifically, the amplifiers are provided with base inputs rather than emitter inputs. The circuit and its operation are otherwise substantially the same as in Fig. 1.
  • each circuit element in Fig. 2 has been given the same reference numeral as its counterpart in Fig. l and the circuit of Fig. 2 will not be further described.
  • FIGURE 3 This figure illustrates a modified form of trigger circuit employing the principles of the invention.
  • a magnetic memory device 26 including a saturable ring core 27 on which are provided two driving windings 28 and 29, two feedback windings 30 and 31, and an output winding 32.
  • the amplifier 33 includes a point contact transistor having a body 35 of n-type semi-conductive material, an emitter elec trode 35s, a collector electrode 35c and a base electrode 35b.
  • the amplifier 34 includes a transistor having a body 36 of n-type semi-conductive material, an emitter electrode 362, a collector electrode 360 and a base electrode 36b.
  • the input circuit of amplifier 33 may be traced from emitter 35c through a resistor 37, a battery 38, battery 39, secondary winding 40 of an input transformer 41, wire 42 and feedback winding 30 to base electrode 35b.
  • An asymmetric impedance unit 43 is connected between emitter electrode 35c and ground.
  • the input circuit for amplifier 34 may be traced from emitter electrode 36c through wire 44, resistor 37, batteries 38 and 39, secondary winding 40, wire 45 and feedback winding 31 to base electrode 36b.
  • the input transformer 41 is provided with a primary winding 46 connected to input terminals 47 and 38.
  • the output circuit of amplifier 33 may be traced from collector electrode 35c through driving winding 28, battery 49, battery 39. secondary winding 40, wire 42, and feedback winding 30 to base electrode 352;.
  • the output circuit of amplifier 34 may similarly be traced from collector 36c through driving winding 29, battery 49, battery 39, secondary winding 40, wire 45, and feedback winding 31 to base electrode 36b.
  • Output winding 32 is connected to output terminals 50 and 51.
  • FIGURE 3 The circuit of Fig. 3 and its operation are generally analogous to those in Figs. 1 and 2, except for the novel biasing arrangement for the two input circuits, including battery 38, resistor 37 and asymmetric impedance unit 43. These three circuit elements form a closed loop whose function is to supply, to the two emitters c and 366, a constant amount of current which is suflicient to maintain only one of the two amplifiers 33 and 34 in its On condition.
  • This input current supply arrangement cooperates with the blocking action due to the polarity of magnetization of the core 27 to prevent more than one of the two amplifiers from being On at any given time.
  • the following table shows, by way of example, a particular set of values for the potentials of the various batterics and for the impedance of the various resistors, in a circuit which has been operated successfully. It will be understood that these values are set forth by way of example only and that the invention is not limited to these values or any of them. No value is given for the asymmetric impedance element 43, which may be considered to have substantially zero impedance in its forward direction and substantially infinite impedance in its reverse direction.
  • FIGURE 4 This figure illustrates a decimal counter circuit including four stages, each of which is generally equivalent to the binary trigger circuit illustrated in Figure 3.
  • the four stages are respectively indicated by the reference numerals 52, 53, 54 and 55.
  • the individual circuit elements in each of the four stages correspond exactly to their counter parts in Figure 3. Consequently, those elements have been given the same reference numerals and will not be further described.
  • the output winding 32 of the stage 52 serves as an input winding for stage 53.
  • the output winding for stage 53 serves as an input winding for stage 54.
  • the two amplifiers 33 and 34 in the final stage 55 are provided with separate input circuits, instead of being connected to a common input circuit, as in the other stages.
  • Amplifier 34 has its input circuit connected to the output winding 32 of stage 54, and the input circuit of amplifier 33 is connected to a second output winding 56 in stage 52.
  • the final stage 55 is provided with two output windings, the normal output winding 32 which is connected to output terminals 57 and 58 through an asymmetric impedance element 59, and a second output winding 60 which is connected through a wire 61 and an asymmetric impedance element 62 to the input circuit of the second stage 53.
  • the output pulse applied through winding 60 and wire 61 is effective in the input of stage 53 to block the output pulse from stage 52 which corresponds to the tenth in the series of input pulses.
  • the output signal produced at winding 32 in stage 55 is transmitted to the output terminals 57 and 58, where it represents a decimal count of the input signals.
  • Figure 5 illustrates graphically a series of ten input pulses 63, which are applied through transformer 41 to the input stage 52.
  • the pulses 63 produce output pulses 64 in winding 32 of stage 52, these output pulses being of alternately opposite polarities.
  • the output pulses are transmitted through output winding 32 of stage 52, to the input circuits of stage 53.
  • the negative pulses are of the wrong polarity to produce any efiect in stage 53.
  • the positive pulses are effective to actuate stage 53, producing in its output winding 32 signal pulses 65, which are also alternately of opposite polarities. These output pulses 65 are transmitted to the input circuits of stage 54.
  • the negative output pulses are ineffective to actuate stage 54, but the positive output pulses produce output signals 66 in output winding 32 of stage 54.
  • one positive output pulse 64 is produced for each two input pulses 63
  • one positive output pulse 65 is produced for each four input pulses 63
  • one positive output pulse 66 is produced for each eight input pulses 63.
  • the three stages 52, 53 and 54 therefore constitute a three order binary counter circuit.
  • the negative output pulse 66 from stage 54 is ineffective to actuate stage 55, since its polarity is in the wrong direction.
  • the positive output pulse 66 which corresponds to the eighth input pulse 63 is effective to actuate the amplifier 34 in stage 55, in a sense to produce a negative pulse 67 in output winding 32 of stage 55, which negative output pulse is suppressed by the asymmetric impedance element or diode 59.
  • the ninth input signal pulse 63 has no effect beyond the first stage, but the tenth input pulse is transmitted from the first stage through output winding 56 to the input circuit of amplifier 33 in stage 55, where it is effective to actuate that stage to produce a positive output pulse 68 in each of windings 32 and 60.
  • This positive output pulse is transmitted through asymmetric impedance element 59 to the output terminals 57 and 58, where it provides a decimal count of the input signal pulses. It is also trans mitted through wire 61 and asymmetric impedance ele meat 62 to the input circuit of stage 53, where it serves to counteract and suppress the corresponding output signal 64 received from stage 52, so that the signal pulse is ineffective to actuate the stage 53, and the counter circuit is then ready to count the next series of ten input pulses.
  • a binary trigger circuit comprising a memory device having a saturable magnetic core, a pair of saturating windings on said core, a pair of saturating means, each including one of said windings, both saturating means being operable in response to input signals of limited duration and of only one predetermined polarity to initiate a variation of the magnetic flux in the core in respectively opposite senses and to continue that variation to saturation, each of said saturating means including limiting means effective to prevent operation of its associated saturating means when the core is saturated in its direction, means to deliver input signals of said limited duration and predetermined polarity simultaneously to both said saturating means, so that successive input signals are effective to saturate the core alternately in opposite directions, and signal output means responsive to variation of the flux in the core in one sense only.
  • a binary trigger circuit comprising a memory device including a saturable magnetic core, means for saturating said core with magnetic flux in selectively opposite directions, including two driving windings on said core, two feedback windings on said core, two amplifying means, each including an output circuit and an input circuit, each of said output circuits including one of said driving windings, each of said input circuits including one of said feedback windings, the driving and feedback windings for each amplifying means being connected to provide positive feedback, the feedback windings for the respective amplifying means being connected to provide feedback signals of opposite polarities upon a change in magnetic flux in said core in a given sense, the driving windings being connected to vary the magnetic flux in the core in opposite senses in response to input signals of a predetermined polarity, and means for supplying input signal pulses of limited duration and of said polarity simultaneously to both input circuits, so that successive input signals are effective to saturate the core alternately in opposite directions, and signal output means responsive to variation of the flux in the core in one
  • each said amplifying means comprises a transistor operable selectively in On and Off conditions.
  • each said transistor comprises an emitter electrode; and including common biasing means for both emitter electrodes including constant current supply means arranged to supply only sufficient current to maintain one transistor in its On condition.
  • a binary counter circuit comprising: at least two binary trigger stages, each said trigger stage including a memory device having a saturable magnetic core, a pair of saturating windings on said core, a pair of saturating means, each including one of said windings.
  • both saturating means being operable in response to input signals of only one predetermined polarity to vary the magnetic flux in the core in respectively opposite senses and to the point of saturation, each of said saturating means including limiting means effective to prevent operation of its associated saturating means when the core is saturated in its direction; means to deliver input signals of said predetermined polarity simultaneously to both the saturating means of the first stage, so that successive input signals are effective to saturate the core alternately in opposite directions; coupling means including an output winding on the core of said first stage for transmitting output signals of opposite polarities due to variation of the core flux of the first stage in opposite senses to both the saturating means of the second stage, said second stage saturating means being responsive to signals of one polarity only; and signal output means including an output winding on the core of said second stage and responsive to variation of the flux in the second stage core in one sense only.
  • a decimal counter circuit comprising four binary trigger stages, each said trigger stage including a memory device having a saturable magnetic core, a pair of saturating windings on said core, a pair of saturating means, each including one of said windings, both saturating means being operable in response to input signals of predetermined polarity to vary the magnetic flux in the core in respectively opposite senses and to the point of saturation, each of said saturating means including limiting means effective to prevent operation of its associated saturating means when the core is saturated in its direction, means to deliver input signals of said predetermined polarity simultaneously to both the saturating means of the first stage, so that successive input signals are effective to saturate the core alternately in opposite directions; first and second coupling means including output windings on the cores of said first and second stages for transmitting output signals due to variation of the core flux of each of said first and second stages to both the saturating means of the succeeding stage; third coupling means including an output winding on the core of the third
  • a binary trigger circuit comprising amplifier means, means to transmit input signal pulses of limited duration to said amplifier means, a memory device shiftable between two distinct memory conditions and stable in either of said conditions without the expenditure of energy, means including said amplifier means effective upon successive input signal pulses to shift said memory device alternately from one condition to the other and back again, and signal output means operated by said memory device to produce an output signal only when said device shifts from a particular one of said conditions to the other.
  • a binary trigger circuit comprising transistor means, means to transmit input signal pulses of limited duration to said transistor means, a memory device shiftable between two distinct memory conditions and stable in either of said conditions without the expenditure of energy, means including said transistor means effective upon successive input signal pulses to shift said memory device alternately from one condition to the other and back again, and signal output means operated by said memory device to produce an output signal only when said device shifts from one of said conditions to the other.
  • said memory device comprises a saturable magnetic core and said two conditions comprise saturation of the core with magnetic fields of opposite polarities.
  • a magnetic memory device including a saturable magnetic core, means for saturating the said core with magnetic flux including a driving winding on said core and a feedback winding on said core, amplifying means including an output circuit and an input circuit, means normally effective to cut off substantially the flow of current in said output circuit, means connecting said driving winding electrically in said output circuit, means connecting said feedback winding electrically in both said input and output circuits, said feedback winding being arranged both magnetically and electrically, to provide positive feedback, means independent of said feedback winding for supplying an input pulse of limited duration to said input circuit, said driving and feedback windings being effective in response to such an input signal to produce in said driving winding a current continuing until the core becomes saturated.
  • a magnetic memory device including a saturable magnetic core, means for saturating said core with magnetic flux in selectively opposite directions, including two driving windings on said core, two feed back windings on said core, two amplifying means, each including an output circuit and an input circuit, means normally efiective to cut off substantially the flow of current in both said output circuits, each of said output circuits including one of said driving windings, each of said input circuits including one of said feedback windings, the driving and feedback windings for each amplifying device being connected to provide positive feedback, the feedback windings for the respective amplifying means being connected to provide feedback signals of opposite polarities upon a change in magnetic flux in said core in a given sense, the driving windings being connected to vary the magnetic flux in the core in opposite senses in response to input signals of a predetermined polarity, and means external to said feedback windings for supplying input signals of limited duration simultaneously to said input circuits, each said signal being effective to turn on only one of said amplifying means, depending

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  • Power Engineering (AREA)
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US401674A 1953-12-31 1953-12-31 Binary trigger and counter circuits employing magnetic memory devices Expired - Lifetime US2772370A (en)

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Application Number Priority Date Filing Date Title
NL193550D NL193550A (is") 1953-12-31
BE534549D BE534549A (is") 1953-12-31
US25262D USRE25262E (en) 1953-12-31 Input
US401674A US2772370A (en) 1953-12-31 1953-12-31 Binary trigger and counter circuits employing magnetic memory devices
GB37379/54A GB766852A (en) 1953-12-31 1954-12-24 Binary trigger and counter circuits employing magnetic memory devices
FR1120525D FR1120525A (fr) 1953-12-31 1954-12-28 Déclencheurs binaires et circuits de comptage utilisant des dispositifs de mémoiremagnétiques
DEI9608A DE1023613B (de) 1953-12-31 1954-12-30 Binaere Trigger- und Zaehlerkreise unter Verwendung magnetischer Speicher

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US3056931A (en) * 1958-05-07 1962-10-02 Itt Transistorized generator of telephone ringing current
US3060324A (en) * 1957-12-31 1962-10-23 Bell Telephone Labor Inc High current transistor pulser
US3061797A (en) * 1957-11-07 1962-10-30 Bell Telephone Labor Inc Shifting reference transistor oscillator
US3067378A (en) * 1960-03-17 1962-12-04 Gen Electric Transistor converter
US3076925A (en) * 1960-03-29 1963-02-05 North Electric Co Current supply apparatus
US3079542A (en) * 1960-03-29 1963-02-26 North Electric Co Current supply apparatus
US3089077A (en) * 1958-10-06 1963-05-07 Basler Electric Co Transistor converters
US3102206A (en) * 1958-06-11 1963-08-27 Gen Electric Saturable current transformer-transistor circuit
US3134023A (en) * 1958-04-11 1964-05-19 Ibm Protection of transistor circuits against predictable overloading
US3135832A (en) * 1960-12-20 1964-06-02 Electro Mechanical Res Inc Current transformer coupling means for time sequential switching of low level signals
DE1172723B (de) * 1962-03-07 1964-06-25 Telefunken Patent Bistabile Kippschaltung mit zwei Transistoren und einem Speicherkern, insbesondere zur Verwendung in elektronischen Speicher-schaltungen fuer die Pegelregelung in der Traegerfrequenz-Nachrichtentechnik
US3157864A (en) * 1961-01-09 1964-11-17 Gulton Ind Inc Controil for magnetic memory matrix
US3162768A (en) * 1954-05-03 1964-12-22 Ibm Magnetic core deca-flip
US3193691A (en) * 1959-12-23 1965-07-06 Ibm Driver circuit
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US3278918A (en) * 1963-02-18 1966-10-11 Gen Signal Corp Binary counter
US3683208A (en) * 1970-12-23 1972-08-08 North Electric Co Power supply circuit arrangement utilizing regenerative current feedback
US3988575A (en) * 1973-12-14 1976-10-26 R. Alkan & Cie Magnetic-doughnut memorizing device for counting system

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US3225305A (en) * 1954-04-29 1965-12-21 Franklin F Offner Symmetrical transistor amplifier which is self-compensating with respect to changes in temperature
US3162768A (en) * 1954-05-03 1964-12-22 Ibm Magnetic core deca-flip
US2933620A (en) * 1954-05-27 1960-04-19 Sylvania Electric Prod Two-input ring counters
US2860258A (en) * 1954-09-17 1958-11-11 Bell Telephone Labor Inc Transistor decade counter
US3017084A (en) * 1954-11-26 1962-01-16 Raytheon Co Magnetic core shift register
US2876438A (en) * 1955-01-20 1959-03-03 Burroughs Corp Regenerative shift register
US2910594A (en) * 1955-02-08 1959-10-27 Ibm Magnetic core building block
US2954481A (en) * 1955-03-17 1960-09-27 Sperry Rand Corp Digital multivibrator
US3001084A (en) * 1955-06-28 1961-09-19 Sperry Rand Corp Magnetic amplifier without ringback
US2964693A (en) * 1955-08-17 1960-12-13 Honeywell Regulator Co Current regulator
US2964694A (en) * 1955-08-17 1960-12-13 Honeywell Regulator Co Electrical regulating apparatus
US2931863A (en) * 1955-08-23 1960-04-05 Gen Telephone Lab Inc Automatic electronic telephone system
US2925958A (en) * 1955-10-25 1960-02-23 Kienzle Apparate Gmbh Method and apparatus for counting electrical impulses
US2937332A (en) * 1955-12-19 1960-05-17 Gordon H Cork Magnetic relay
US2958075A (en) * 1956-01-30 1960-10-25 Sperry Rand Corp Shift register
US3020117A (en) * 1956-06-05 1962-02-06 Philips Corp System for controlling a plurality of writing heads
US3017611A (en) * 1956-07-02 1962-01-16 Ericsson Telefon Ab L M An assembly for counting marking impulses in an automatic telephone system
US2849624A (en) * 1956-08-31 1958-08-26 Richard L Snyder Saturable reactance circuits
US2885149A (en) * 1956-09-04 1959-05-05 Ibm Transistor full adder
US3026422A (en) * 1956-10-22 1962-03-20 Gen Electric Co Ltd Transistor shift register with blocking oscillator stages
US2971332A (en) * 1956-11-13 1961-02-14 Bendix Corp Electrical timing control apparatus
US3001711A (en) * 1956-12-03 1961-09-26 Ncr Co Transistor adder circuitry
US2941090A (en) * 1957-01-31 1960-06-14 Rca Corp Signal-responsive circuits
US3024367A (en) * 1957-03-22 1962-03-06 Philips Corp Bistable circuit arrangement
US2903601A (en) * 1957-03-29 1959-09-08 Burroughs Corp Transistor-magnetic core relay complementing flip flop
US2912681A (en) * 1957-05-08 1959-11-10 Paull Stephen Counter circuit
US2955264A (en) * 1957-05-24 1960-10-04 Rca Corp Modulation system
US3007142A (en) * 1957-06-06 1961-10-31 Ibm Magnetic flux storage system
US2925469A (en) * 1957-08-02 1960-02-16 Rca Corp Multiplex modulation communication system
US3061797A (en) * 1957-11-07 1962-10-30 Bell Telephone Labor Inc Shifting reference transistor oscillator
US3010096A (en) * 1957-12-27 1961-11-21 Westinghouse Electric Corp Counter circuit
US2989651A (en) * 1957-12-31 1961-06-20 Bell Telephone Labor Inc Transistor pulse generator
US3060324A (en) * 1957-12-31 1962-10-23 Bell Telephone Labor Inc High current transistor pulser
US2966595A (en) * 1957-12-31 1960-12-27 Ibm Pulse sensing system
US3134023A (en) * 1958-04-11 1964-05-19 Ibm Protection of transistor circuits against predictable overloading
US2953741A (en) * 1958-04-21 1960-09-20 Westinghouse Electric Corp Magnetic amplifiers
US3056931A (en) * 1958-05-07 1962-10-02 Itt Transistorized generator of telephone ringing current
US3030521A (en) * 1958-05-29 1962-04-17 William H Lucke Magnetic core binary counter
US3002107A (en) * 1958-06-02 1961-09-26 Ibm Transformer coupling of logical circuits
US3018389A (en) * 1958-06-03 1962-01-23 Rca Corp Delay circuit using magnetic cores and transistor storage devices
US3102206A (en) * 1958-06-11 1963-08-27 Gen Electric Saturable current transformer-transistor circuit
US3047731A (en) * 1958-07-14 1962-07-31 Smith Corona Marchant Inc Magnetic core circuit
US3089077A (en) * 1958-10-06 1963-05-07 Basler Electric Co Transistor converters
DE1134710B (de) * 1958-11-07 1962-08-16 Standard Elektrik Lorenz Ag Bistabile Kippschaltung mit dauernder Speichereigenschaft bei Ausfall der Betriebsspannung
US3036221A (en) * 1958-11-07 1962-05-22 Int Standard Electric Corp Bistable trigger circuit
DE1110218B (de) * 1958-11-08 1961-07-06 Telefunken Patent Bistabile Kippschaltung
US3193691A (en) * 1959-12-23 1965-07-06 Ibm Driver circuit
US3067378A (en) * 1960-03-17 1962-12-04 Gen Electric Transistor converter
US3079542A (en) * 1960-03-29 1963-02-26 North Electric Co Current supply apparatus
US3076925A (en) * 1960-03-29 1963-02-05 North Electric Co Current supply apparatus
US3135832A (en) * 1960-12-20 1964-06-02 Electro Mechanical Res Inc Current transformer coupling means for time sequential switching of low level signals
US3157864A (en) * 1961-01-09 1964-11-17 Gulton Ind Inc Controil for magnetic memory matrix
US3229194A (en) * 1961-09-29 1966-01-11 Bell Telephone Labor Inc Switching regulator
DE1172723B (de) * 1962-03-07 1964-06-25 Telefunken Patent Bistabile Kippschaltung mit zwei Transistoren und einem Speicherkern, insbesondere zur Verwendung in elektronischen Speicher-schaltungen fuer die Pegelregelung in der Traegerfrequenz-Nachrichtentechnik
US3278918A (en) * 1963-02-18 1966-10-11 Gen Signal Corp Binary counter
US3683208A (en) * 1970-12-23 1972-08-08 North Electric Co Power supply circuit arrangement utilizing regenerative current feedback
US3988575A (en) * 1973-12-14 1976-10-26 R. Alkan & Cie Magnetic-doughnut memorizing device for counting system

Also Published As

Publication number Publication date
FR1120525A (fr) 1956-07-09
GB766852A (en) 1957-01-23
USRE25262E (en) 1962-10-16
NL193550A (is")
BE534549A (is")
DE1023613B (de) 1958-01-30

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