US3129336A - Matrix switch - Google Patents

Description

April 14, 1964 Filed Sept. 6, 1960 INVENTOR GREGORY CONSTANTINE, JR.

ATTORNEY United States Patent 3,129,336 MATRIX SWITCH Gregory Constantine, Jr., Arlington, Mass, assignor to International Business Machines Corporation, New York, N.Y., a corporation of New York Filed Sept. 6, 1960, Ser. No. 54,262 6 Claims. (Cl. 307-88) This invention relates to matrix switches and particularly to matrix switches for controlling the read-in and read-out of data to and from a memory matrix of magnetic cores.

A memory matrix of the type described, commonly consists of a plurality of rows and columns of magnetic cores, each core being formed of material having a rectangular hysteresis loop. Each core carries several windings, usually both a row input winding and a column input winding, and at least one output winding. Sometimes separate row and column output windings are used. The row input windings in each row are connected in series in a row input circuit. The column input windings in each column are connected in series in a column input circuit. According to one common mode of operation, each input circuit is effective when energized to saturate magnetically all the cores in its row or column. The saturation by the column circuit may be in the opposite sense to that produced by the row circuit. Alternatively, the row and column input windings of a core may act magnetically in the same sense, in which case energization of both windings may be required to saturate the core in that sense. In order to store a memory bit in a core, it is saturated in one sense, and in order to read out the stored memory bit, an electrical pulse is applied to one of the windings having an amplitude and polarity effective to saturate the core in the opposite sense. If a bit has been previously stored in the core when the readout signal is applied, then the flux in the core reverses and a substantial output signal is produced in the output winding. If no memory bit was stored in the core prior to the application of the read-out signal, then there is no change in the flux in the core, and no signal is produced in the read-out winding.

The electric circuits through the various input windings of a core memory matrix are commonly driven by matrix switches of the type with which the present invention is concerned. Such a switch includes a core of rectangular hysteresis loop material and has an output winding connected in series with one of the row or column input circuits of the memory matrix. In the particular type of matrix switch with which the present invention is concerned, each core is provided with a bias Winding having a current continually flowing therein of a magnitude eifective to saturate the core in one particular sense. The core is provided with at least one and usually a plurality of input windings, which at times have currents produced in them in a sense to produce a magnetomotive force having a polarity opposite to that of the magnetomotive force of the bias winding. A current pulse is produced in the output winding of a particular core only when the sum of the magnetomotive forces due to the input winding or windings is great enough to overcome the magnetomotive force of the biasing winding and switch the core out of saturation.

Matrix switches of the prior art have had difficulty in producing output pulses of fixed magnitude. A certain variation or tolerance must be expected in the current flowing through the biasing winding, and other variations or tolerances must be permitted in the currents in the various input windings. If all the tolerance errors happen to be in the same sense on any particular output pulse, then that output pulse may be shifted from its nominal or intended value by an amount equal to the sum of the several input tolerances.

An object of the present invention is to provide a matrix switch of the type described, including an improved arrangement by which the output tolerance is minimized.

Another object is to provide a matrix of the type described having several inputs and an output, in which the output tolerance is no greater than a single input tolerance.

The foregoing and other objects of the invention are attained in the apparatus described herein. In that apparatus, the bias windings of all the cores in a matrix switch are connected in series, as is customary. Also, a portion of the bias current is used to supply the current for each signal input winding by having the bias winding in series with the current sources for these signal input windings. When a current pulse is to be sent through a signal input winding, this current pulse is supplied from a predetermined proportion of the current in the bias winding, and this current is switched into a signal path through the input winding. The respective numbers of turns on the input and bias windings are in the inverse ratio-to the predetermined proportional relationship of the currents, so that the magnetomotive forces of the two windings are equal and opposite. Consequently, any tolerance varia tion in the bias winding magnetomotive force is accompanied by a counteracting tolerance variation in the input winding magnetomotive force. The input winding currents are controlled by transistor networks so that the amplitudes of the currents in the input windings are determined by the characteristics of the current supply and of the networks and not by the amplitudes of the input sig nals which control the switching of the input winding currents. Consequently, any input signal variation does not introduce a variation in the amplitude of the matrix switch output pulse.

Other objects and advantages of the invention will become apparent from a consideration of the following specification and claims, taken together with the accompanying drawing.

In the drawing:

FIG. 1 is a wiring diagram of a portion of an array of matrix switches and a memory matrix embodying the invention;

FIG. 2 is a graphical illustration of the hysteresis loop of the material employed in a matrix switch core in accordance with the invention; and

FIG. 3 is a similar graphical illustration of the hysteresis loop of a memory matrix core of the type appearing in the circuit of FIG. 1.

There is shown in FIG. 1 a portion of a memory matrix generally indicated by the reference numeral 1. The memory matrix 1 includes a large number of memory cores, only one of which is shown at 2. The core 2 is illustrated as being annular in configuration and as being traversed by a row wire 3 which is turned around the core to form a single turn winding thereon. The core 2 is also traversed by a column wire 4, which is similarly wound around the core 2 to form a single turn winding. The currents in the row wire 3 and the column wire 4 are supplied by two matrix switches 5 and 6. In the matrix switch 5, only a single core 7 is shown. Similarly, in the matrix switch 6 only a single core 8 is shown. It will be readily understood by those skilled in the art that the matrix switches 5 and 6 will, in practice, comprise a large number of core units such as the cores 7 and 8 and their associated windings.

The cores 7 and 8 are formed of material having a hysteresis loop such as that shown at 9 in FIG. 2. While this loop may be recognized as being of the type which is regarded as generally rectangular, it is relatively narrow,

and requires therefore smaller magnetizing forces (H) to switch it between its two operating conditions.

The material of the core 2, on the other hand, has a hysteresis loop such as that illustrated at 10 in FIG. 3. This hysteresis loop, while rectangular, is more nearly square, and consequently requires larger magnetizing forces to switch it between its two conditions of saturation.

The core 7 is encircled by a bias winding 11, a pair of input windings 12 and 13, and a turn of the wire 3, which serves as an output winding. The complete circuit of the wire 3 is not shown, since it is not material to the present invention, and since many configurations of such circuits are common in the art. The core 8 is similarly provided with a bias winding 14, a pair of input windings 15 and 16, and an output winding in the form of a single turn of the column wire 4. As in the case of the wire 3, the details of the circuit of wire 4 are not shown.

The bias windings 11 and 14 in all the core units of the matrix switches and 6 are connected in series in a circuit which may be traced from a terminal 17, marked +30 volts in the drawing, through winding 11, wire 18, winding 14 and thence through a wire 19 from which lead a plurality of parallel branches extending respectively through resistors 20, 21, 22 and 23.

The parallel branch through resistor 20 may be traced through the emitter-collector impedance of a PNP transistor 24, the collector-emitter impedance of an NPN transistor 25 and thence to a terminal 26 labeled 12 volts in the drawing. It will be understood that the circuit between the terminals 17 and 26 is completed through a suitable supply of direct current, for example, a battery. The base of transistor 24 is connected to a terminal 27 marked +12 volts in the drawing, which is connected to a source of suitable biasing potential. The base of transistor 25 is connected to an input terminal 28 which may receive a square wave input signal shifting between a no-signal value more positive than 12 volts and a signal value more negative than l2 volts. The collectors of the transistors 24 and 25 are connected to a common junction 29. A diode 30 has its'anode connected to the junction 29 and its cathode connected through the input winding 13 to ground at 31.

The network just described, including the resistor 20, transistors 24 and 25, diode 30, and input winding 13, forms an input network for the winding 13. The other three input windings illustrated, namely, windings 12, 15 and 16, have similar input networks. These other input networks will not be described in detail, but the reference numerals of their principal elements will be listed.

The input network for winding 12 includes resistor 21, transistors 32 and 33, a diode 34, and winding 12. The input network for winding'16 includes resistor 22, transistors 35 and 36, a diode 50, and input winding 16. The input network for winding 15 includes resistor 23, transistors 37 and 38, a diode 39 and winding 15.

Note that the bias windings 11 and 14 are each illustrated as having four turns, and that the input windings 12, 13, 15 and 16 are illustrated as having 16 turns. Note also that the current flowing through the bias windings is divided among the four input networks. The input networks have their impedances equal so that each network continuously carries one-fourth of the bias winding current. Each network operates in response to an input signal to switch that current from a normal or non-signal path to a path through its associated input winding, so that each input winding, when energized, carries one-quarter the current of the bias winding and has four times the number of turns. The magnetomotive force produced by each input winding (which may be expressed as ampere-turns) is thus made exactly equal to the magnetomotive force of the bias winding.

Operation The source of direct current connected to terminal 17 provides a constant current source for the several bias windings 11 and 14 and the several input networks. Each of the resistors 20, 21, 22 and 23 is arranged to have a substantially higher impedance than the sum of the impedances of all the bias windings 11 and 14 connected in the series circuit. If the resistors 20, 21, 22 and 23 are so selected, then the total current in the circuit is determined primarily by the impedances of those resistors and the potential of the source connected to terminal 17. Fur thermore, if the resistors 20, 21, 22 and 23 are substantially equal in value, the current flowing through each input network is substantially equal to the current in every other input network. The transistors are all connected in the common emitter configuration, and the source of potential connected to the bases of transistors 24, 32, 35 and 37 at terminal 27 is selected so that the transistors 24, 32, 35 and 37 are permanently biased On. Substantially constant currents are thereby delivered to the junctions 29 in the respective input networks. The no-signal potentials at the terminals 28, 40, 41 and 42 are so selected that in the absence of an input signal, the transistors 25, 33, 36 and 38 are likewise biased On, and those last-mentioned transistors present a low impedance to the current appearing at junction 29. The potential at the junction 29 is therefore not much greater than 12 volts. The diodes 30, 34, 50 and 39 are then reversely biased, since their cathodes are connected to ground and their anodes to a potential of about -12 volts. The constant currents supplied through the transistors 24, 32, 35 and 37 therefore flow through the transistors 33, 36 and 38 and do not flow through the diodes 30, 34, 50 and 39, nor through the input windings 12, 13, 15 and 16.

If an input signal is now received at the input terminal 28, for example, the signal value of that potential is sufiiciently negative to cut off the transistor 25, thereby raising the potential of junction 29, which swings positive, but is caught just above ground potential when the diode 30 becomes forwardly biased, whereupon, the constant current supplied through transistor 24 passes through diode 30* and winding 13.

Referring now to FIG. 2, and remembering that the magnetomotive forces of the currents in windings 11 and 13 are equal, it may be seen that the current in bias winding 11 produces a magnetomotive force equal to that shown at 43 in FIG. 2, effective to bias the core 7 well beyond saturation in one direction. When an input signal current is received in winding 13 alone, it is suflicien-t to shift the magnetic state of the core 7 from the point 44 in FIG. 2 to point 45. Note that this involves a very small change in flux (B) in the core, and hence produces little or no signal in the output line 3. On the other hand, if both the input windings 12 and 13 receive signals simultaneously, the magnetomotive force will be equal to the sum shown at 43 and 46 in FIG. 2, and will be suflicient not only to buck down the force due to the winding 11, but further to swing the core 7 through its hysteresis loop to the opposite end thereof at 47 in FIG. 2, so that a large change of flux is produced in the core, namely, from the value indicated by the point 45 to substantially the value indicated by the point 48. This change in flux produces an output signal in the output line 3 sufficient to drive the memory core 2 and any other memory cores which may be connected in the circuit of wire 3 to one condition of saturation.

In the arrangement shown, the tolerance of variation in the current through the bias windings is exactly balanced by the counteracting variation in the current through one of the input windings; The variation in the bias winding is always opposite in direction to the variation in the input windings. Consequently, the variation or tolerance which may appear in the output signal is equal to the variation permitted in one input winding alone. This is in sharp contrast to the matrix switches of the prior art wherein the variation in the output signal had to be regarded as the sum of the possible variations in the several inputs including the bias winding as an input for such purposes. In such an arrangement, the three variations in the two input windings and the bias winding might all add in the same direction and produce a substantial departure of the output signal from its nominal or standard value.

While I have shown an arrangement in which an output signal is produced in response to coincident inputs on two windings, it will be readily apparent that the invention may be extended to other systems wherein an output signal is produced in response to coincident inputs on other numbers of input windings, for example, four input windings. It might also be noted that separate bias windings can be used for switches 5 and 6. In this case, circuit parameters are adjusted so that one-half bias current flows through each input winding, e.g., 12 and 13. Each switch 5 or 6 is then independent of the other. In any case, the sum of the variations from standard appearing in the output signal is only equal to one-half the sum of the variations which may appear in the input windings alone. The variation in the bias winding is always counteracted and may be neglected in determining the output signal variation.

While I have shown and described a preferred embodiment of my invention, other modifications thereof will readily occur to those skilled in the art, and I, therefore, intend my invention to be limited only by the appended claims.

I claim:

1. A matrix switch comprising a magnetic core having at least one input winding, an output winding and a biasing winding, circuit means for continuously energizing the biasing winding with a direct electric current, and means responsive to an input signal to switch a predetermined proportion of said current through said input Winding in a direction to produce a magnetomotive force opposing that of the biasing winding, said input and biasing windings having numbers of turns inversely proportional to the respective currents flowing therethrough, so that the magnetomotive forces of the input and biasing windings are equal and opposite, regardless of current variations.

2. A matrix switch comprising a magnetic core having a plurality of input windings, an output winding and a biasing winding, circuit means for continuously energizing the biasing winding with a direct electric current sufficient to bias the core beyond saturation in one sense, a plurality of sign-a1 input means corresponding in number to said input windings, each said input means including one input winding and means effective in response to an input signal to supply to said one input winding a predetermined proportion of the current flowing in the biasing winding, said input windings being arranged so magnetomotive forces produced by the currents flowing therein are opposed to the magnetomotive force of the biasing winding, said input and biasing windings having numbers of turns inversely proportioned to said predetermined proportion, so that variations between input signals in the biasing winding current do not cause corresponding variations in the output winding current produced in response to said input signals, said input and biasing windings being proportioned so that energization of at least two input windings is required to overcome the biasing winding and produce an output signal current in the output winding.

3. A matrix switch comprising a magnetic core having at least one input winding, an output winding and a biasing winding, circuit means for continuously energizing the biasing winding with a direct electric cur-rent, said circuit means comprising a pair of alternate paths for carrying at least a predetermined proportion of the current flowing in the biasing winding, one only of said alternate paths including said input winding in series, signal responsive switching means connecting said alternate paths to said circuit means and operable in response to an input signal to direct said proportion of current through the input winding and in the absence of an input signal to direct said proportion of current through the other alternate path, said input and biasing windings being arranged so that opposed magnetomotive forces are produced by the currents flowing therein, said input and biasing windings having numbers of turns inversely proportional to said predetermined proportion, so that variations between input signals in the input winding current do not cause corresponding variations in the output winding currents produced in response to said input signals.

4. A matrix switch comprising a magnetic core having at least one input winding, an output winding and a biasing winding, a first transistor having an emitter, a base and a collector and connected in the common emit ter configuration, first circuit means connected to the emitter and including in series, a source of direct electrical energy, said biasing winding and a resistor, further circuit means connected to the base and the collector and cooperating with the first circuit means continuously to bias the collector reversely with respect to the base and the emitter forwardly with respect to the base so that the transistor carries a substantially constant emitter-collector current; said further circuit means comprising a second transistor having an emitter, a base, and a collector and connected in the common emitter configuration, said second transistor being of opposite conductivity type to said first transistor, means connecting the collectors of the two transistors to a common junction, means connecting the emitter of the second transistor to a source of fixed potential, and signal input means connected to the base of the second transistor and efiective in the absence of an input signal to maintain the second transistor in a high conductivity state and in the presence of an input signal to shift the second transistor to a low conductivity state, means connecting said input winding and a diode in series between said common junction and a point of fixed potential, said diode and input winding being efi'ective to carry the constant current of the first transistor only when the second transistor is in its low conductivity state, the polarity of the diode being arranged with respect to the potentials of said point of fixed potential and said source of fixed potential so as to block the flow of current through the input winding at all other times.

5. A matrix switch comprising an array of magnetic cores, each having at least one input winding, an output winding, and a biasing winding, a source of direct electrical energy, means connecting the source and all the biasing windings in series between two terminals; a plurality of input networks, equal in number to said input windings, each network comprising a first transistor having an emitter, a base and a collector and connected in the common emitter configuration, a resistor connected between the emitter and one of the two terminals, a second source of direct electrical energy connected between the base and the other of the two terminals, a second transistor having an emitter, a base and a collector and connected in the common emitter configuration, said second transistor being of opposite conductivity type to the first transistor, means directly connecting the collectors of the two transistors, a third source of direct electrical energy connected between the emitter of the second transistor and the other of the two terminals, a diode and one of the input windings connected in series between the other of the two terminals and the means directly connecting the collectors, and signal input means connected between the base of the second transistor and the other of the two terminals, said signal input means being shiftable between a no-si'gnal condition in which the second transistor is in a relatively high conduction state, and a signal condition in which the second transistor is in a relatively low conduction state, said first, second and third sources cooperating to maintain said first transistor in a state of substantially constant conductivity, so that a constant current flows in said biasing winding, said second transistor being effective when it switches to its state of low conductivity to switch the current flowing through the determined by the ratio of one over the number of said 10 2,902,609

input networks; and in which the respective numbers of turns in the input and biasing windings are inversely pro portional to the currents flowing therethrough.

References Cited in the file of this patent UNITED STATES PATENTS 2,734,184 Rajchman Feb. 7, 1956 2,776,419 Rajchman -1 Jan. 1, 1957 2,801,345 Eckert et a1 July 30, 1957 Ostrofif et a1. Sept. 1, 1959

Claims (1)

1. 2. A MATRIX SWITCH COMPRISING A MAGNETIC CORE HAVING A PLURALITY OF INPUT WINDINGS, AN OUTPUT WINDING AND A BIASING WINDING, CIRCUIT MEANS FOR CONTINUOUSLY ENERGIZING THE BIASING WINDING WITH A DIRECT ELECTRIC CURRENT SUFFICIENT TO BIAS THE CORE BEYOND SATURATION IN ONE SENSE, A PLURALITY OF SIGNAL INPUT MEANS CORRESPONDING IN NUMBER TO SAID INPUT WINDINGS, EACH SAID INPUT MEANS INCLUDING ONE INPUT WINDING AND MEANS EFFECTIVE IN RESPONSE TO AN INPUT SIGNAL TO SUPPLY TO SAID ONE INPUT WINDING A PREDETERMINED PROPORTION OF THE CURRENT FLOWING IN THE BIASING WINDING, SAID INPUT WINDINGS BEING ARRANGED SO MAGNETOMOTIVE FORCES PRODUCED BY THE CURRENTS FLOWING THEREIN ARE OPPOSED TO THE MAGNETOMOTIVE FORCE OF THE BIASING WINDING, SAID INPUT AND BIASING WINDINGS HAVING NUMBERS OF TURNS INVERSELY PROPORTIONED TO SAID PREDETERMINED PROPORTION, SO THAT VARIATIONS BETWEEN INPUT SIGNALS IN THE BIASING WINDING CURRENT DO NOT CAUSE CORRESPONDING VARIATIONS IN THE OUTPUT WINDING CURRENT PRODUCED IN RESPONSE TO SAID INPUT SIGNALS, SAID INPUT AND BIASING WINDINGS BEING PROPORTIONED SO THAT ENERGIZATION OF AT LEAST TWO INPUT WINDINGS IS REQUIRED TO OVERCOME THE BIASING WINDING AND PRODUCE AN OUTPUT SIGNAL CURRENT IN THE OUTPUT WINDING.

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