US2556200A - Electrical translation system - Google Patents

Electrical translation system Download PDF

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Publication number
US2556200A
US2556200A US11261A US1126148A US2556200A US 2556200 A US2556200 A US 2556200A US 11261 A US11261 A US 11261A US 1126148 A US1126148 A US 1126148A US 2556200 A US2556200 A US 2556200A
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Prior art keywords
output
voltage
combining
circuits
circuit
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US11261A
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English (en)
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Lesti Arnold
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International Standard Electric Corp
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International Standard Electric Corp
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Priority to BE487541D priority Critical patent/BE487541A/xx
Priority to NL84059D priority patent/NL84059C/xx
Application filed by International Standard Electric Corp filed Critical International Standard Electric Corp
Priority to US11261A priority patent/US2556200A/en
Priority to GB33225/48A priority patent/GB659576A/en
Priority to ES0187210A priority patent/ES187210A1/es
Priority to CH288032D priority patent/CH288032A/fr
Priority to FR981785D priority patent/FR981785A/fr
Priority to DEF4328A priority patent/DE977039C/de
Application granted granted Critical
Publication of US2556200A publication Critical patent/US2556200A/en
Priority to GB7228/55A priority patent/GB765825A/en
Priority to FR69065D priority patent/FR69065E/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/26—Arbitrary function generators
    • G06G7/28—Arbitrary function generators for synthesising functions by piecewise approximation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
    • H03M1/367—Non-linear conversion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B14/00—Transmission systems not characterised by the medium used for transmission
    • H04B14/02—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation
    • H04B14/04—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation using pulse code modulation
    • H04B14/046—Systems or methods for reducing noise or bandwidth
    • H04B14/048—Non linear compression or expansion

Definitions

  • Pulse Code Modulation an expensive method based upon the use of silicon crystals carefully maintained in a temperature' controlled oven has' been utilized.
  • the present invention allows the logarithmic 'response' characteristic useful in Pulse Code Modulation to be obtained cheaply and easily; and in fact to be obtained as an incidental result during thepro-cess of coding.
  • vIt is a speciiic object ofthe invention to provide an improved method of translating pulse amplitude modulation to pulse code' modulation, by means of a simple circuit consisting ⁇ entirely ofv passive elements.
  • an Yelectrical circuit is provided which may be adjusted in accordance with the method disclosed hereinafter to produce an arbitrarily predetermined transfer characteristic.
  • amplitude modulated pulses are applied to a series of biased rectiers, and the output of each of said rectiers is individually adjusted and fed to a combining circuit arranged to produce an arbitrarily predetermined output referred to said pulses.
  • amplitude modulated pulses are applied to a series of biased rectiiriers, and the outputs of said rectiers are combined inra number of different combining circuits which function to produce in their output a representation of binary code of the input to said biasedk rectiers.
  • two sets of biased diodes are fed in pushpull and the outputs of the two sets are combined in such a way as to produce a desired amplitude transfer characteristic.
  • two sets of( biased diodes are fed in pushpull and the output of the two sets are combined in a number of different circuits in different ways, so as to produce a set of desired output transfer characteristics.
  • Fig. 1 shows a basic circuit of my invention
  • Fig. 2 shows a ⁇ family ofl characteristic response curves obtained from the circuit of Fig. l;
  • Fig. 3 shows a set of input-output characteristics obtained in accordance with ther invention
  • Fig. 4 shows a Vcircuit according to the invention for producing a coded representation of amplitude modulated pulses
  • Fig. 5 shows a modification of the circuit of Fig. 4.
  • Fig. 6 shows another group of input-output characteristics
  • Fig. 7 shows a modication of the invention
  • Fig. 8 shows a push-pull version of the invention
  • Fig. 9 shows another embodiment of the invention.
  • Fig. 10 shows a set of Vinput-output characte'ristics accordingto Fig. 9.
  • I show a signal ⁇ source I which produces a signal chc'uacterizeclA by a varying amplitude.
  • the output of signal source I is applied by means of blocking condenser 2 to a groupl of biassed rectifl'ers v3, kwhich may be,
  • each rectier 3 is connected through a load resistor 4 to a source of biassing potential, obtained in cooperation with a positive source of potential from the voltage divider 5.
  • the biassing voltage for each of the rectiiiers is held constant by means of condenser 6. As is well known to those skilled in the art, a given one of the rectiers will not conduct until the amplitude of the voltage from signal source I becomes greater than the bias potential applied to the corresponding rectifier from voltage divider 5.
  • FIG. 2 I show a family of characteristic curves representative of the transfer characteristics of a group of biassed diodes such as shown in Fig. 1.
  • the rst rectiiier is shown biassed to a potential V1 of zero volts, the second rectifier to a potential V2, the third to potential V3, and so on.
  • the rectiers are shown biassed by uniformly differing amounts, but it is clear that they could be biassed by steadily increasing amounts or in any other irregular fashion.
  • a solution of the set of simultaneous equations will in general give a set of xs some of which have positive and others negative values.
  • the voltage dividers 9 do not change the positive output from load resistor 4 to negative values. This function is accomplished in the combining circuit IS, Where the outputs whose s are negative are subtracted from those whose s are positive.
  • K1, K2 and so on up to KN are the specified Values that the output of combining circuit I0 in Fig. 1 must have for the input voltages V2, Vs and so on up to VN of Fig. 2. It is apparent that the output of the circuit of Fig. 1 can never exceed the input, and it will become clear that the absolute value of these Ks should be kept small with respect to the amplitude of the input signal. An arbitrary ratio of Ks, however, may be obtained at the output of Fig. 1. A logarithmic or any other desired transfer characteristic may accordingly be obtained by use of the circuit of Fig. 1.
  • a combination of M circuits based on Fig. 1 may be used to obtain an M-element binary code in particular.
  • FIG. 3 I show a group of three input-output characteristics which, when obtained in time sequence from a single input, constitute a translation of the input signal into a threeelement seven-level binary code output, as commonly used in coded modulation systems.
  • the amplitude of the output of any one of the circuits to be equal to either zero or a as shown in Fig. 3, Where a is kept small.
  • Fig. 4 The result of applying these solutions to a circuit based on that of Fig. 1 is shown in Fig. 4. Corresponding parts of Figs. 4 and 1 are given like reference numerals.
  • the voltages taken from blocking condensers 'I are applied, as above described, to suitable impedance matching resistors 8, and to voltage dividers comprising resistances II through I9 as shown.
  • the outputs of voltage dividers II-I8, I3-I8, I5-I8, and I'I-I8 are added on resistor I8, and the outputs of voltage dividers I2-I9, I4-I9 and I6-I9 are added on resistor I9.
  • the voltage on resistor I8 is applied to one terminal of the primary of transformer 20, and the voltage on resistor I9 is applied to the opposite terminal; while the center top of the primary is connected to the common junction of resistors I8 and I9, and to grou-nd.
  • the transformer 29 constitutes a subtraction circuit of the voltage on resistor I9 from that on resistor I8, and the output is taken on the secondary of transformer 2G.
  • the ratio of resistor I8 to the sum of resistor II and resistor I8 is made equal to a
  • the ratio of resistor I9 to the sum of resistor I2 land resistor I9 is made-equal to 2a, that of resistor I8 to the sum of resistor I3 plus resistor I8 equal to 2a, that of resistor I9 tothe-sum of resistor I4 plus resistor I9 equal to 2a, that of resistor I8 to the sum of resistor I5 plus resistor I8 equal to 2a, that of resistor I9 to the sum of resistor IB plus resistor I9 equal to2a, and that of resistor I8 to the sum of resistor I?
  • resistor I8 equals2a.
  • Resistors II through Il are all made relatively large compared to resistors I8 and I9.
  • Resistors I8and I9 are considered to include the resistance looking towards the transformer.
  • the values of resistors 8 are all adjusted independently to present the same lead impedance to each of the rectifiers 3.
  • the transformer 20 shown in the-combining circuit A is selected to be capable of passing a band of frequencies which includes the frequencies present in they signal produced by signal source I.
  • the output of the combining circuit A then is that shown in Fig. 3.
  • the output of the rectifiers is applied to combining cir-cuits B and C of Fig. 4 through resistance voltage divider adjusted on the basis of the values of a: obtained for the circuits B and C as listed above.
  • the output of circuits B and C will then be as shown in Fig. 3.
  • the input signal consists of pulses modulated in amplitude;
  • the outputs as given by Fig. 3 will then 'appear simultaneously for each input pulse at the output vof circuits A, B, and C.
  • delay devices 22 and 23 may be inserted at the output of combining circuits B and C. r'lhe'outputs are then passed through 'coupling pads 2l and when combined directly consist of pulses code modulated inaccordance with the amplitude of the input signal pulse.
  • Fig. 5 shows an alternative arrangement of the portion to the right of line 5 5 of Fig. 4 for translating amplitude modulated pulses to code modulated pulses in accordance with the invention.
  • Corresponding elements of v Figures 5 and 4 are given like reference numerals.
  • the outputs are combined through condensers 26 and 21 and applied to the control grid of tube 28.
  • the plate circuit of tube 2B has condenser 29 which is charged negatively when a positive code pulseV appears on the input of tube 258.
  • Condenser 29 stores the charge for a short time controlled by the time constant of the resister-condenser combination 29-39, and the resulting voltage is yapplied to the control grid of tube 3 I, 'whose plate is tied to the plate of tube 32. If either or both tubes 3I and 32 have their grids relatively positive, the voltage at their plates is low, but if both their control grids have a negative voltage on them the voltage at their plates, which are connected to the output, lwill rise.
  • a positive voltage into tube 28 will charge condenser 2'9 negatively to cut oif tube 3 I. Under this 'condition, and only then, if a negative keying pulse is applied at 33 to the control grid of tube 32, which is normally conductive, a positive pulse will appear at the output whose duration is equal to that of the keying pulse. The resistor 30 will discharge condenser 28 in time for the next input pulse.
  • Subtraction circuits B and C function in a similar manner but have their voltage divider resistors at the input adjusted in accordance with the solution of the equations for the corresponding circuit, as given above.
  • a set of keying leads such as 34, 35 and 36 is provided, on which gating pulses occur in sequence.
  • These gating pulses may be easily obtained by conventional means, and are synchronized in groups with the amplitude Amodulated into pulses.
  • tube 3I of circuit A is gated by the pulse on lead 34.
  • a short time thereafter a Acorresponding tube in subtraction circuit B is gated by a later pulse v0n lead 35.
  • circuit C On lead 36.
  • the common output of these circuits will then consist of a group oi coded pulses corresponding to the input amplitude. After the termination of the'last gating action, a new signal pulse is applied to the input to start a new cycle of operation.
  • Fig. 6 shows a new set of response characteristics for subtraction circuits A, B, and C. It is to be noted that the above-mentioned skipjumping effect no longer occurs because the width of each of the responses has been narrowed so that there is no longer any overlap. At the same time, however, a zero reading is obtained at the output lof the circuit, at the times Where skip-jumping formerly occurred.
  • the response characteristics shown may be conveniently 'obtained by utilizing a larger number of rectiers and adjusting the output of the various subtraction circuits. At the places where skipjumping would normally occur, zero output is obtained, and advantage is taken of this fact in accordance with Fig. 1.
  • Fig. 7 Shows in block diagram form a circuit such as that of Fig.
  • rlhe outputs of the combining circuits A, B, and C which are produced simultaneously are fed to a feedback control circuit 31.
  • the function of feedback control 31 is to take the combined output of circuits A, B, and C, and when their sum is zero add a small negative voltage to the input to the biassed rectifier circuit 38. The result will be that the input signal amplitude is reduced or raised by a small amount to a level which falls within the next lower amplitude range. If, however, an output occurs on any of the combining circuits A, B, or C, feedback control circuit 31 is adjusted to apply no additional voltage to the signal input.
  • the magnitude of the resultant feedback control output voltage is such as to reduce or raise the input signal by a small amount so that an output will occur on one or more of the circuits A, B, or C.
  • the magnitude of the output feedback control voltage is kept small, say one half the magnitude of the smallest difference in levels Vi-Vi-i.
  • the exact circuit details of feedback control circuit 36 will Vary with the particular application, but suitable circuits will be readily apparent to those skilled in the art.
  • FIG. 8 I show a modification of my invention which reduces the combining circuit to a simple addition circuit, and which avoids the need for subtraction devices. This result is accomplished by utilizing a push-pull input as shown so that both the positive and negative voltages from any rectifier which is actuated become available across the output load resistors of the various rectiers for utilization in the combining circuits.
  • the circuit arrangement shown in Fig. 8 there are two positive Xs taken from the upper set of biassed rectifiers and two negative Xs taken from the lower set of biassed rectiers. The resultants are simply added in circuit 39, ⁇ and no subtraction circuit is required.
  • each of the biassed rectifiers 3 taken across the load resistor 4 is clipped by an additional biassed rectifier 40 before being passed on through blocking condenser 1 to the remainder of the circuit.
  • the rectifier outputs in this case are action of 'anyone of the rectiers '4U is to prevent the voltage on its positive terminal from rising very much above the voltage on its negative terminal. After passing through the blocking condenser 1, the voltage across resistor 8 will, therefore, not rise by an amount very much greater than the difference between two biassing levels.
  • a set of characteristics response codes for a group of rectifers biassed in accordance with Fig. 9 is shown in Fig. 10.
  • Fig. 10 thus corresponds to Fig. 9 in the same way that Fig. 2 corresponds to Fig. l. It is apparent that a set of simultaneous equations relating the output of Fig. 9 to the input can be written based on Fig. 10 in a manner similar to that outlined above.
  • An electrical translator comprising a signal source plurality of circuits each adjusted to pass only that portion of a voltage above a given corresponding level, means for applying said signal to said circuits, individual voltage dividing means adapted to produce output voltages proportional to the input voltages, each dividing means being associated with a separate one of said circuits and adjusted in accordance with the desired response characteristic, means for applying the said passed portion of a voltage above a given corresponding level of each of said circuits to said associated voltage dividing means, and means for combining the outputs of said voltage dividing means so as 'to produce said response characteristic.
  • An electrical translator comprising a signal source, a plurality of load resistors, a plurality of rectiiiers each biassed across a corresponding one of said load resistors to a corresponding voltage, means for applying said signal to said rectiflers, and means for combining predetermined proportions of the voltages developed across said load resistors in response to said signal in such a Way as to obtain a required output versus input response characteristic.
  • An electrical translator comprising a signal source, a plurality of load resistors, a plurality of rectiers each biassed across a corresponding one of said load resistors to one of an equal plurality of different voltages, means for applying said signal to said rectiers, a plurality of voltage dividers, means for coupling the voltage developed across each of said load resistors in response to said signal to a corresponding one of said voltage dividers, means for adding the output of the predetermined ones of said voltage dividers to obtain a first sum, means for adding the output of predetermined others of said voltage dividers to obtain a second sum, combining means for subtracting said second sum from said first sum to obtain a resultant, and an output circuit for said from the load resistors 4I. It is clear that the 75 resultant.
  • An electrical translator comprising a signal source, a plurality of load resistors, a plurality of rectiiiers each biassed across a corresponding one of said load resistors to one of an equal plurality of different voltages, means for applying said signal to said rectifiers,v a plurality of voltage dividing resistors, part of which are connected to a first common resistor and part to a second common resistor, a plurality of blocking condensers for coupling the voltage developed across each of said load resistors in response to said signal to a corresponding one of said voltage dividing resistors, a plurality of impedance matching resistors, each connected to the common junction of a corresponding blocking condenser and voltage divider resistor, combining means for subtracting the voltage ceveloped across said second common resistor from the voltage developed across said rst common resistor to obtain a resultant, and an output circuit for said resultant.
  • said combining means comprises a transformer having a primary and a secondary Winding, one terminal of said primary being connected to said rst common resistor, the other terminal of said primary being connected to said second common resistor, the remaining terminals of the two said common resistors being connected together, and said secondary comprising said output circuit.
  • said combining means comprises a pair of electron dischargev devices, one of which has its output taken from its anode circuit and the other of which has its output taken from its cathode circuit, one of which has its output taken from said rst. common resistor, and the other of which has its input taken from said second common resistor, and meansr for combining said outputs.
  • An electrical translator comprising a rst plurality of rectiiiers each biassed across a corresponding load .resistor to a corresponding positive voltage, a second plurality ⁇ of rectiers each negatively biassed acrossV a corresponding load resistor to a corresponding negative voltage, a source of a positive signal and a negative signal of equal magnitude, means for applying said positive signal to said rst plurality of rectiiers, means for applying said negative signal to said second plurality of rectiflers, means for individually dividing the amplitude of the voltage produced across each of said load resistors in response to said input signals, and means for cornbining said divided voltages in such a way as to obtain a specified output voltage versus input voltage response characteristic.
  • a method Aof translating an electrical signal using a plurality of load resistors and a plurality of rectifiers each biassed across a corresponding one of said load resistors to a corresponding voltage, comprising individually dividing the magnitude of the output voltage developed across each of said load resistors in response to said signal by a predetermined factor which is different for at least two of said resistors to produce output voltages of different magnitude, and combining said divided outputs to obtain a desired output versus input response characteristic.
  • a method according to claim 9 further comprising the method of evaluating said predetermined factor, comprising the solution of a lset of linear simultaneous equations based on the y response characteristics of said biassed rectifiers and on said desired output versus input characteristic.
  • An electrical translator according to claim 3y wherein said means for coupling the voltage developed across each of said load resistors in response to said signal' to a corresponding one of said voltage dividers, comprises a clipper for individually clipping each of said developed voltagesl at a predetermined level, and means for applying the output of said clipper to said voltage divider.
  • An electrical translator for translatingasingie voltage into a plurality of voltages comprising a plurality of biassedrectiers, means for applying said single voltage to said rectiers, and a plurality of combining circuits, of which at least one has a combining characteristic different from another, for each separately combining the outputs of all of said rectiiiersv in such a way as to obtain said plurality of voltages.
  • An electrical translator comprising a signal source, a plurality of load resistors, a plurality of rectiers each biassed across a corresponding one of said loadr resistors to a corresponding voltage, means for applyingY said signal to said rectiers, a plurality of voltage-dividing circuits for each separately and individually adjusting the proportion of the amplitude of the voltage taken from each load resistor, and means for combining the adjusted voltages in each of said circuits in such a Way as to obtain a plurality of desired output versus input response characteristics.
  • An electrical translator comprising a signal source, a plurality of load resistors, a plurality of rectiiiers each biassed across a corresponding one of' saidv resistors to one of an equal plurality of different voltages, means for applying said signal to said rectiiiers, a plurality of combining circuits, each of said combining circuits comprising ⁇ a plurality of voltage dividers, means for coupling the voltage developed across said load resistors in response to said signal to a corresponding one of said voltage dividers, means for combining the outputsof predetermined ones of said voltage dividers to obtain a rst sum, means for combining the outputs of predetermined others oi saidr voltage dividers to obtain a second sum, means for subtracting said second sum from said rst sum to obtain a resultant for each of said combining circuits, an output circuit for each of said resultants associated with each of said combining circuits, and means for combining the output in each of said output circuits.
  • An electrical translator for translating amplitude modulated pulses to binary code modulated pulses comprising a plurality of load resistors, a plurality of rectiers each biassed across a corresponding one of said load resistors to one of an equal plurality of different voltages, means for applying said amplitude modulated pulses to said biassed rectiers, a plurality of combining circuits, each separately responsive to selected ones of the voltages developed across each of said load resistors in response to the input amplitude modulated pulses, each of said plurality of combining circuits comprising means for individually adjusting the voltage amplitude of said plurality of selected voltages in such a way as to produce in the output of said combining circuits a pulse when lthe binary code representation of the input amplitude modulated pulse has a corresponding element present and to produce zero output when the primary code representation of the input amplitude modulated pulse has the corresponding element absent, and utilization means for the resulting binary code representing the input amplitude modulated pulse.
  • An electrical translator for translating amplitude modulated pulses to binary code modulated pulses comprising a source of amplitude modulated pulses, a plurality of load resistors, a plurality of rectiiiers each biassed across a corresponding one of said load resistors to one of an equal plurality of different voltages, means for applying said amplitude modulated pulsesrto said biassed rectiers, a plurality of combining circuits, one corresponding to each possible code element in the binary code representation of an input modulated pulse, means for applying the individual voltages developed across said load resistors in response to said amplitude modulated pulses to each of said combining circuits, each of said combining circuits comprising voltage dividing and polarity selecting means arranged to combine said individual voltages so as to produce in the output of the corresponding combining circuit a pulse when the binary code representation of the corresponding input modulated pulse has an element present corresponding to said combining circuit and to produce no out put from the corresponding combining circuit when said binary code representation has no element present
  • An electrical translator according to claim 17, further comprising a plurality of delay devices, each connected to the output of a corresponding one of said combining circuits, and means for combining the output of said delay devices to obtain in response to each of said input amplitude modulated pulses a code group representative of said input amplitude modulated pulse with the elements of said code group arrangedin time sequence.
  • An electrical translator comprising a source of a sequence of keying pulses, on sequence being associated with each input amplitude modulated pulse, means for applying a corresponding pulse of each sequence to a corresponding combining circuit so as to key said combining circuits in time sequence, and means for combining the output of said combining circuits so as to obtain in response to each ofsaid input amplitude modulated pulses a binary code group representation with the ele- ⁇ ments of said code group arranged in time sequence.
  • An electrical translator comprising a signal source, a plurality of translating circuits each having linear response curves mathematically independent of the curves of the other circuits, means for applying the signal to the input of each of said translating circuits, means for dividing the magnitude of each of the outputs of said translating circuits according to a predetermined factor which is different for at least tWo of said outputs, and means for combining the divided voltages.
  • An electrical translator comprising a signal source, a plurality of translating circuits each having linearly independent response curves, means for applying the signal to the input of each of said translating circuits, a plurality of dividing means each dividing means dividing the magnitude of each of the outputs of said translating circuits according to a predetermined factor, this factor with respect to at least one of said outputs being different from each other for at least two of said dividing means, and means for combining the divided voltages.
  • An electrical translator comprising a signal source, a plurality of translating circuits providing a set of linearly independent response curves, means for applying the signal to the input of each of said translating circuits, and a plurality of combining circuits each including means for dividing the magnitude of each of the outputs of said translating circuits according to a predetermined factor, and means for combining the divided voltages, at least one of said combining circuits having a different response characteristic from one of the other combining circuits.

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  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Signal Processing (AREA)
  • Logic Circuits (AREA)
  • Rectifiers (AREA)
  • Ultra Sonic Daignosis Equipment (AREA)
  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
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US11261A 1948-02-26 1948-02-26 Electrical translation system Expired - Lifetime US2556200A (en)

Priority Applications (10)

Application Number Priority Date Filing Date Title
BE487541D BE487541A (et) 1948-02-26
NL84059D NL84059C (et) 1948-02-26
US11261A US2556200A (en) 1948-02-26 1948-02-26 Electrical translation system
GB33225/48A GB659576A (en) 1948-02-26 1948-12-24 Electric transmission circuits having non-linear amplitude transfer characteristics
ES0187210A ES187210A1 (es) 1948-02-26 1949-02-24 Sistema traductor eléctrico
CH288032D CH288032A (fr) 1948-02-26 1949-02-25 Dispositif électrique à caractéristique entrée-sortie non linéaire.
FR981785D FR981785A (fr) 1948-02-26 1949-02-25 Systèmes translateurs de signaux électriques
DEF4328A DE977039C (de) 1948-02-26 1950-10-01 Schaltungsanordnung fuer Signalumsetzer bei Pulscodemodulation
GB7228/55A GB765825A (en) 1948-02-26 1955-03-11 Electrical translation system
FR69065D FR69065E (fr) 1948-02-26 1955-03-28 Systèmes translateurs de signaux électriques

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US11261A US2556200A (en) 1948-02-26 1948-02-26 Electrical translation system

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US2556200A true US2556200A (en) 1951-06-12

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BE (1) BE487541A (et)
CH (1) CH288032A (et)
DE (1) DE977039C (et)
ES (1) ES187210A1 (et)
FR (1) FR981785A (et)
GB (1) GB659576A (et)
NL (1) NL84059C (et)

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US2636133A (en) * 1950-12-01 1953-04-21 Bell Telephone Labor Inc Diode gate
US2647238A (en) * 1948-11-26 1953-07-28 Hartford Nat Bank & Trust Co Telephonic pulse-code-modulation system
US2666861A (en) * 1952-01-09 1954-01-19 Reed Res Inc Transducer
US2673936A (en) * 1952-04-28 1954-03-30 Bell Telephone Labor Inc Diode gate
US2715724A (en) * 1951-10-23 1955-08-16 Nederlanden Staat Converter for linear and binary codes
US2738504A (en) * 1951-08-18 1956-03-13 Gen Precision Lab Inc Digital number converter
US2752489A (en) * 1950-03-03 1956-06-26 Int Standard Electric Corp Potential comparing device
US2758206A (en) * 1955-08-03 1956-08-07 Hughes Aircraft Co Transistor pulse generator
US2758787A (en) * 1951-11-27 1956-08-14 Bell Telephone Labor Inc Serial binary digital multiplier
US2764678A (en) * 1951-06-07 1956-09-25 Airborne Instr Lab Inc Pulse stretcher
US2765115A (en) * 1951-10-30 1956-10-02 Raytheon Mfg Co Arithmetic adders
DE958124C (de) * 1952-08-28 1957-02-14 Int Standard Electric Corp Anordnung zur Codierung von Signalimpulsen
US2787418A (en) * 1952-06-14 1957-04-02 Hughes Aircraft Co Analogue-to-digital converter system
US2831107A (en) * 1951-07-26 1958-04-15 Electronique & Automatisme Sa Electric simulators of arbitrary functions
US2845219A (en) * 1950-06-07 1958-07-29 Electronique & Automatisme Sa Representation translation of electric magnitude
US2870406A (en) * 1957-06-03 1959-01-20 Caldwell P Smith Device for voltage measurement
US2878434A (en) * 1954-05-10 1959-03-17 North American Aviation Inc Error sensing servo component
US2902217A (en) * 1953-02-11 1959-09-01 Nat Res Dev Control gating means for a digital computer
US2950469A (en) * 1954-04-14 1960-08-23 Honeywell Regulator Co Analogue to digital conversion apparatus
US2954502A (en) * 1958-11-10 1960-09-27 Bell Telephone Labor Inc Deflection circuit for cathode ray tubes
US2986704A (en) * 1956-06-29 1961-05-30 Gen Electric Function generator
US2987629A (en) * 1957-07-10 1961-06-06 Burroughs Corp Voltage comparator
US3034038A (en) * 1959-06-23 1962-05-08 Honeywell Regulator Co Control apparatus
US3062445A (en) * 1955-12-10 1962-11-06 Kienzle Apparate Gmbh System for electronic transformation of analogue values into digital values
US3078713A (en) * 1959-01-15 1963-02-26 Blaw Knox Co Means for generating electric functions
US3114057A (en) * 1961-10-04 1963-12-10 Frank E Caruso Cascaded differential amplifiers with biased diode switches for providing single output dependent upon input amplitude
US3131298A (en) * 1960-05-27 1964-04-28 Melville C Creusere Diode multiplier network
US3135862A (en) * 1953-09-29 1964-06-02 Bell Telephone Labor Inc Digital target information transmission system with parallax correction
US3207889A (en) * 1960-09-21 1965-09-21 Naz Metanodotti S P A Soc Analogue pipe network analyzer
US3249898A (en) * 1958-01-10 1966-05-03 Caldwell P Smith Adjustable modulator apparatus
DE1219258B (de) * 1960-10-26 1966-06-16 Bendix Corp Schaltungsanorndung zur Erzeugung eines Ausgangssignals als vorgegebene lineare Funktion eines veraenderlichen elektrischen Eingangssignals
US3280315A (en) * 1957-09-06 1966-10-18 Bell Punch Co Ltd Key controlled decimal electronic calculating machine
US3280319A (en) * 1963-02-13 1966-10-18 Nathan Amos Electronic multiplier
US3412339A (en) * 1965-07-07 1968-11-19 Conrad H. Koning Variable-gain amplifier
FR2414268A1 (fr) * 1978-01-05 1979-08-03 Analog Devices Inc Convertisseur analogique-numerique parallele
EP0126868A2 (en) * 1983-03-30 1984-12-05 Kabushiki Kaisha Toshiba Quantizer-subtractor circuit
US4837505A (en) * 1985-11-20 1989-06-06 Ricoh Company, Ltd. Test mode activation circuit

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GB2219113A (en) * 1988-05-20 1989-11-29 Teledyne Ind Curve approximating circuits

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US2453461A (en) * 1946-06-19 1948-11-09 Bell Telephone Labor Inc Code modulation communication system

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US2416329A (en) * 1942-08-24 1947-02-25 Standard Telephones Cables Ltd Push-pull modulation system
US2420374A (en) * 1944-07-01 1947-05-13 Rca Corp Pulse multiplex transmission system
US2453461A (en) * 1946-06-19 1948-11-09 Bell Telephone Labor Inc Code modulation communication system

Cited By (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2647238A (en) * 1948-11-26 1953-07-28 Hartford Nat Bank & Trust Co Telephonic pulse-code-modulation system
US2616960A (en) * 1949-04-04 1952-11-04 Hartford Nat Bank & Trust Co Circuit arrangement for transmitting an alternating voltage through a transmission circuit under the control of a unidirectional control voltage
US2632880A (en) * 1950-03-03 1953-03-24 Flowers Thomas Harold Electric pulse modulator
US2752489A (en) * 1950-03-03 1956-06-26 Int Standard Electric Corp Potential comparing device
US2845219A (en) * 1950-06-07 1958-07-29 Electronique & Automatisme Sa Representation translation of electric magnitude
US2636133A (en) * 1950-12-01 1953-04-21 Bell Telephone Labor Inc Diode gate
US2764678A (en) * 1951-06-07 1956-09-25 Airborne Instr Lab Inc Pulse stretcher
US2831107A (en) * 1951-07-26 1958-04-15 Electronique & Automatisme Sa Electric simulators of arbitrary functions
US2738504A (en) * 1951-08-18 1956-03-13 Gen Precision Lab Inc Digital number converter
US2715724A (en) * 1951-10-23 1955-08-16 Nederlanden Staat Converter for linear and binary codes
US2765115A (en) * 1951-10-30 1956-10-02 Raytheon Mfg Co Arithmetic adders
US2758787A (en) * 1951-11-27 1956-08-14 Bell Telephone Labor Inc Serial binary digital multiplier
US2666861A (en) * 1952-01-09 1954-01-19 Reed Res Inc Transducer
US2673936A (en) * 1952-04-28 1954-03-30 Bell Telephone Labor Inc Diode gate
US2787418A (en) * 1952-06-14 1957-04-02 Hughes Aircraft Co Analogue-to-digital converter system
US2894214A (en) * 1952-08-28 1959-07-07 Int Standard Electric Corp Coding circuit
DE958124C (de) * 1952-08-28 1957-02-14 Int Standard Electric Corp Anordnung zur Codierung von Signalimpulsen
US2902217A (en) * 1953-02-11 1959-09-01 Nat Res Dev Control gating means for a digital computer
US3135862A (en) * 1953-09-29 1964-06-02 Bell Telephone Labor Inc Digital target information transmission system with parallax correction
US2950469A (en) * 1954-04-14 1960-08-23 Honeywell Regulator Co Analogue to digital conversion apparatus
US2878434A (en) * 1954-05-10 1959-03-17 North American Aviation Inc Error sensing servo component
US2758206A (en) * 1955-08-03 1956-08-07 Hughes Aircraft Co Transistor pulse generator
US3062445A (en) * 1955-12-10 1962-11-06 Kienzle Apparate Gmbh System for electronic transformation of analogue values into digital values
US2986704A (en) * 1956-06-29 1961-05-30 Gen Electric Function generator
US2870406A (en) * 1957-06-03 1959-01-20 Caldwell P Smith Device for voltage measurement
US2987629A (en) * 1957-07-10 1961-06-06 Burroughs Corp Voltage comparator
US3280315A (en) * 1957-09-06 1966-10-18 Bell Punch Co Ltd Key controlled decimal electronic calculating machine
US3249898A (en) * 1958-01-10 1966-05-03 Caldwell P Smith Adjustable modulator apparatus
US2954502A (en) * 1958-11-10 1960-09-27 Bell Telephone Labor Inc Deflection circuit for cathode ray tubes
US3078713A (en) * 1959-01-15 1963-02-26 Blaw Knox Co Means for generating electric functions
US3034038A (en) * 1959-06-23 1962-05-08 Honeywell Regulator Co Control apparatus
US3131298A (en) * 1960-05-27 1964-04-28 Melville C Creusere Diode multiplier network
US3207889A (en) * 1960-09-21 1965-09-21 Naz Metanodotti S P A Soc Analogue pipe network analyzer
DE1219258B (de) * 1960-10-26 1966-06-16 Bendix Corp Schaltungsanorndung zur Erzeugung eines Ausgangssignals als vorgegebene lineare Funktion eines veraenderlichen elektrischen Eingangssignals
US3114057A (en) * 1961-10-04 1963-12-10 Frank E Caruso Cascaded differential amplifiers with biased diode switches for providing single output dependent upon input amplitude
US3280319A (en) * 1963-02-13 1966-10-18 Nathan Amos Electronic multiplier
US3412339A (en) * 1965-07-07 1968-11-19 Conrad H. Koning Variable-gain amplifier
FR2414268A1 (fr) * 1978-01-05 1979-08-03 Analog Devices Inc Convertisseur analogique-numerique parallele
EP0126868A2 (en) * 1983-03-30 1984-12-05 Kabushiki Kaisha Toshiba Quantizer-subtractor circuit
EP0126868A3 (en) * 1983-03-30 1988-05-11 Kabushiki Kaisha Toshiba Quantizer-subtractor circuit
US4837505A (en) * 1985-11-20 1989-06-06 Ricoh Company, Ltd. Test mode activation circuit

Also Published As

Publication number Publication date
CH288032A (fr) 1952-12-31
BE487541A (et)
DE977039C (de) 1964-12-10
GB659576A (en) 1951-10-24
FR981785A (fr) 1951-05-30
ES187210A1 (es) 1949-04-16
NL84059C (et)

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