US2556200A

US2556200A - Electrical translation system

Info

Publication number: US2556200A
Application number: US11261A
Authority: US
Inventors: Lesti Arnold
Original assignee: International Standard Electric Corp
Current assignee: International Standard Electric Corp
Priority date: 1948-02-26
Filing date: 1948-02-26
Publication date: 1951-06-12
Anticipated expiration: 1968-06-12
Also published as: BE487541A; FR981785A; NL84059C; DE977039C; GB659576A; ES187210A1; CH288032A

Description

June 12, 1951 A. LES-rl 2,556,200

ELECTRICAL TRANSLATION sYsTEu Filed Feb. ze, 194s 5 sheets-sheet 1 VL 72465 DIV/DEI? VOL 77765 D/ V/DEP VOL TME 0/ V/DEP voz 7466 0/ waff? Voz. 77465 0/ VIDE/17 www June 12, 1951 A ST. 2,556,200

ELECTRICAL TRANSLATION SYSTEM Filed Feb. 26. 1948 5 sheets-sheet 2 l; O 5 a our/ur 0F cana/NW6 CPC'U/T I i oar/Par 0F COME/NMI; g l c/Qcwy- A l l e v5 v4 v: v6 v7 K9 /VPU T VOL 7776 E TO D/DE S l/VPU 7' VOL TAGE June 12, 1951 A. LES-rl ELECTRICAL TRANSLATION sTsTEu 5 Sheets-Sheet 3 Filed Feb. 26. 1948 Jun 12, 1951 A, LE$1| 2,556,200

ELECTRICAL TRANSLATION SYSTEM Filed Feb. 26,. 1948 5 Sheets-Sheet 4 INVEN TOR. 4F/VOLO 577 June 12, 1951 A. LESTl ELECTRICAL TRANSLATION SYSTEM Filed Feb. 26. 1948 f /NPUT 5 Sheets-Sheet 5 A F550 Arx conf/POL /nsfo #ferme/Ps APPH/PH T05 INVENTOR. /I/PA/ D 5 7/ Patented June 12, `T951 ELECTRICAL TRANSLATION SYSTEM Arnold Lesti, Brooklyn, N. Y., assignor, bymesne assignments, to International Standard Electric Corporation, New York, N. Y., a corporation of Delaware Application February 26, 1948, Serial No. 11,261

22 Claims.

The possibility of obtaining cheaply and conveniently a circuit capable of producing an arbitrarily speciiied non-linear response is of great importance to the communication industry, to

the art of automatic calculation, to nuclearV physics, and to many other branches of science and engineering. In one present known system of obtaining a logarithmic response characteristic, which is of considerable utility in the system of communication known as Pulse Code Modulation, an expensive method based upon the use of silicon crystals carefully maintained in a temperature' controlled oven has' been utilized. The present invention allows the logarithmic 'response' characteristic useful in Pulse Code Modulation to be obtained cheaply and easily; and in fact to be obtained as an incidental result during thepro-cess of coding.

It is an objectof the invention to provide an electrical translator which can be readily adjusted to produce a substantially `arbitrary inputoutput transfer characteristic.

It is another object of the invention to provide an electrical translator having a predetermined arbitrary transfer characteristic, which is constructed enti-rely of passive elements such as resistors, condensers, and simple crystal rectiers.

It is a further object ofv 'the vinvention to provide' an improved amplitude quantizer circuit.

vIt is a speciiic object ofthe invention to provide an improved method of translating pulse amplitude modulation to pulse code' modulation, by means of a simple circuit consisting `entirely ofv passive elements.

In accordance with a feature of the invention, an Yelectrical circuit is provided which may be adjusted in accordance with the method disclosed hereinafter to produce an arbitrarily predetermined transfer characteristic.

In accordance with another feature of the invention, amplitude modulated pulses are applied to a series of biased rectiers, and the output of each of said rectiers is individually adjusted and fed to a combining circuit arranged to produce an arbitrarily predetermined output referred to said pulses. l Y

In accordance with another feature of the invention, amplitude modulated pulses are applied to a series of biased rectiiriers, and the outputs of said rectiers are combined inra number of different combining circuits which function to produce in their output a representation of binary code of the input to said biasedk rectiers.

In accordance with another feature of the invention, two sets of biased diodes are fed in pushpull and the outputs of the two sets are combined in such a way as to produce a desired amplitude transfer characteristic.

In accordance with another feature of the invention, two sets of( biased diodes are fed in pushpull and the output of the two sets are combined in a number of different circuits in different ways, so as to produce a set of desired output transfer characteristics.

The above-mentioned and other features and objects of the invention and the manner of attaining themv will become more apparent and the invention itself will be best understood by reference to the following description of an embodiment of the inventiony taken in conjunction with the accompanying drawings, wherein:

Fig. 1 shows a basic circuit of my invention;

Fig. 2 shows a` family ofl characteristic response curves obtained from the circuit of Fig. l;

Fig. 3 shows a set of input-output characteristics obtained in accordance with ther invention;

Fig. 4 shows a Vcircuit according to the invention for producing a coded representation of amplitude modulated pulses;

Fig. 5 shows a modification of the circuit of Fig. 4;

Fig. 6 shows another group of input-output characteristics;

Fig. 7 shows a modication of the invention;

Fig. 8 shows a push-pull version of the invention;

Fig. 9 shows another embodiment of the invention;

Fig. 10 shows a set of Vinput-output characte'ristics accordingto Fig. 9.

ReferringV rst to Fig. l, I show a signal `source I which produces a signal chc'uacterizeclA by a varying amplitude. The output of signal source I is applied by means of blocking condenser 2 to a groupl of biassed rectifl'ers v3, kwhich may be,

for example, diodes, or preferably simple crystal rectifiers. The negative terminal of each rectier 3 is connected through a load resistor 4 to a source of biassing potential, obtained in cooperation with a positive source of potential from the voltage divider 5. The biassing voltage for each of the rectiiiers is held constant by means of condenser 6. As is well known to those skilled in the art, a given one of the rectiers will not conduct until the amplitude of the voltage from signal source I becomes greater than the bias potential applied to the corresponding rectifier from voltage divider 5. Inasmuch as the rectiers are successively biassed along the voltage divider to higher and higher potentials it is evident that the number of rectiers which conduct upon the application of a signal of a given amplitude, depends upon the amplitude of the signal. Those rectiers which conduct upon application of a signal will have developed across their corresponding load resistor 4 a voltage dependent also upon the amplitude of the signal. The output of each of the load resistors 4 is applied through blocking condensers 'I across resistors 8 to voltage divider 9, where the output of each rectifier undergoes an adjustment in magnitude which will be described more completely hereinafter. The output of the voltage dividers 9 is applied to combining circuit I0. In the combining circuit III, the plurality of outputs from voltage dividers 9 are combined in such a way as to produce a desired output. The manner of accomplishing this will be described more completely hereinafter.

Referring now to Fig. 2, I show a family of characteristic curves representative of the transfer characteristics of a group of biassed diodes such as shown in Fig. 1. In Fig. 2 the rst rectiiier is shown biassed to a potential V1 of zero volts, the second rectifier to a potential V2, the third to potential V3, and so on. The rectiers are shown biassed by uniformly differing amounts, but it is clear that they could be biassed by steadily increasing amounts or in any other irregular fashion. We now wish to use the curves in Fig. 2 in conjunction with Fig. 1 to specify the desired output of combining circuit Ill. We find that we are able to specify the voltage output of Fig. 10 at a number of input voltages equal to the number of biassed rectifiers used in Fig. 1. Assuming that there are N of these rectifiers we may write the following N simultaneous equations, with the unknown mn as the ratio of the voltage output of a voltage divider 9 to its voltage input. Although it is clear that other input voltages might be chosen, we will specify the voltage output of combining circuit I0 for input voltages of V2, Vs and so on up to VN volts.

It is apparent that we have here N simultaneous equations which may be easily solved by Cramers rule, provided the determinant of the coefcient of the Xs does not vanish. This determinant will not be zero when the rectifiers are biassed consecutively along a voltage divider as shown in Fig. 1. They may, in fact, be biassed in a large number of other ways without reducing the determinant of the coeflioient to zero, but the 4 method shown is the one most suitable for certain applications.

A solution of the set of simultaneous equations will in general give a set of xs some of which have positive and others negative values. The voltage dividers 9, however, do not change the positive output from load resistor 4 to negative values. This function is accomplished in the combining circuit IS, Where the outputs whose s are negative are subtracted from those whose s are positive.

The numbers K1, K2 and so on up to KN are the specified Values that the output of combining circuit I0 in Fig. 1 must have for the input voltages V2, Vs and so on up to VN of Fig. 2. It is apparent that the output of the circuit of Fig. 1 can never exceed the input, and it will become clear that the absolute value of these Ks should be kept small with respect to the amplitude of the input signal. An arbitrary ratio of Ks, however, may be obtained at the output of Fig. 1. A logarithmic or any other desired transfer characteristic may accordingly be obtained by use of the circuit of Fig. 1.

A combination of M circuits based on Fig. 1 may be used to obtain an M-element binary code in particular.

Referring to Fig. 3, I show a group of three input-output characteristics which, when obtained in time sequence from a single input, constitute a translation of the input signal into a threeelement seven-level binary code output, as commonly used in coded modulation systems. In order to obtain the transfer characteristics shown Here We have assumed A1=1, A2=2 and so on up to A'1='7. And we have assumed the amplitude of the output of any one of the circuits to be equal to either zero or a as shown in Fig. 3, Where a is kept small. The solutions of the above three sets of simultaneous equations are given below:

` Okt. A Okt. B l Ckt. C

The result of applying these solutions to a circuit based on that of Fig. 1 is shown in Fig. 4. Corresponding parts of Figs. 4 and 1 are given like reference numerals. The voltages taken from blocking condensers 'I are applied, as above described, to suitable impedance matching resistors 8, and to voltage dividers comprising resistances II through I9 as shown. The outputs of voltage dividers II-I8, I3-I8, I5-I8, and I'I-I8 are added on resistor I8, and the outputs of voltage dividers I2-I9, I4-I9 and I6-I9 are added on resistor I9. The voltage on resistor I8 is applied to one terminal of the primary of transformer 20, and the voltage on resistor I9 is applied to the opposite terminal; while the center top of the primary is connected to the common junction of resistors I8 and I9, and to grou-nd. The transformer 29 constitutes a subtraction circuit of the voltage on resistor I9 from that on resistor I8, and the output is taken on the secondary of transformer 2G.

On the basis of the above listed solutions of the simultaneously equations-for the values of X, the ratio of resistor I8 to the sum of resistor II and resistor I8 is made equal to a, the ratio of resistor I9 to the sum of resistor I2 land resistor I9 is made-equal to 2a, that of resistor I8 to the sum of resistor I3 plus resistor I8 equal to 2a, that of resistor I9 tothe-sum of resistor I4 plus resistor I9 equal to 2a, that of resistor I8 to the sum of resistor I5 plus resistor I8 equal to 2a, that of resistor I9 to the sum of resistor IB plus resistor I9 equal to2a, and that of resistor I8 to the sum of resistor I? `plus resistor I8 equal to2a. Resistors II through Il are all made relatively large compared to resistors I8 and I9. Resistors I8and I9 are considered to include the resistance looking towards the transformer. The values of resistors 8 are all adjusted independently to present the same lead impedance to each of the rectifiers 3. The transformer 20 shown in the-combining circuit A is selected to be capable of passing a band of frequencies which includes the frequencies present in they signal produced by signal source I. The output of the combining circuit A then is that shown in Fig. 3.

In 'a similar fashion to that described above, the output of the rectifiers is applied to combining cir-cuits B and C of Fig. 4 through resistance voltage divider adjusted on the basis of the values of a: obtained for the circuits B and C as listed above. The output of circuits B and C will then be as shown in Fig. 3. In order to obtain pulse code modulation most conveniently from the circuit of Fig. 4, it is convenient that the input signal consists of pulses modulated in amplitude; The outputs as given by Fig. 3 will then 'appear simultaneously for each input pulse at the output vof circuits A, B, and C. If the three code Aelements are to ber transmitted in time sequence, as is often convenient,

delay devices

22 and 23 may be inserted at the output of combining circuits B and C. r'lhe'outputs are then passed through 'coupling pads 2l and when combined directly consist of pulses code modulated inaccordance with the amplitude of the input signal pulse.

Fig. 5 shows an alternative arrangement of the portion to the right of line 5 5 of Fig. 4 for translating amplitude modulated pulses to code modulated pulses in accordance with the invention. Corresponding elements of

vFigures

5 and 4 are given like reference numerals. After passing through the potential dividing resistors I I through I9, the voltage across resistor I8 is applied to the control grid of tube 2 and that across resistorv I9 is applied to the control grid of tube 25. The output oi tube 24 is taken from its cathode, while that of tube 25 is taken from its plate as shown. These tubes are arranged to have the same gain, and they constitute a subtraction circuit of the voltage on resistor I9 from that on resistor- I8. The outputs are combined through

condensers

26 and 21 and applied to the control grid of tube 28. The plate circuit of tube 2B has condenser 29 which is charged negatively when a positive code pulseV appears on the input of tube 258. Condenser 29 stores the charge for a short time controlled by the time constant of the resister-condenser combination 29-39, and the resulting voltage is yapplied to the control grid of tube 3 I, 'whose plate is tied to the plate of tube 32. If either or both tubes 3I and 32 have their grids relatively positive, the voltage at their plates is low, but if both their control grids have a negative voltage on them the voltage at their plates, which are connected to the output, lwill rise. A positive voltage into tube 28 will charge condenser 2'9 negatively to cut oif tube 3 I. Under this 'condition, and only then, if a negative keying pulse is applied at 33 to the control grid of tube 32, which is normally conductive, a positive pulse will appear at the output whose duration is equal to that of the keying pulse. The resistor 30 will discharge condenser 28 in time for the next input pulse.

Subtraction circuits B and C function in a similar manner but have their voltage divider resistors at the input adjusted in accordance with the solution of the equations for the corresponding circuit, as given above. When it is desiredto deliver the code elementsyas 'a sequence-of pulses on the output, a set of keying leadssuch as 34, 35 and 36 is provided, on which gating pulses occur in sequence. These gating pulses may be easily obtained by conventional means, and are synchronized in groups with the amplitude Amodulated into pulses. For example, tube 3I of circuit A is gated by the pulse on lead 34. A short time thereafter a Acorresponding tube in subtraction circuit B is gated by a later pulse v0n lead 35. Still later a gating occurs in circuit C on lead 36. The common output of these circuits will then consist of a group oi coded pulses corresponding to the input amplitude. After the termination of the'last gating action, a new signal pulse is applied to the input to start a new cycle of operation.

While the arrangement shown is with positive input and positive bias on the re'ctifiers, it is obvious that a negative input could be taken care of'in a similar manner by reversingthe polarity of the bias and reversing the rectiers. A large f number of subdivisions of the pulse amplitude into a correspondingly large code combination output can be achieved by increasing the number of rectiers and the number of combining circuits such as A, B and C. There Iwould be as many rectiers as distinct code combinations or 2M rectiers; while there would be M circuits such as A, B, and C, corresponding to the M code elements.

Referring once again to Fig. 3, it may be noted that on certain input voltages, as for example a voltage half way between V4 and V5, the output vof the translators of Fig. 4 and 5 is given not by the code corresponding to either V4 and V5 but to the code corresponding to Vs. That is, for input voltages very close to half way between V4 and V5 the output of the circuit of Fig. 4 or 5 will be seriously in error. This undesirable effect is referred to as skip-jumping and one method of over-coming it is explained below, with reference to Fig. 6.

Fig. 6 shows a new set of response characteristics for subtraction circuits A, B, and C. It is to be noted that the above-mentioned skipjumping effect no longer occurs because the width of each of the responses has been narrowed so that there is no longer any overlap. At the same time, however, a zero reading is obtained at the output lof the circuit, at the times Where skip-jumping formerly occurred. The response characteristics shown may be conveniently 'obtained by utilizing a larger number of rectiers and adjusting the output of the various subtraction circuits. At the places where skipjumping would normally occur, zero output is obtained, and advantage is taken of this fact in accordance with Fig. 1. Fig. 7 Shows in block diagram form a circuit such as that of Fig. 4 or 5. rlhe outputs of the combining circuits A, B, and C which are produced simultaneously are fed to a feedback control circuit 31. The function of feedback control 31 is to take the combined output of circuits A, B, and C, and when their sum is zero add a small negative voltage to the input to the biassed rectifier circuit 38. The result will be that the input signal amplitude is reduced or raised by a small amount to a level which falls within the next lower amplitude range. If, however, an output occurs on any of the combining circuits A, B, or C, feedback control circuit 31 is adjusted to apply no additional voltage to the signal input. When the feedback control circuit 31 is actuated by the absence of an output of one of the circuits A, B, or C, the magnitude of the resultant feedback control output voltage is such as to reduce or raise the input signal by a small amount so that an output will occur on one or more of the circuits A, B, or C. The magnitude of the output feedback control voltage is kept small, say one half the magnitude of the smallest difference in levels Vi-Vi-i. The exact circuit details of feedback control circuit 36 will Vary with the particular application, but suitable circuits will be readily apparent to those skilled in the art.

Referring now to Fig. 8, I show a modification of my invention which reduces the combining circuit to a simple addition circuit, and which avoids the need for subtraction devices. This result is accomplished by utilizing a push-pull input as shown so that both the positive and negative voltages from any rectifier which is actuated become available across the output load resistors of the various rectiers for utilization in the combining circuits. In the circuit arrangement shown in Fig. 8, there are two positive Xs taken from the upper set of biassed rectifiers and two negative Xs taken from the lower set of biassed rectiers. The resultants are simply added in circuit 39,`and no subtraction circuit is required.

Referring once again to Fig. 2, it is evident that some of the voltages output from the biassed rectiers reach relatively large values. It is well known that in performing the operation of subtraction by mechanical or electrical means, more precise results are generally obtained when taking the difference of two small numbers, than when taking the difference of two large numbers, although the difference in question may be the same in both cases. In order to take advantage of this fact, and to reduce the errors which might be occasioned by the subtraction of large numbers such as those corresponding to the response curve shown in Fig. 2, a circuit for obtaining a more suitable series of response curves is shown in Fig. 9. The circuit of Fig. 9 is quite similar to that of Fig. 4. The only difference is that the output of each of the biassed rectifiers 3 taken across the load resistor 4 is clipped by an additional biassed rectifier 40 before being passed on through blocking condenser 1 to the remainder of the circuit. The rectifier outputs in this case are action of 'anyone of the rectiers '4U is to prevent the voltage on its positive terminal from rising very much above the voltage on its negative terminal. After passing through the blocking condenser 1, the voltage across resistor 8 will, therefore, not rise by an amount very much greater than the difference between two biassing levels. A set of characteristics response codes for a group of rectifers biassed in accordance with Fig. 9 is shown in Fig. 10. Fig. 10 thus corresponds to Fig. 9 in the same way that Fig. 2 corresponds to Fig. l. It is apparent that a set of simultaneous equations relating the output of Fig. 9 to the input can be written based on Fig. 10 in a manner similar to that outlined above.

- It should be pointed out that in the above arrangement the process of quantizing and coding a signal in accordance with its quantized value has been carried out simultaneously. It should also be clear that the process of compression and expansion in a logarithmic fashion can also be carried out simultaneously by suitably locating the bias point on the biassing potentiometer 5, and by suitably writing the simultaneous equation to be solved.

While I have described above the principles of my invention in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation to the scope of my invention.

I claim:

l. An electrical translator comprising a signal source plurality of circuits each adjusted to pass only that portion of a voltage above a given corresponding level, means for applying said signal to said circuits, individual voltage dividing means adapted to produce output voltages proportional to the input voltages, each dividing means being associated with a separate one of said circuits and adjusted in accordance with the desired response characteristic, means for applying the said passed portion of a voltage above a given corresponding level of each of said circuits to said associated voltage dividing means, and means for combining the outputs of said voltage dividing means so as 'to produce said response characteristic.

2. An electrical translator comprising a signal source, a plurality of load resistors, a plurality of rectiiiers each biassed across a corresponding one of said load resistors to a corresponding voltage, means for applying said signal to said rectiflers, and means for combining predetermined proportions of the voltages developed across said load resistors in response to said signal in such a Way as to obtain a required output versus input response characteristic.

3. An electrical translator comprising a signal source, a plurality of load resistors, a plurality of rectiers each biassed across a corresponding one of said load resistors to one of an equal plurality of different voltages, means for applying said signal to said rectiers, a plurality of voltage dividers, means for coupling the voltage developed across each of said load resistors in response to said signal to a corresponding one of said voltage dividers, means for adding the output of the predetermined ones of said voltage dividers to obtain a first sum, means for adding the output of predetermined others of said voltage dividers to obtain a second sum, combining means for subtracting said second sum from said first sum to obtain a resultant, and an output circuit for said from the load resistors 4I. It is clear that the 75 resultant.

'4. An electrical translator according to claim 3 wherein said` combining means comprises a transformer.

5. An electrical translator comprising a signal source, a plurality of load resistors, a plurality of rectiiiers each biassed across a corresponding one of said load resistors to one of an equal plurality of different voltages, means for applying said signal to said rectifiers,v a plurality of voltage dividing resistors, part of which are connected to a first common resistor and part to a second common resistor, a plurality of blocking condensers for coupling the voltage developed across each of said load resistors in response to said signal to a corresponding one of said voltage dividing resistors, a plurality of impedance matching resistors, each connected to the common junction of a corresponding blocking condenser and voltage divider resistor, combining means for subtracting the voltage ceveloped across said second common resistor from the voltage developed across said rst common resistor to obtain a resultant, and an output circuit for said resultant.

6. An electrical translator according to claim 5, wherein said combining means comprises a transformer having a primary and a secondary Winding, one terminal of said primary being connected to said rst common resistor, the other terminal of said primary being connected to said second common resistor, the remaining terminals of the two said common resistors being connected together, and said secondary comprising said output circuit.

'7. An electrical translator according to claim 5,

wherein said combining means comprises a pair of electron dischargev devices, one of which has its output taken from its anode circuit and the other of which has its output taken from its cathode circuit, one of which has its output taken from said rst. common resistor, and the other of which has its input taken from said second common resistor, and meansr for combining said outputs.

8. An electrical translator comprising a rst plurality of rectiiiers each biassed across a corresponding load .resistor to a corresponding positive voltage, a second plurality` of rectiers each negatively biassed acrossV a corresponding load resistor to a corresponding negative voltage, a source of a positive signal and a negative signal of equal magnitude, means for applying said positive signal to said rst plurality of rectiiers, means for applying said negative signal to said second plurality of rectiflers, means for individually dividing the amplitude of the voltage produced across each of said load resistors in response to said input signals, and means for cornbining said divided voltages in such a way as to obtain a specified output voltage versus input voltage response characteristic.

9. A method Aof translating an electrical signal using a plurality of load resistors and a plurality of rectifiers each biassed across a corresponding one of said load resistors to a corresponding voltage, comprising individually dividing the magnitude of the output voltage developed across each of said load resistors in response to said signal by a predetermined factor which is different for at least two of said resistors to produce output voltages of different magnitude, and combining said divided outputs to obtain a desired output versus input response characteristic.

10. A method according to claim 9 further comprising the method of evaluating said predetermined factor, comprising the solution of a lset of linear simultaneous equations based on the y response characteristics of said biassed rectifiers and on said desired output versus input characteristic.

1l. An electrical translator according to claim 3y wherein said means for coupling the voltage developed across each of said load resistors in response to said signal' to a corresponding one of said voltage dividers, comprises a clipper for individually clipping each of said developed voltagesl at a predetermined level, and means for applying the output of said clipper to said voltage divider.

l2'. An electrical translator according to claim 11, wherein said clipper comprises a biassed reotiiier.

13; An electrical translator for translatingasingie voltage into a plurality of voltages comprising a plurality of biassedrectiers, means for applying said single voltage to said rectiers, and a plurality of combining circuits, of which at least one has a combining characteristic different from another, for each separately combining the outputs of all of said rectiiiersv in such a way as to obtain said plurality of voltages.

14. An electrical translator comprising a signal source, a plurality of load resistors, a plurality of rectiers each biassed across a corresponding one of said loadr resistors to a corresponding voltage, means for applyingY said signal to said rectiers, a plurality of voltage-dividing circuits for each separately and individually adjusting the proportion of the amplitude of the voltage taken from each load resistor, and means for combining the adjusted voltages in each of said circuits in such a Way as to obtain a plurality of desired output versus input response characteristics.

l5. An electrical translator comprising a signal source, a plurality of load resistors, a plurality of rectiiiers each biassed across a corresponding one of' saidv resistors to one of an equal plurality of different voltages, means for applying said signal to said rectiiiers, a plurality of combining circuits, each of said combining circuits comprising` a plurality of voltage dividers, means for coupling the voltage developed across said load resistors in response to said signal to a corresponding one of said voltage dividers, means for combining the outputsof predetermined ones of said voltage dividers to obtain a rst sum, means for combining the outputs of predetermined others oi saidr voltage dividers to obtain a second sum, means for subtracting said second sum from said rst sum to obtain a resultant for each of said combining circuits, an output circuit for each of said resultants associated with each of said combining circuits, and means for combining the output in each of said output circuits.

16. An electrical translator for translating amplitude modulated pulses to binary code modulated pulses, comprising a plurality of load resistors, a plurality of rectiers each biassed across a corresponding one of said load resistors to one of an equal plurality of different voltages, means for applying said amplitude modulated pulses to said biassed rectiers, a plurality of combining circuits, each separately responsive to selected ones of the voltages developed across each of said load resistors in response to the input amplitude modulated pulses, each of said plurality of combining circuits comprising means for individually adjusting the voltage amplitude of said plurality of selected voltages in such a way as to produce in the output of said combining circuits a pulse when lthe binary code representation of the input amplitude modulated pulse has a corresponding element present and to produce zero output when the primary code representation of the input amplitude modulated pulse has the corresponding element absent, and utilization means for the resulting binary code representing the input amplitude modulated pulse.

17. An electrical translator for translating amplitude modulated pulses to binary code modulated pulses, comprising a source of amplitude modulated pulses, a plurality of load resistors, a plurality of rectiiiers each biassed across a corresponding one of said load resistors to one of an equal plurality of different voltages, means for applying said amplitude modulated pulsesrto said biassed rectiers, a plurality of combining circuits, one corresponding to each possible code element in the binary code representation of an input modulated pulse, means for applying the individual voltages developed across said load resistors in response to said amplitude modulated pulses to each of said combining circuits, each of said combining circuits comprising voltage dividing and polarity selecting means arranged to combine said individual voltages so as to produce in the output of the corresponding combining circuit a pulse when the binary code representation of the corresponding input modulated pulse has an element present corresponding to said combining circuit and to produce no out put from the corresponding combining circuit when said binary code representation has no element present.

18, An electrical translator according to claim 17, further comprising a plurality of delay devices, each connected to the output of a corresponding one of said combining circuits, and means for combining the output of said delay devices to obtain in response to each of said input amplitude modulated pulses a code group representative of said input amplitude modulated pulse with the elements of said code group arrangedin time sequence.

19. An electrical translator according to claim 17, comprising a source of a sequence of keying pulses, on sequence being associated with each input amplitude modulated pulse, means for applying a corresponding pulse of each sequence to a corresponding combining circuit so as to key said combining circuits in time sequence, and means for combining the output of said combining circuits so as to obtain in response to each ofsaid input amplitude modulated pulses a binary code group representation with the ele-` ments of said code group arranged in time sequence.

20. An electrical translator comprising a signal source, a plurality of translating circuits each having linear response curves mathematically independent of the curves of the other circuits, means for applying the signal to the input of each of said translating circuits, means for dividing the magnitude of each of the outputs of said translating circuits according to a predetermined factor which is different for at least tWo of said outputs, and means for combining the divided voltages.

21. An electrical translator comprising a signal source, a plurality of translating circuits each having linearly independent response curves, means for applying the signal to the input of each of said translating circuits, a plurality of dividing means each dividing means dividing the magnitude of each of the outputs of said translating circuits according to a predetermined factor, this factor with respect to at least one of said outputs being different from each other for at least two of said dividing means, and means for combining the divided voltages.

22. An electrical translator comprising a signal source, a plurality of translating circuits providing a set of linearly independent response curves, means for applying the signal to the input of each of said translating circuits, and a plurality of combining circuits each including means for dividing the magnitude of each of the outputs of said translating circuits according to a predetermined factor, and means for combining the divided voltages, at least one of said combining circuits having a different response characteristic from one of the other combining circuits.

ARNOLD LESTI.

REFERENCES CITED The following references are of record in the le of this patent:

UNITED STATES PATENTS Number Name Date 2,416,329 Labin et al Feb. 25, 1947 2,420,374 Houghton May 13, 1947 2,453,461 Schelleng Nov. 9, 1948