GB2219113A

GB2219113A - Curve approximating circuits

Info

Publication number: GB2219113A
Application number: GB8911401A
Authority: GB
Inventors: Sheng-Hann Lee; Marina Shou-Chun Chao
Original assignee: Teledyne Industries Inc
Current assignee: TDY Industries LLC
Priority date: 1988-05-20
Filing date: 1989-05-18
Publication date: 1989-11-29
Also published as: DE3916431A1; GB8911401D0; JPH02141012A

Description

7 1

CURVE APPROXIMATING CIRCUITS DESCRIPTION

This invention relates to curve approximating circuits or logarithmic amplifiers, such as are used for dynamic range expansion in video frequency systems.

In many electronic circuits it is desirable to implement a non-linear or variable slope transfer function such as a logarithmic transfer function of the form eout = Allog(ein)r where ein is an input voltage signal, eout is an output voltage signal, and Al is an amplification constant. Such non-linear transfer functions are particularly useful for compressing and decompressing signals of wide dynamic range (e.g. 60dB) in telecommunication systems. Circuits which provide such transfer functions are sometimes referred to as log video amplifiers (LVA) because of their popularity in video frequency systems. Reference is now made to Figures 1 and 2 of the accompanying drawings, in which: 25 Fig. 1 is a graph of a logarithmic transfer function, Fig. 2A is a schematic diagram of a previous logarithmic circuit employing saturation- limited amplifiers, 30 Fig. 2B is a graph of the transfer function of a previous saturation-limited amplifier, Fig. 2C shows a saturation-limited amplifier comprising a diode clamping circuit, Fig. 2D graphs the current versus voltage characteristics of a conventional clamping diode, and 1 Fig. 2E is a schematic of a differential amplifier sometimes used to form the saturation-limited amplifiers of Fig. 2A.

It can be seen, by referring to the logarithmic 5 curve shown in Fig. 1, that the output signal versus input signal derivative, or slope, of the curve eout = log( ein) decreases monotonically as the input voltage ein increases. This means that the small signal gain d(eout)/d(ein) of a circu-it implementing the logarithmic transfer function (or other variable slope function) needs to change with input signal level. It is common practice to approximate variable slope curves of this nature by using a multiple section approximating circuit 20, such as shown in Fig. 2A.

The multiple section approximating circuit 20 comprises a plurality of saturation- limited amplifiers SA1, SA2, SA3,r...r SAn, a voltage summing means 25 for summing SJP/M-706 9 11 12 13 14 16 17 18 19 respective output signals eol, eo2, eo31..., eon of the saturation- limited amplifiers SAl-SAn, and a plurality of nonsaturable amplifiers NAl, NA21. . NAn-1 connected in 4 series between input nodes of the saturation-limited amplifiers. The input voltage signal ein is presented to 6 the input node of the first saturation-limited amplifier SA, 7 while a once amplified version of the input signal ex, = GN ein appears at the input node of the second saturationlimited amplifier SAV a twice amplified version of the input signal ex2 GN 2 ein appears at the input node of the third saturation-limited amplifier SAP and eventually, an (n- 1) times amplified version of the input signal exn-1 GN (n-l)ein appears at the input node of the last saturation limited amplifier SAW amplification factor GN here being the gain of nonsaturable amplifiers NAl, NA21..., NAn-l The saturation-limited amplifiers SAl-SAn each have an input/output characteristic curve 5 such as shown in Fig. 2B wherein the output signal e., of amplifier SA, for example, increases as a linear ramp function eol=k1ein while the input signal ein is relatively small and then, at some saturation-limiting point P. along the input scale, the 21 22 magnitude of the output signal eol asymptotically flattens 23 out towards a maximum level emax as the magnitude of the 24 input signal ein is further increased. This type of curve can be used to approximate a section of a log curve 6 to a 26 maximum allowable approximation error as indicated by the 27 separation between solid curve 5 and dash-dot curve 6 in 28 Fig. 2B. Nonsaturable amplifiers NAl-NAn-1 have linear 29 ramp-like characteristics over the full range of input signal ein 31 Figure 2C illustrates one circuit SA' for implementing 32 the saturation-limited amplifiers SA,-SAn, A first terminal 33 of a clamping diode Dclamp is coupled to a low resistance 34 output Rout (e.g. 4 ohms) of a linear amplifier 10 having a gain K,. The circuit SA' is arranged in a manner which 36 causes the diode Dclamp to be forward biased and driven into 37 a saturated portion 12 (Figure 2D) of its current versus 38 voltage characteristic curve 14 whenever the amplifier WP/M-706 1 output voltage VO exceeds a clamping voltage Vclamp provided 2 at a second terminal of the diode Dclamp, The output 3 resistance Rout is chosen sufficiently small so that its presence is negligible for low level outputs YO << v clamp but sufficiently high such that the clamping diode Dclamp 6 will be protected from burn out when high level output 7 signals VO > Vclamp are developed.

8 The operation of diode based circuits such as SA' of 9 Fig. 2C may be undesirably affected by an inherent temperature sensitivity characteristic of the clamping diode 11 Dclamp, which is particularly pronounced near saturation, 12 and by the inability of the diode Dclamp to quickly come out 13 of saturation (recovery time) when the output voltage VO suddenly jumps from a level well above the clamping voltage, v 0 >> Vclamp, to a level below the clamping voltage, 14 is 16 Vo < Vclamp. The so-called recovery time of the clamping 17 diode Dclamp tends to increase as the diode is driven 18 further into saturation. Also the usable dynamic range of 19 circuit SA' is generally limited to 6 db (for 0.3 db 20 approximation error) when approximating the log curve 6 (Fig. 2B).

Referring back to Fig. 1, it should be understood that if a 60 db dynamic range is desired, ten stages SA,-SA10 of the SA' configuration would be required. Also it should be understood that when the input voltage signal ein Of circuit -26 20 is relatively small, all the saturation-limited 27 amplifiers SA, - SAn are expected to be operating in linear 28 portions of their respective transfer curves so that the 29 cumulative slope, S, = d(eOl + eo2 + eo3 + + 31 21 22 23 24 25 32 33 34 35 36 37 38 eon)/d(ein) of the summed output signal, eout = e0l + e02 + . + eon, is relatively steep at a first point P, along the abscissa of the Fig. 1 plot. As the magnitude of the input voltage signal ein increases to a second point P21 the n-l times amplified input signal exn presented to the last saturation-limited amplifier SAn forces that amplifier SAn to clamp into a saturation mode. The corresponding slope term d(eon)/d(ein) contributed to the total output gain d(eout)/d(ein) by the last output signal eon approaches zero WP/M706 1 and a second, less steep slope S2 = d(e., + e.2 +. ' - + 2 eon-l)/d(ein) results at second point P2. When the 3 magnitude of the input voltage signal ein increases to yet a 4 third point P31 the next to last saturation-limited amplifier, e.g. SA3, goes into a saturation mode and this 6 further decreases the slope or small signal gain of the 7 circuit 20. Eventually the first saturation-limited 8 amplifier SA, of the series SA, - SAn is also driven into a 9 saturation mode and the slope d(eout)/d(ein) flattens out to zero. A reverse process, of progressive increases in 11 circuit gain, takes place when the magnitude of the input 12 voltage signal ein decreases past points l3, P2 and P,.

13 The multiple section circuit 20 of Fig. 2A has a number 14 of disadvantages, most notable of which is a requirement for a large number of amplifiers. Whenever further slope 16 approximating steps, e.g., slopes S4, S51. .. are 17 desired for the purpose of decreasing the approximation 18 error and/or increasing the total dynamic range of the 19 approximating circuit 20, the addition of individual saturation-limited amplifiers, e.gr SAn+11 SAn+21 1. and 21 nonsaturable amplifiers, e.g., NAn, NAn+11... on a two 22 amplifiers per step basis is required for each additional 23 slope approximating step desired. This two-for-one 24 amplifiers per step increase disadvantageously adds to the cost and complexity of the approximating circuit 20. It 26 further exacerbates a signal propagation delay problem which 27 is already inherent in the multiple section approximating 28 circuit 20. The serial topology of nonsaturable amplifiers 29 NA, through NAn-1 mandates that low level input signals (non-saturating signals) propagate through the summed time 31 delays of all the nonsaturable amplifier stages NAl-NAn-1 32 before a valid summed output signal eout can be developed at 33 output node 25a of the summing means 25. This additive type 34 of time delay disadvantageously reduces the rise time of the summed output signal eout The delay due to the low level 36 signal propagation problem is particularly annoying when the 37 circuit 20 must handle very small but very fast changing 38 input signals ein such as may occur in video systems. The WP/M-706 1 serial ganging of amplifiers NA, - NAn-l also disadvantageously acts to narrow the overall bandwidth of 3 the system with respect to low level, high-frequency input signals. A bandwidth constriction effect is known to occur when multiple amplifiers having identical structures are 6 strung together in serial fashion. Yet another problem 7 associated with low level signals is that of adjusting the zero points of saturation-limited amplifiers SAl-SAn and 9 non-saturable amplifiers NA1-NAn-l so all the amplifiers will produce zero level output signals eol-eOn 11 simultaneously when the input signal ein is at a zero level 12 (zero offset adjustment problem).

13 At the other end of the input scale, where relatively 14 large but again very fast changing input signals (saturating signals) ein are presented (for example, input signals 16 having step-like waveforms of large magnitude and steep 17 falling edges), the response time of circuit 20 is limited 18 by the time it takes for saturation-limited amplifiers SAl 19 SAn to recover out of saturation. The recovery time of each saturation-limited amplifier may be defined as the time 21 needed to recover out of saturation and reenter the linear 22 portion of its operating curve. This recovery time tends to 23 increase as the amplifier is driven deeper and deeper into 24 saturation. The last saturation- limited amplifier SAn which receives the n-l times amplified input signal enx ' 26 GN (n-l)ein will tend to be driven far more heavily into 27 saturation than will front end amplifiers SA2 or SAl. As 28 such the last amplifier SAn will have the most difficulty in 29 coming out of saturation when the input signal ein shifts rapidly from a relatively high level to a relatively low 31 level. This saturation recovery phenomenon can 32 significantly limit the usable frequency range of the 33 multiple section approximating circuit 20.

34 In cases where the circuit 20 is to operate with high frequency signals, such as present in video processing 36 circuits (DC-20MHz), all the amplifiers SAl-SAn and NAl 37 NAn-l need to be of a very high frequency variety 38 (bandwidths > 20 MHz) in order to compensate for the above- 1 SJP/M-706 1 described low level signal propagation problem and the high 2 level saturation recovery problem. When this high frequency 3 requirement is placed on all the amplifiers of circuit 20, 4 it can greatly increase the cost and complexity of the overall circuit.

6 The multiple section circuit 20 of Figure 2A is 7 sometimes referred to, when it is formed with amplifiers 8 SA, - SAn each having a diode clamped circuit configuration 9 such as shown in Figure 2C, as a linear-limited log video amplifier circuit. Another circuit, referred to as a non 11 linear log amplifier, is disclosed in a book by Richard 12 Smith Hughes, "Logarithmic Amplification", Artech House, 13 1986. The latter circuit is often used in place of the 14 linear-limited log circuit for implementing logarithmic transfer functions. The non-linear log circuit utilizes 16 differential amplifiers with constant current sources such 17 as shown in Figure 2E in place of clamping diodes for 18 limiting output voltage in a saturation-like manner. The 19 advantages of such non-linear limiting circuits is that they can offer a greater dynamic range than diode clamping 21 circuits (usually 13 db per stage for 0.3 db error versus 22 the 6 db range per stage of diode clamped circuit) and they 23 can be designed to overcome the saturation recovery problem 24 of clamping diodes as well as the need for larger number of stages. But the non-linear log amplifier circuits generally 26 suffer from severe temperature instability (e.g. changes in 27 gain and saturation knee point relative to temperature), 28 problems with accurate alignment of knee points of multiple 29 stages along a desired transfer function curve, and more importantly, they don't overcome the small signal 31 propagation delay problem associated with serial ganging of 32 video stages.

33 A third circuit for realizing the log transfer function 34 uses multiple RF detectors coupled to tap points of a multiple stage microwave amplifier. The third circuit is 36 often referred to either as an RFDLVA (radio frequency 37 detector log video amplifier) or a successive detection 38 LVA. While the RFDLVA may offer improved rise time response, its primary disadvantages are linearity, cost, complexity and temperature sensitivity.

In accordance with the present invention, a logarithmic amplifier or other transfer function approximating circuit comprises a plurality of voltage dividers each formed of first and second resistive elements joined at a voltage generating node so as to produce different constant voltage levels at respective voltage generating nodes when no currents are supplied from other elements of the circuit to the voltage generating nodes. A plurality of level triggered switches, e.g. switching diodes, are each connected to respective ones of the voltage generating nodes so as to couple a voltage changing current to each of the nodes when the corresponding switch is closed (switching diode is forward biased) and to not couple a voltage changing current to the node when the switch is open (switching diode is reverse biased).

Each of the switches (or switching diodes) has a first terminal connected to its respective voltage generating node and a second terminal connected to the other switches at a common input node. As the magnitude of an input voltage supplied to the common input node changes, some of the switches (switching diodes) may be rendered non-conductive (reverse biased) because the input voltage causes the switches (diodes) to be triggered open (switched OFF) and other of the switches (switching diodes) may be rendered conductive (forward biased) because the input voltage causes them to be triggered closed (switched ON). As a result of WP/M-706 1 this action, the input voltage appears (ignoring minor 2 voltage drops of closed switches) at the voltage gene;ating 3 nodes of the switches (diodes) that are switched ON 4 (conductive) and the different constant voltages appear at the voltage generating nodes of the switches (diodes) that 6 are switched OFF (nonconductive).

7 The voltage levels appearing at the plural voltage generating nodes, be they constant or input signal 9 dependent, are passed through attenuation networks or amplifier input networks of preferably differing 11 attenuation/amplification factors, and summed to produce a 12 summed output voltage at an output node.

13 A different number of switches (diodes) will be 14 switched ON or OFF as the input signal changes in magnitude. The small signal gain of the system will 16 accordingly change in response to changes in the input 17 signal magnitude because the constant voltages that appear 18 at the voltage generating nodes of those of the switches 19 (diodes) that open (become nonconductive) in response to a change in input signal magnitude will contribute only a zero 21 term to the small signal gain of the system.

22 A transfer function of continuously decreasing slope 23 with respect to increasing input signal magnitude may be 24 obtained by suitably arranging the switches/diodes to become nonconductive in sequence so that the slope contribution of 26 their corresponding voltage generating nodes sequentially 27 converge toward zero. Only one summing amplifier with 28 plural input terminals is needed for summing the constant or 29 input signal dependent voltages developed at multiple voltage generating nodes. The problems of adding more 31 approximating steps to the circuit transfer function, 32 avoiding small signal propagation delay and/or minimizing 33 large signal saturation recovery are obviated. A simple 34 solution to the problem of approximating a multiple slope transfer function is made possible.

36 37 38 The present invention thus provides a curve approximating circuit of substantially simpler construction and of improved performance than prior art circuits. The invention avoids the saturation recovery problem of the prior art clamping diode system, and overcomes the time delay and bandwidth constriction problems associated with serially ganged amplifiers.

The invention is further described below, by way of example, with reference to the remaining Figures of the accompanying drawings, in which:

Fig. 3A is a schematic diagram of one portion of a variable slope approximating circuit in accordance with the invention, Fig. 3B graphs the transfer function of the one portion shown in Fig. 3A, Fig. 4A is a schematic diagram of a first curve approximating circuit in accordance with the present invention; Fig. 4B graphs the transfer function of the circuit of Fig. 4A, Fig. SA is a block diagram of a second circuit in accordance with the present invention, Fig. 5B shows a variation on the theme of Fig. SA, Fig. 6 is a schematic diagram of a third circuit including a temperature compensating and process variation compensating feature, Fig. 7 shows a voltage divider version o-f the invention, and Fig. 8 is a schematic of an embodiment employing the features of Figs. 6 and 7.

WP/M-706 1 2 Referring to Fig. 3A, the operation of a sub-circuit 30 3 of one embodiment of the invention will be first 4 explained. The sub-circuit 30 comprises a switching diode D,, a resistor R, coupling the anode of diode D, to a 6 constant voltage +VC,, and a high input impedance amplifier 7 Al having a predetermined gain %. Resistor R, and the 8 anode of diode D, are joined at a voltage generating node N2 9 which supplies intermediate voltage VN2 to the high impedance input of amplifier A,. Input voltage VN1 'S 11 applied to the cathode of the diode D, through an input node 12 Nj.

13 If the input voltage VN1 is sufficiently high relative 14 to the constant voltage + VC, at the anode of D, so as to is cause diode D, to be reverse biased, the diode D, will not 16 contribute any current to the voltage generating node N2 and 17 the intermediate voltage at that node will be a constant 18 level VN2 = + VC, Resistor R, in essence couples the 19 constant voltage +Vcl to the voltage generating node N2. If the input voltage VN1 is now decreased so that the switching 21 diode D, comes into conduction, the diode D, will begin to 22 withdraw a current I, from the voltage generating node N2 23 and thereby decrease the intermediate voltage VN2 in 24 accordance with the formula VN2 = VC - I1Rl. Under this condition, the intermediate voltage VN2 will equal the value 26 of the applied input voltage VN1 Plus the forward drop of 27 switched-on diode D,. Amplifier A, multiplies voltage VN2 28 by a predetermined gain factor G, to produce a final voltage 29 V N3 at node N3 in accordance with the formulas:

VN3 = Gl(Vc-I1R1) Gl%l+VD1) for VN, < VN2 31 VN3 = G1Vc f or VN1 VN2 32 where VD1 is the forward drop across diode D,. In many 33 instances, e.g. AC signal analysis, the forward drop voltage 34 V D1 can be assumed to be close to zero and neglected.

The behavior of this sub-circuit 30 is illustrated in 36 Fig. 3B. It should be noted that the slope d(VN3)/d(VN1) 37 goes to zero when the input voltage VN1 increases beyond a 38 switching point PS, and that the location of this switching 4 WP/M-706 -12- 1 point along the VN, axis is determined by the value of the 2 constant voltage +VC, produced at the voltage generating 3 node N2 as a result of potential coupling through resistor 4 Rl. If an ideal switching diode which has no forward voltage drop is assumed for diode Dl, the switching point 6 PS, will be exactly equal to the constant voltage +VC1.

7 Fig. 4A is a schematic diagram of a first curve 8 approximating circuit 40 in accordance with the present 9 invention. It can be seen that this curve approximating circuit 40 employs a plurality of diode/resistor sub 11 circuits Dl/Rl, D2/R2, D3/R3 such as the sub-circuit 30 12 shown in Fig. 3A. The cathodes of diodes Dl-D3 are all 13 connected to a common input node Nl, The anodes of diodes 14 Dl-D31 on the other hand, are individually coupled to different constant voltages +VCl, +VC21 +VC3 by respective 16 potential coupling resistors Rl, R2 and R3. Respective 17 intermediate node voltages VN211 VN22 and VN23 at the anodes 18 of sub-circuits Dl/Rl through D3/R3 are summed by a voltage 19 summing amplifier 45 having a plurality of high-impedance input terminals 41, 42 and 43. Of importance, the switching 21 points PSl_PS3 of the three D/R sub-circuits are set to 22 different values by suitable selection of constant voltages 23 V cl, Vc2 and Vc3 so that diodes Dl-D3 become reverse biased 24 at different points along the input signal voltage scale and they switch off in sequence as the magnitude of input signal 26 vNl increases. input terminals 41, 42 and 43 of the summing 27 amplifier are preferably each associated with different gain 28 factors or signal weighting factors, Gl, G2 and G3 which are 29 approximately one order of magnitude apart from one another (e.g., 10, 100, 1000) so as to develop a logarithmic-like 31 transfer function. The transfer function of the circuit 40 32 33 34 may be expressed as:

eout/ein "" G1VN21 + G2VN22 + G3VN231/ein where VN2i = ein for ein:S Vci and i = 1, 2, 3; 35 and VN2i _ Vci for ein > Vci and i = 1, 2, 3. 36 It will, of course, be understood that in cases where a 37 summing amplifier 45 has input terminals 41-43 of finite 38 input impedances that the Thevenin equivalency theorem can I- 4 %I- SJP/M-706 -13- 2 3 1 be applied to draw an equivalent circuit having an amplifier with infinite input impedances and appropriate series resistances coupling the inputs to the Thevenin equivalent 4 voltage sources of voltages +Vc, and ein The transfer function curve of circuit 40 is shown in 6 Fig. 4B. It will of course be understood that additional 7 linear ramp segments can be added to the curve simply by 8 adding more input terminals to the single summing amplifier 9 45 and more D/R sub-circuits between common input node N, and the additional input terminals of the summing 11 amplifier. This feature is a clear advantage over the 12 expansion requirements of the previous serial circuit 20 13 shown in Fig. 2A. There is no need to add more amplifiers 14 to circuit 40 when expansion is desired. There are no propagation delay penalties or saturation recovery time 16 problems in circuit 40 similar to the problems encountered 17 with circuit 20. Diodes D, - D3 are not in saturation when 18 switching occurs but rather coming into or out of reverse 19 bias so very little charge needs to be moved about the diode junctions when a gain change is desired. Low level input 21 signals do not need to propagate serially through a large 22 number of stages in circuit 40. Instead, the input signal 23 is split current-wise to pass in parallel through the diode 24 switches Dl-D31 when each of the latter is closed, to input terminals 41-43 of the summing amplifier. As such a 26 remarkable simplification of the circuit is obtained 27 together with improved performance.

28 Fig. SA shows a block diagram of another curve 29 approximating circuit 50 having generic switches SW, - SW3 responsively coupled to a switch control 51 such that the 31 switches respectively open or close when the magnitude of a 32 supplied input signal ein passes pre-set trip points PS1, 33 P S2 and PS3 of different values. Each of the switches, when 34 closed, applies the input signal ein to respective input terminals 51, 52 and 53 of summing amplifier 55. When one 36 of the switches SWl - SW3 opens, a corresponding one of 37 resistors Rl, R2 and R3 Pulls its corresponding one of input 38 terminals 51, 52 and 53 to one of constant voltage levels 14 WP/M-7 0 6 1 VC11 VC2 and VC31 Input gains Gl, G2 and G3 Of input 2 terminals 51-53 are preferably each set to a different value 3 to produce a logarithmic-like variable gain transfer 4 function. Switches SWl - SW3 may be formed of any suitable components including for example, Schottky diodes, Schottky 6 transistors and/or high speed field effect transistors

7 having gates charged to different voltages VGl_VG3 and 8 sources/drains acting as opposed ends of dual terminal 9 switches SW1 - SW3' Fig. 5B shows a variation on the theme of Fig. 5A 11 wherein three-terminal switches SWl' SW3' couple input 12 terminals of summing amplifier 155 either to receive input 13 signal ein or constant voltages VC, - VC3 in accordance with 14 the magnitude of input signal ein relative to trip points P sil Ps2 and Ps3 set by control 151. Switches SW11 through 16 SW 31 may, again, be composed of various types of transistors 17 and/or diodes as desired. It is within the contemplation of 18 the present invention to include switches for programmably 19 changing the constant voltages Vcl-Vc3 or the trip-points P sl_Ps3 in response to computer generated instruction 21 signals when such circuit programmability is desired.

22 Fig. 6 shows a temperature compensated version 60 of 23 the invention. Diodes Do - D3 are preferably all Schottky 24 diodes (high speed metal-semiconductor junctions) integrally formed on a common substrate or otherwise matched during 26 manufacture such that they have substantially identical 27 voltage and/or current versus temperature dependencies.

28 Input amplifier 64 forces the voltage at node No to follow 29 the magnitude of input voltage ein in a mirror replicating like linear manner as a result of a negative feedback loop 31 formed by a temperature insensitive voltage divider 32 comprised of resistors RA and RB The voltage at node N, 33 will include the temperature dependent forward drop VDO Of 34 diode Do Temperature dependency cancellation occurs when one of the diodes D, - D3 is switched on by an input signal 36 ein together with diode Do so that the voltage at the 37 corresponding amplifier input terminals, terminal 61 for 38 example, will be of the form VN61 m VNo VDO + V Dl WP/M-706 2 3 16 Process and temperature variations in the terms VDO and VD1 tend to cancel each other out both in the DC sense and AC sense because of the back-to-back relation between diode D 0 and diodes Dl-D3 when moving from the input mirroring node No to any one of amplifier input nodes N61, N62 or N63.

Currents through diodes Do through D3 are preferably kept 7 high to minimize the small signal AC impedance dVD/dID 8 26mV/ID(ma) @ 250C of the diodes DO-D3 9 The present invention contemplates the use of plural voltage dividers such the RAl/RBl divider shown in Figure 7 11 for generating voltages VC1 through VCn at the G, - Gn input 12 terminals of a summing amplifier 75. Those skilled in the 13 art will readily understand how power supply voltages +VC 14 and -VC can be converted to different potential levels VC, VCn, free of temperature and manufacturing variations, using simple voltage division and how the circuit of Fig. 7 may be 17 integrally fabricated on a semiconductive substrate 18 (integrated circuit chip).

19 Figure 8 shows a circuit 80 employing the principles of 20 Figs. 6 and 7. Operation amplifiers 84 and 85 are used for 21 amplifying the input signal ein. The negative input 22 terminal 85a of amplifier 85 acts as a virtual ground point 23 at which the currents of resistors R7, R10 and R13 are 24 summed. It will be noted that the diodes Do - D3 of Fig. 8 25 are inverted in polarity relative to the ones discussed thus 26 far. It should be understood from this that the input 27 voltage signal ein is of anegative polarity and that diodes 28 DO-D3 are switched closed when the voltage at node N, is 29 less negative than respective negative voltages VA, VBj VC and VD at the cathodes of diodes DO-D3' Operation amplifier 31 85 together with gain-determining resistors R7, Rjor R13 and 32 R14 forms the summing amplifier. In one embodiment of the 33 circuit shown in Fig. 8 the components listed in the 34 following table were used. 35 36 37 38 WP/M-706 1 - TABLE 2

3 7 8 9 10 11 12 13 14 Numerous variations and modifications of the circuits 16 disclosed above will, of course, occur to those skilled in 17 the art once the principles of the present invention are 18 understood. As such, the scope of the invention is not to 19 be limited to the above embodiments but rather defined to 20 encompass the subject matter of the following claims. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Ri: R2: R3: R4: R_9: R6: R7: R8:

220 ohms 220 ohms 3.9K 2.OK 15 ohms 2.OK 82 ohms 470 ohms R10: 1. OK R,,: 5. 1K R12: 2. OK R13: 2. 4K R14: 820 ohms DO-D3: Motorla MBD101 84-85: Analog Devices Operational Amplifier AD5539 -V = -8 Volts Rg:

5. 1K W

Claims

CLAIMS is 1. A curve approximating circuit comprising: plural limiting

networks including a voltage input node, a voltage output node, a constant voltage node, a resistor joining the voltage output node to the constant voltage node, and a switching diode connecting the voltage input node to the voltage output node, wherein the respective voltage input nodes of the limiting networks are coupled to receive a common input signal and wherein different constant voltages will appear at the voltage output nodes of the limiting networks when the diodes of the limiting networks are reverse biased; and summing means having plurality input terminals coupled to the voltage output nodes of the limiting networks, for summing voltages developed at the respective voltage output nodes and producing a summed output voltage.
2. A circuit as claimed in claim 1 wherein the input terminals of the summing means are each coupled to signal attenuating/amplifying means which attenuate/ amplify voltages developed at the input terminals in accordance with different 25 attenuation/amplification factors.
3. A circuit as claimed in claim 1 or 2 wherein the switching diodes include Schottky barrier junctions.
4. A curve approximating circuit comprising: a summing amplifier having first to nth input multiplier means of differing multiplier factors G1 to Gn for multiplying the magnitude of a plurality of first to nth input voltage signals; first to nth potential coupling means for respectively coupling first to nth constant voltages VC1 - VCn to the f irst to nth input multiplier means; and first to nth switches having respective first terminals coupled to the f irst to nth input multiplier means and second terminals all coupled to a common signal receiving node, the switches operating-to open at different magnitude values of a common input signal supplied to the common signal receiving node.
5. A circuit as claimed in claim 4 wherein the summing amplifier comprises an operational amplifier and a plurality of resistors each having one terminal coupled to an input node of the operational amplifier and a second terminal forming a respective portion of first to nth input multiplier means.
6. A circuit as claimed in claim 4 wherein the first to nth switches include first to nth diodes which respectively become reverse biased when corresponding ones of the switches are open.
7. A circuit as claimed in claim 6 wherein the diodes are Schottky diodes.
8. A circuit as claimed in claim 4 wherein the first to nth potential coupling means respectively comprise first to nth voltage dividing networks supplying constant voltages VC1 - VCn to the first to nth summing amplifier input means.
9. A curve approximating circuit comprising:

summing means having first to nth weighted inputs for producing an output signal of the form eout = G1 el = G2e2 + -.. + Gnen where Gi is a weighting factor of input i, ei is a signal applied to input i, and n is an integer greater than one; and first to nth switching means each connected to selectively couple the first to nth weighted Q inputs of the summing means so that the inputs respond substantially either to an input signal ein supplied to the switching means or to corresponding ones of first to nth constant voltages VC1 - VCnr the first to nth switching means being responsive to the supplied input signal ein so as to each switch at a different level of the supplied input signal ein-
10. A circuit as claimed in claim 9 wherein the includes first to nth f or summing means attenuation/amplification networks attenuating/ ampli f ying the applied input signals el-en by attenuation/ ampli f i cation factors corresponding to weighting factors G1 to G2 n and a current summing means coupled to the attenuation/ ampl if i cation networks for summing currents of respective amplified/ attenuated signals developed by the attenuation/ ampl if i cation networks.
11. A circuit as claimed in claim 9 comprising temperature drift compensating means, interposed between an input node where the supplied input signal is produced or a mirror node where a mirror replica of the supplied input signal is produced and the first through nth switching means, for cancelling out temperature related voltage changes of the switching means, the compensating means including components that are temperature-wise substantially identical to those of the switching means.
12. A circuit as claimed in claim 11 wherein the first to nth switching means include first to nth switching diodes and the temperature drift compensating means includes a matched voltage drop cancelling diode which is voltage-wise in an opposed back-to-back relation with the first to nth switching diodes such that temperature related drifts in the forward bias 1 11.1 voltages of the f irst to nth switching diodes are matched by an equivalent voltage change across the opposed voltage drop cancelling diode.
13. A curve approximating circuit substantially as herein described with reference to Figures 4A & 4B, Figure 5A, Figure 5B, Figure 6, Figure 7 or Figure 8 of the accompanying drawings.

Published 1989 atThe Patent Office, State House, 66/71 High Holborn, London WClR 4TP. Further copies maybe obtained from The Patent Office. Sales Brancl-4 St Mary Cray, Orpington, Kent BR5 3RD. Printed by Multiplex techniques It4d, St Maxy Cray, Kent, Con. 1/87