US3280319A

US3280319A - Electronic multiplier

Info

Publication number: US3280319A
Application number: US258301A
Authority: US
Inventors: Nathan Amos
Original assignee: Individual
Current assignee: Individual
Priority date: 1963-02-13
Filing date: 1963-02-13
Publication date: 1966-10-18
Anticipated expiration: 1983-10-18

Description

Oct. 18, 1966 A. NATHAN 3,280,319

ELECTRONIC MULTIPLIER Filed Feb. 13, 1965 4 Sheets-Sheet 1 FIG- I (l!) 0- n) 0- FGI 9 (l) (7.!)0- (Z) (12)? F6?- 9 F f (o) 1 FIG. 2

V=Ed 33 U=6d U I2 V I5 22 3| u=0 vz'o so( *4 X FIG. 4-

R0 To INVENTOR v a W Oct. 18, 1966 A. NATHAN 3,280,319

ELECTRONIC MULTIPLIER Filed Feb. 13, 1963 4 Sheets-Sheet 2 I T D (I) Y" D INVENTOR Ch ML ELECTRONIC MULTIPLIER Filed Feb. 13, 1963 4 Sheets-Sheet 5 IN VENTOR Oct. 18, 1966 A. NATHAN 3,280,319

ELECTRONIC MULTIPLIER Filed Feb. 13, 1963 4 Sheets-Sheet 4 X l el uq r N F60 (O) (D -H m y (emai To FIG. 12 A L x g L 113 6 L C U) H7. (O)

0 no I I M; m l (2) L, INVENTOR I N am United States Patent a 0 ,28 31 ELECTRONIC MULTIPLIER Amos Nathan, Dept. El Engg., Technion, Haifa, Israel Filed Feb. 13, 1963, Ser. No. 258,301 18 Claims. (Cl. 235-194) This invention relates to electronic analog multipliers in which an output signal is produced which represents the product of the instantaneous values of two variables. More specifically, this invention includes a squarer having the transfer property which consists in transferring to its output terminal any signal simultaneously applied to all input terminals thereof.

This application is a continuation in part of my prior copending applications Serial No. 801,468 filed March 24, 1959, and Serial No. 837,616 filed September 2, 1959, both now abandoned.

Electronic multipliers have a great number of applications. Of particular interest is their application in analog computers in which the variables are represented in the form of electric potentials. One prior art embodiment of such multipliers uses the quarter squares system in which the product 2 of x and y is written as follows:

where u and v are given by the expressions A quarter squares multiplier first produces signals corresponding to u and v, subsequently employs two squarers for the production of 1: and v from u and v, respectively and finally produces 2: by taking the difference of the square signals. Such a multiplier, while simple in principle, has a number of disadvantages: It usually requires a considerable number of sign changers and/or adders in its implementations; it is liable to introduce errors because of the need of computingx as the difference of two quantities both of which may be large while the required result may be small.

In particular, any quarter squares multiplier employs at least one sign changer or one added for the production of the difference of n and v which are first separately produced.

This invention makes use of one or more squarers having the transfer property in a novel circuit configuration which eliminates the need for said one sign changer or said one adder and simultaneously does not produce 2 as the difference of two separately produced functions, thus eliminating another of the disadvantages of quarter squares multipliers. For this punpose the invention produces in a first stage from x and y as input signals a plu rality of secondary input signals which represent the sums of u and third signals, said 'secondary signals being fed to a second stage consisting of a transferring squarer adapted to produce from said third signals a signal representing v and simultaneously transferring n to its'output terminal, whereat a signal representingz for the instantaneous values of x and y is thereby produced. I

Function generators having the transfer property and being thus suitable for use in the present invention are described in my copending application, Serial Number 837,617 filed September 2, .1959, entitled Electronic Function Generator with Intenpolating Resistors, now Patent No. 3,106,639. Another type of function generator suitable for use in the present invention consists of simple diode selection circuits comprising a plurality of input terminals, one diode each connected to a corresponding one of said input terminals, said diodes having a common output connection, their polarity being such 3,280,319 Patented Oct. 18, 1966 that either all anodes or all cathodes are connected at said common connection. I

The invention will now be more particularly described in connection with the accompanying drawings in which FIGURE 1 is a block diagram, illustrating theuse of transferring function generators for the production of functions of two variables;

FIGURE 2 is a plot of the x, y plane and of its subdivision into regions which are of interest in some embodiments of this invention;

FIGURE 3 is a schematic diagram of circuits for the production of input voltages for the multiplier of FIG- URE 4; 7

FIGURE 4 is a schematic diagram of one embodiment of the invention using diode selection circuits as basic squarers;

FIGURE 5 is a schematic diagram ofone embodiment of the invention, using piecewise-linear intenpolators as basicsquarers; v I

FIGURE 6 is a schematic diagram of another embodiment of the invention that uses piecewise-linear interpolators as basic squarers; v V,

FIGURE 7 is a schematic diagram of a direct coupled embodiment of the invention; r

' FIGURE 8 is one embodiment of a four-quadrant multiplier of the invention using non-linear interpolating squarers as basic elements;

FIGURE 8A is a plot of the x, y plane relating to the embodiment of FIGURE 8;

FIGURE 9 is a block diagram corresponding to the multiplier of FIGURE 8;

FIGURE 10 is a block diagram of a four-quadrant multiplier of the invention using only one sign-changer;

FIGURE 11 is a block diagram of bilinear function generators;

FIGURE 12 is a schematic diagram of one embodiment of a bilinear multiplier of this invention;

FIGURES 13A and B are scrap circuit diagrams relating to multipliers of the invention; I

Let it be required to produce the function where s and t are both functions of x and y. FIGURE 1 is a block diagram of a f-unctiongenerator producing F. In FIGURE 1, FG FGQ and FG are similar function generators having a plurality of input terminals at 11,12,...;21,22,...;and31,32,...;21,22, and 31, 32, respectively, and possessing the transfer property. FG produces at terminal 1 the function g(t) when

input terminals

11, 12, are fed with voltages e e which are each suitable functions of x and y or suitable constants. FG similarly produces at terminal 2 the function g(t) when the same input voltages are fed to

terminals

21, 22, respectively. FG is similarly adaptable to produce g( t at terminal 3. PG, is a transferring function generator which produces f(s) at output terminal 0 if voltages e e e are applied at

terminals

1, 2 3, respectively.

In order to produce F (x,y) the function generator corresponding to FIGURE 1 proceeds as follows:

FG is fed with voltages:

e =e +e at 11 12= i1+ e2 at 12 etc.

FG is fed with voltages:

e21:ef2+ at 22= r2+ g2 at 22 etc.

which is simultaneously transferred through FG F6 similarly produces at terminal 2 the signal and FG produces at terminal 3 the signal The signals e e e are the input signals to PG, which therefore transfers g(2) to output terminal and simultaneously produces thereat the signal f(s). The total signal thus produced at output terminal 0 is therefore equal to F(x,y), as required. The circuit for the production of e e will be called the first stage of the function generator while FG constitutes its second stage. In the above example FG has three input terminals this being purely illustrative. In general the second stage has two or more input terminals.

In order to apply these considerations to multipliers we write s u and t=v, u and 11 being defined above, and

The function flu) :14 thus requires a squarer for its production and the function g(v)=v requires another squarer which simultaneously changes the sign and produces -v2 from suitable input signals. Another way of applying the scheme of FIGURE 1 to multipliers is by taking s=v and t=u and thus 003)=f( )l-..( l=

In this case the second stage must be a squarer and the first stage a sign reversing squarer. Both schemes are clearly equivalent and it will be sufiicient to describe one of them.

As an example of a multiplier of the invention let it be required to design a multiplier operative for values of x and y within the square area defined in the plot of FIGURE 2 by u and v between 0 and 6d, where d: (50/ 12) volt in this example. A multiplier of this invention which produces an approximation to an output voltage e =(1/ 100 )xy volt where x and y are both in volts will be described in connection with FIGURES 3 and 4 in which FIGURE 3 corresponds to the input unit and FIGURE 4 comprises both stages of the multiplier. In order to understand the operation of the circuit it is best to proceed from output voltage 2 backwards to the input signals.

The second stage of the multiplier comprises terminals T T T diodes D D D connected thereto, respectively, said diodes having a common cathode connection at output terminal T whereat output voltage e is produced. Positive current is withdrawn from terminal T through resistor R connected to negative potential means at E We denote the voltages at terminals T T T by e e 2 The second stage transfers a signal representing -(l/l()0)v and simultaneously produces a signal representing (l/1O0)u Production of (1/l0())u alone would require input signals at u=U. The second stage is a selection circuit thus approximating the required square function by three straight lines in a well known manner. In addition to v at terminal T i=l,2,3; (l/l()0)v must be transferred and the required voltages at the input terminals to the second stage are therefore given by These signals are produced in the first stage of the multiplier, 12;, for example, is produced in a selection circuit comprising three input terminals fed with voltages v v v respectively, one of which is selected in the selection circuit comprising diodes D D12 D which have a common anode connection at terminal T Into T positive current is injected through resistor R which is connected to positive potential means at E+. This circuit for the production of e transfers (l/lOO) (Zulu-d from the input terminals to terminal T simultaneously producing an approximation to -(1/100)v from i= l,2,3; these signals representing the lines tangential to (1/100)v touching this curve at v=V. The required input voltages are therefore Expressing u and v in terms of x and y we have,

The other input voltages are similarly given by The nine input voltages V 'i,j= 1,2,3; are readily produced in linear resistive circuits from voltages x, y, y, 50 volts and --50 volts. FIGURE 3 is a schematic diagram of circuits for the production of v v v The other six input voltages can be produced in similar circuits. V for example, is produced at terminal 6, FIGURE 3, at a low impedance level. Terminal 6 is the cathode connection of cathode follower 5 whose grid connection is at terminal 4. The voltage at terminal 4 was in one example equal to v l.8volt. This voltage is produced from voltage x and a voltage of 50 volt by a combining

circuit comprising resistors

1, 2, 3.

It is of interest to note that the voltages v represent planes tangential to the surface corresponding to e =(1/100)x y at the centres of the nine squares in FIGURE 2. The reason is as follows: In operation, the selection circuits of FIGURE 4 conductively con nect output terminal T with one and only one input terminal at any given instant. e is then equal to the input voltage at the input terminal so selected. The circuit of FIGURE 4 can select only one of nine input voltages, each of which is a linear function of x and y. e does therefore correspond to a piecewise-linear approximation to the required exact product function. The nine linear pieces which are produced are shown in FIGURE 2.

FIGURE 5 is a schematic diagram of another embodiment of this invention. It produces at output terminal (I the voltage where x and y are in volts and E 25 volts, provided that u and v are as defined above and u,v are between and 25 volts. The second stage of the multiplier comprises

input terminals

1, 2 3, equal interpolating resistors r' connected in series with diodes D which have a common cathode connection at output terminal 0 from which constant positive current of strength i is Withdrawn. The principle of operation of interpolating function generators as used in this stage is explained in said copending application. In this stage of the multiplier voltage (1/E)v is transferred from

terminals

1, 2, 3 to terminal 0. The second stage is operative as a half squarer for the production of (l/E)u at 0 from suitable input voltages. The voltages at 1, 2 3 are respectively. Thus, voltage (l/E) (v +i'r, being equally applied to all input terminals of the second stage, is transferred, whereas voltages (l/E) (2du'-d (1/E)(l0dud (1/E)(l8dla8ld produce at 0 a voltage corresponding to (1/E)u -ir'. In this example d=E/=2.5 volts, and the produced function (l/E)u consists of an approximation curve comprising five linear segments.

A A A are sign changers having a gain A=2 each. They are fed from terminals T T T which are at voltages e' 2' 2' respectively, where e' is produced in thi example by a first stage comprising another interpolating function generator. Its

input terminals

11, 12, 13 are fed with voltages e e e respectively. Each input terminal is connected to an interpolating resistor of resistance r in series with diode D. These diodes have a common cathode connection at terminal T from which positive current i is withdrawn. Voltage (1/2E) (2du+d )i'r/2+ir is simultaneously applied to all three input terminals and is thereby transferred to terminal T Simultaneously the voltages (1/2E) (2a'vd (l/2E)(1Odv25d (1/2E)(18dv 81d are additively applied to

terminals

11, 12, 13, thereby producing an approximation to (l/ZE) v ir volt at terminal T The total voltage produced at terminal T is therefore equal to (l/2E) (2du+d ir/ 2 l-r'r-f-(l/ZE) v ir which is equal to 2' as required. The input voltages e e e at

terminals

11, 12, 13, respectively, are thus equal to In this example ir=ir'/2=1 volt and therefore, expressing u,v in terms of x and y,

e =(d/E) (x) =(1/10) (x) volt e (d/E) (3x+2y 12d) =(1/10)(3x+2y-30) volt e (d/E) (5x+4y40d) =(1/lO)(-5x+4yl00) volt Voltages e e' are produced in similar interpolating function generating circuits from input voltages at terminals 21 22, 23, 31, 32, 33, respectively. Any ine of the nine input voltages e i,j=1, 2, 3; is readily produced from x, y and constant voltages in circuits similar to those corresponding toFIGURE 3.

In one example of the multiplier of FIGURE 5, i=i"=l ma.; r=1 kilohm; 1":2 kilohms. Aplifiers A A A draw negligible current from their input terminals and have a low output impedance. Output terminal 0 must not be substantially loaded, a condition which can be achieved by connecting an adder having a high input resistance to terminal it and connecting any load to the output terminal thereof. These conditions ensure that substantially all currents i, i supplied by the current generators supplying currents i and i' flow into the diodes adjacent to said common connections.

A still further embodiment of the invention will be described in connection with FIGURE 6 which is a schemtatic diagram of a multiplier producing at output terminal 0 the voltage e =(1/E)xy where E=56 volts provided that u, v are between 0 and 25 volts. u and v are as defined above and voltage d is 25/6=4.17 volts, in this example. The operation of this circuit is best understood by following output signal formation from output terminal 0 to the input terminals of the multiplier. 41 is a triode connected as a cathode follower and producing the voltage e at terminal 0 at .a low impedance level without loading its input terminal T 36, 37 are the anode and cathode resistor of said triode connected to positive and negative voltage means at +B and respectively. The voltage at terminal T is denoted by e' It is equal in this example to where E'=55 volts. The second stage of the multiplier comprises

terminals

1 and 2, two resistive interpolating branches connected to

terminals

1, 2, respectively, and having a common output connection at terminal T each of said branches comprising a series combination of a linear resistor and a diode D, the resistance of the combination being denoted by r. The polarity of the diode is such that their cathodes are connected to terminal T Constant negative current in supplied to terminal T by triode 40 whose anode is connected to said terminal. 35 is the cathode resistor of said triode and the series com bination of

resistors

32, 33, 34 provides the required grid voltage to triode 40. For this purpose the grid of triode 40 is connected to the adjustable contact of resistor 33. Resistor 32 is connected to ground and

resistors

34 and 35 are connected to negative potential means at Said adjustable contact permits adjustment of the current supplied by said triode. Denoting the current thus supplied by i, which is a negative quantity in this example, the voltages e and 2 at

terminals

1, 2, respectively, are given by Thereby, voltage (1/E')(v )1.8i'r is transferred to terminal T whereas voltages (1/E)(2udd and (l/E')(l0ua'--25d produce thereat an approximation to (l/E)u +i'r. Thus the total volt-age produced at terminal T is approximately equal to 2' as required.

38 and 39 are triodes connected as cathode followers and substantially transferring the voltages at terminals T T to

terminals

1, 2, respectively. Considering the gain of the cathode followers and their bias voltages the voltages e' and e' at terminals T and T are, respectively,

2' e' are produced in the first stage of the multiplier from voltages x, y, y, V, and V. Considering, for example, production of E' this is produced in a transferring interpolating function generator comprising first and second input terminals fed with voltages e e respectively, two similar interpolating resistive branches connected to said terminals each having resistance r and comprising a diode D, where said diodes have a common anode connection at terminal T substantially constant positive current i being applied to said common connection through resistor R connected to constant potential 8 stages thereof, this is by no means an essential feature of the invention as will now be shown in connection means at Taking ir=i'r', the expressions for e e with FIGURE 7 Which is a schematic diagram of a direct are coupled embodiment of the invention. The multiplier 811: E) (zud dz zvd+dz) goriesponldirzg to 7 pll'fductzsittjgttputlzermilitgl e =(1/E")(2udd l0vd+25d )-3.60 t e d" W W the purpose it uses first and second stages each comprisor, in terms of x and y, ing transferring function generators embodying resistive =(2d/E") 3 60 interpolation. 90 is a cathode follower substantially =(2d/E")(3 2 +12d) 3,60 transferring the voltage at grid terminal T to output tervokage (1/E-)(2ud d2) 3.60,hang equally applied minal T which is also designated 0. 87, 88 are the to both input terminals, is transferred to terminal T anofie cathod? 3513mm of mode respacfwely' While Voltages (1/E)( 2vd+d2) and 89: 1s a triode having its anode connected to term nal T 2 withdrawing therefrom a constant posltive current 1 83 I E )(10vd+25d through 85 are resistors supplying the required grid volt- P Oduce thefeat an approximation m age to triode 89 and 86 is its cathode resistor. Said triode (1/E")v +ir=(1/E")v -i'r' operates as a constant current source in a Well-known The total voltage thus produced at terminal T is equal manner- Adlllstment of ifollentlometer 84 @efmlts l to as required. merit of current strength 1 A similar first stage function generator produces volt- The voltage at termmal T 15 equal to age e at terminal T from e and e as input voltages, (1 1 3 volts Where- Where E=57.5 volts, provided that u, v which are as 21 -ldefined above, are confined to the interval of 0 to 22=( 25 volts. The second stage of the multiplier com-prises ter- In FIGURE 6 the circuit comprising resistors 11 minals 11:, 2, 3 and three series combinations of diodes through 1 f d Voltages x and and connected to D and linear interpolating reslstors of resistance r each, terminal T which is the cathode connection of diode Where kllohlPs- Said f have anodes D, is equivalent to a resistor of resistance r fed by voltconnected to F PP termmals of sald sficond age em and connected to terminal TIP Thus the stage, while said interpolating TESIStOIS hBVE a common sistance seen from T looking into said resistors, when connec'flon at The Voltages at tarmmals the input terminals are connected to ground, is equal to r, resmctlvely and the resistors are so chosen that the required linear e =(l/-E')(v +2dud )-1.8+i'r' combination of x and a constant voltage as given in the e =(l/E')(v +10du25d )l.8+i'r' expression for a is produced at T Production of e (l/E')(v l8du8ld )1.8+ir' 12, 21, 22 at terminals 12, 21, 22 proceeds in a where, in this example, i'=0.094 mat. and r'=l0.0 killlal mannerohms. The production of voltage e at terminal T will In the above examples, kilOhms; d 'be quite clear from the previous examples. Voltages e 1= g 2= megohms; e e are produced in similar resistive interpolating func- Voltage at 200 Volts; voltage at Volts; Volttion generators from voltages x, y, 1, V and -V, reag at "In Volts; Voltage Volts- Resistors ceived by a plurality of input terminals. All interpolat- 25 are adjustable and 33 is a potentiometering resistances in said first stage are equal to r=2.61 kil- Sistame Values, in kilOhm, are listed below! ohms. In general, in a direct coupled multiplier the inn 100; 12 100 (max); 13, 14, 200; I15 333; 16 terpolating resistance of the second stage must be made 50.0; 17, 100 (max.); 18, 150; 19, 105; 20, 3 21 several times as much as that of the first stage in order 22 (max); 23, 24, 201); 25 (max); not to introduce large errors into the produced

output

26, 0 27 100; 28 29 41; 30 051; 31 32, function. The reason is that the second stage withdraws 100; 33 50,; 34 200; 35 1200; 3 051; 37 41 All variable CLlI'I'flHlI from the out-put terminals Of the first modes of type A157. 50 stage and this current must therefore be not more than a fraction of the current i flowing into the first stage. The ad ustment of the multiplier proceeds as follows: In this example and a ratio f 4, approxi- (1) Adjust potentiometer 33 for an anode current of mately, therefore corresponds to a ratio of i/i which is 0.168 ma. in triode 40; equally about 4. Such a ratio of current yields sufficiently (2) With x=0.00 volt and 32:8 volts, adjust resistor 12 accurate performance. The computation of the resistive for e =0.00 volt; input networks proceeds in a manner similar to that (3) With x=0.00 volt and 3 :43 volts, adjust resistor 25 explained-in connection with FIGURE 6.

for e =0.00 volt; In one example the following components and values (4) With x=l6.7 volts and y=25.0 volts adjust reare used: sistor 17 for e =-7.45 volts; 8Q, fit double triode type 12AT7 g g fgig gig and volts adjust reslstor Voltage at +B, 200 volts, voltage at 300 volts; voltage at -300 volts. V=5O volts. Resistances as listed While the above examples of multipliers comprise irnbelow, where row A is the resistor and B is the correpedance converting means between the first and second sponding resistance in kilohms.

A 51 52 53 54 55 56 57 5s 59 6O 61 62 A" 70 71 7s 79 80 s1 s2 s3 s4 s5 86 87 88 A a: 11 ea While the above examples of the invention are operative in the quadrant of the plane of variables defined by the given limitations on u and v, this limitation is by no means inherent in the invention and is to be taken purely as an illustration. Similar embodiments are operative as four quadrant multipliers, for example. Moreover, it will be appreciated that the use of linear interpolating resistors in the examples is given by way of illustration and example. In any of the above embodiments the linear interpolating resistors can be replaced by suitable nonlinear resistors, resulting in a further increase of accuracy, as described in said copending application.

As a further example of the invention the multiplier corresponding to the schematic diagram of FIGURE 8 will now be described. This multiplier provides four quadrant multiplication within the shaded area of the plane of variables shown in the plot of FIGURE 8A and limited by x,y=i5 volts.

The second stage of the multiplier has

input terminals

1 and 2 and output terminal 0 whereat the voltage is produced at a low impedance level. This second stage comprises a nonlinear interpolating squarer which, when fed at 1 and 2 with voltages a and u produces an output voltage (1/10)u 7.5 volts in accordance with said copending application. Two similar nonlinear interpolating resistors each of resistance r when traversed by current i, where i is the positive current withdrawn from their common connection at terminal T by transistor 106, are connected to

terminals

1 and 2, respectively. In this example said nonlinear resistors comprise series combinations of fixed nonlinear resistors and adjustable linear resistors. NPN transistor 106 is used as a constant current source in a standard connection. Zener diode 105 fixes the base potential of said transistor. Emitter resistor 109 is adjustable, permitting adjustment of said current i, whereas resistor 108 is a temperature dependent resistor having a negative temperature coeificient. With increasing temperature, the resistance of resistor 108 decreases and current i therefore increases. This increase in current compensates for temperature drift in the squarer. In particular, resistance r decreases when temperature increases thereby raising the potential of terminal T An increase in i, on the other hand, lowers the potential at terminal T The use of a suitable temperature dependent resistor at 108 thus permits compensation of the two opposing effects. 107 is a PNP transistor used as an emitter follower for the provision of the output signal at 0 at a low impedance level without substantially loading terminal T The voltages at

terminals

1 and 2 are in this example where u and v are again as defined above. Voltage (l/1O)v +7.5 is thereby transferred to terminal 0 while u and u produce thereat the voltage (l/ l0)u 7.5. The total output voltage at terminal 0 is therefore equal to s as required.

e and e are produced in similar interpolating function generators, in the first stage of the multiplier. Thus the device having

input terminals

11 and 12 is a squarer producing at terminal 1 the voltage (1/10)v +7.5 volts when

terminals

11 and 12 are at potentials v and v, respectively. This first stage squarer comprises interpolating resistors r connected to

terminals

11 and 12 having a common output connection at T PNP transistor 104 operating as a constant current source its base potential being fixed by Zener diode 101 and its current being adjustable by resistor 103. Resistor 102 is a negative temperature coefficient resistor for the compensation of temperature drift. PNP transistor 104 functions as an impedance converter, in an emitter follower connection. Positive current i is supplied to terminal T by transistor 100. The voltages at 11 and 12 are, respectively,

Voltage u is thereby transferred to terminal 1 Whereas voltages v and v produce thereat the voltage The total voltage produced at terminal 1 is thus equal to 6 as required.

A similar squarer produces at terminal 2 the voltage e from input voltages at

terminals

21 and 22, respectively.

This example of a multiplier of the invention thus requires voltages x, x, y, and y as input signals. Any one of the nonlinear resistors has a characteristic given by where V is the voltage drop in volts and I is the current in amperes. The adjustable resistors in series with said nonlinear resistors have a maximum resistance of 2 kilohms. In each of the two first stage squarers the current supplied to the common connection of the input branches is equal to 0.9 ma., approximately, and the current supplied to the common connection T of the two interpolating branches of the second stage squarer is equal to 0.9 ma., approximately.

A block diagram of the multiplier of FIGURE 8 is given in FIGURE 9 in which each first stage squarer is Ii)der]13tified by A and said second stage squarer is identified FIGURE 10 is a block diagram of another four quadrant multiplier of the invention which requires only signals x and y as input signals and comprises only two B units, one A unit and one sign changer. The signal at 1 is produced as before. The first stage B unit is connected to

terminals

11 and 12 and thus receives input signals x and y and produces therefrom at its output terminal 2 the voltage (1/l0)v 7.5+u=e Sign changer SC accepts the signal at terminal 2' and produces therefrom at its output terminal 2 the voltage e Second stage squarer B produces from e and 2 at

terminals

1 and 2, respectively, the required output signal at terminal 0, as before.

FIGURE 11 is a block diagram of a multiplier in which the first stage comprises only one squarer, FG for the production of one of the input voltages of the second stage, e in this example, while all other second stages input voltages, e e are produced from 2 x, and y in the linear'network N. In any one of the examples of multipliers of the invention recited above, the difference of any two signals e e which are input signals to the second stage, is a linear function of x and y. Thus, having produced one of said signals, all the other said signals are readily produced in a linear network. Such a multiplier will be called bilinear.

A specific example of a bilinear multiplier of the invention will be described in connection with FIGURE 12 which is a schematic diagram thereof. Input voltages x and y are accepted by

input terminals

11 and 12, respectively, of a first stage squarer producing therefrom at terminal 1 the voltage where E and E are constant voltages and u, v are as defined above. Sign changing adder 115 is fed with voltages x and y and produces at its output terminal 114 the voltage (x+y). 110 and 111 are equal resistors connected between terminals 1 and 114 and produced at their common connection at terminal 2' the voltage Resistors 112 and 113 have equal resistance and serve as a potential dividing network producing at terminal 1' the voltage e /2=e' Expressing e' in terms of u and v We have,

A second stage transfers -(l/2E)v +E/2 to output terminal and produces from u/ 2 and u/ 2 the additive output voltage (U 2E )u --E/ 2, thus yielding a total output voltage equal to The examples of FIGURES 8 through 12 relate to function generators in which the second stage comprises only two interpolating branches. This is given by way of example and illustration only. Any plurality of such branches can be used in the invention. Similarly, the first stage may comprise more than two interpolating branches.

If greater accuracy is required in a multiplier of the invention than can be achieved with two interpolating branches it is necessary to use three or more thereof. As an example for the use of three branches in the second stage of the multiplier of FIGURE 8, the embodiment including the device of FIGURE 13A will be described. This is a scrap schematic diagram of the structure required to replace the input circuit, between

terminals

1, 2 and terminal T in FIGURE 8. There are now three input terminals, 1, 2, 3, each connected to terminal T through the series combination of a nonlinear resistor of resistance r and

diodes

116, 117, 118, respectively. The cathodes of said diodes have a common connection at T The current source connected to T as well as the output impedance converting stage are as in FIGURE 8. The characteristics of r are likewise identical with those in the example of FIGURE 8. Diode 117 is optional.

If

terminals

1, 2, 3 are fed with voltages u, 16 volts, +u, respectively, the produced output voltage at terminal 0 is equal to (1/10)u for it between -20 and +20 volts. In this example of the muti-plier the following voltages are received by

terminals

1, 2, 3:

and the output voltage e =(1/ l0)xy is thereby produced at output terminal 0, provided that x and y are between -10 and +10 volts.

The voltages e e 2 are produced in a first stage of the multiplier and it will be quite clear from the above examples how this can be done in the invention.

The circuit corresponding to FIGURE 13A can be replaced by that of FIGURE 13B which, in operation, is completely equivalent to it. Diodes 114 and 115 accept voltages 2 and a respectively, and select at terminal 1' the larger thereof. The diodes have a common cathode connection at terminal 1' to which a negative current is supplied through a resistor connected to negative potential means at We have, therefore at terminals 1' and 2 respectively. Input voltage la] and 10 volts produce in the half squarer which they feed the voltage (1/10)u the additional voltage -(1/10)v being simultaneously transferred to the output terminal, so that, again, the voltage at terminal 0 is equal to (1/ l0)xy.

Although this invention has been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the scope of this invention being limited only by the terms of the appended claims.

What I claim is:

1. An electronic analog multiplier for producing an output signal having a magnitude substantially proportional to the product of the magnitudes of first and second input signals, comprising a plurality of first means for receiving said first and second input signals, second means responsive to said input signals for generating therefrom a plurality of third signals substantially equal to respective ones of a plurality of linear functions of the sum of said input signals and the square of their difference; a plurality of third means responsive to respective ones of said third signals and having a common output connection, for producing thereat a fourth signal substantially equal to a linear function of said square signal and the square of the sum of said input signals, said fourth signal being said output signal; wherein said third means comprise unilaterally conductive means, fourth means connected to said common connection for supplying a current to at least one of said conductive means at any given instant.

2. The multiplier as recited in claim 1, wherein said third means include interpolating resistor means having resistive values to cause at least two of them to conduct simultaneously for suitable values of said input signals.

3. The multiplier as recited in claim 2, wherein said fourth means is adapted to cause the magnitude of the current flowing through said common connection into said plurality of third means to be substantially independent of the magnitudes of said input signals.

4. The multiplier as recited in claim 3, wherein said fourth means includes means responsive to temperature for causing the current supplied by said fourth means to be temperature dependent for the compensation of temperature drift.

5. An electronic analog multiplier for producing an output signal having a magnitude substantially proportional to the product of the magnitudes of first and second input signals, comprising a plurality of first means for receiving said first and second input signals, second means responsive to said input signals for generating therefrom a plurality of third signals substantially equal to respective ones of a plurality of linear functions of the sum of said input signals and the square of their difference; a plurality of third means responsive to respective ones of said third signals and having a common output connection, for producing thereat a fourth signal substantially equal to a linear function of said square signal and the square of the sum of said input signals, said fourth signal being said output signal; wherein said third means comprise bilaterally conductive nonlinear interpolating means, fourth means connected to said common connection for supplying a current to at least one of said conductive means at any given instant, said third means having resistive values to cause at least two of them to conduct simultaneously for suitable values of said input signals.

6. The multiplier as recited in claim 5, wherein said fourth means is adapted to cause the magnitude of the current flowing through said common connection into said plurality of third means to be substantially independent of the magnitudes of said input signals.

7. The multiplier as recited in claim 6, wherein said fourth means includes means responsive to temperature for causing the current supplied by said fourth means to be temperature dependent for the compensation of temperature drift.

8. An electronic analog multiplier for producing an output signal having a magnitude substantially proportional to the product to the magnitudes of first and second input signals, comprising a plurality of first means for receiving said first and second input signals, second means responsive to said input signals for generating therefrom a plurality of third signals substantially equal to respective ones of a plurality of linear functions of the sum of said input signals and the square of their difference; a plurality of third means responsive to respective ones of said third signals and having a common output connection, for producing thereat a fourth signal substantially equal to a linear function of said square signal and the square of the sum of said input signals, said fourth signal being said output signal; wherein said second means includes a plurality of unilaterally conductive means responsive to said input signals having a common output connection for producing thereat one of said third signals; fifth means connected to said common connection for supplying a current to at least one of said conductive means at any given instant.

9. The multiplier as recited in claim 8, wherein said conductive means include interpolating resistor means having resistive values to cause at least two of them to conduct simultaneously for suitable values of said input signals.

10. A bilinear multiplier comprising the device as recited in claim 8, wherein said second means includes linear means responsive to said third signal and to said input signals for the production of at least one other signal of said plurality of third signals.

11. A fourth quadrant multiplier comprising the device as recited in claim *8, wherein said second means comprises a second plurality of unilaterally conductive means having a common output connection, for producing thereat a signal having a magnitude substantially equal to the inverse of the magnitude of a second of said third signals; sign changing means connected thereto for inverting the sign of said inverse signal.

12. An electronic analog multiplier for producing an output signal having a magnitude substantially proportional to the product of the magnitudes of first and second input signals, comprising a plurality of first means for receiving said first and second input signals, second means responsive to said input signals for generating therefrom a plurality of third signals substantially equal to respective ones of a plurality of linear functions of the sum of said input signals and the square of their difference; a plurality of third means responsive to respective ones of said third signals and having a common output connection, for producing thereat a fourth signal substantially equal to a linear function of said square signal and the square of the sum of said input signals, said fourth signal being said output signal; wherein said second means includes first and second pluralities of unilaterally conductive means responsive to said input signals each having a common out-put connection for producing thereat respective third signals; first and second fifth means connected to respective ones of said output connections each for supplying a current to at least one conductive means of said respective plurality of conductive means at any given instant.

13. A four quadrant multiplier comprising the device as recited in claim 12; first and second sixth means for receiving first and second inverse input signals having magnitudes substantially equal to the negative of the magnitudes of said first and second input signals, respectively; wherein said first and second pluralities of unilateral means are connected to respective ones of said first and second first and sixth means respectively.

14. An electronic analog multiplier for producing an output signal having a magnitude substantially proportional to the product of the magnitudes of first and second input signals, comprising a plurality of first means for receiving said first and second input signals, second means responsive to said input signals for generating therefrom a plurality of third signals substantially equal to respective ones of a plurality of linear functions of the sum of said input signals and the square of their difference; a plurality of third means responsive to respective ones of said third signals and having a common output connection, for producing thereat a fourth signal substantially equal to a linear function of said square signal and the square of the sum of said input signals, said fourth signal being said output signal; wherein said second means comprises a plurality of bilaterally conductive nonlinear interpolating means responsive to said input signals having a common output connection for producing thereat one of said third signals; fifth means connected to said common connection for supplying a current to at least one of said conductive means at any given instant; said conductive means having resistive values to cause at least two of them to conduct simultaneously for suitable values of said input signals.

15. A bilinear multiplier comprising the device as recited in claim 14, wherein said second means includes linear means responsive to said third signal and to said input signals for the production of at least one other signal of said plurality of third signals.

16. A four quadrant multiplier comprising the device as recited in claim 14, wherein said second means comprises a second plurality of bilaterally conductive nonlinear means having a common output connection, for producing thereat a signal having a magnitude substantially equal to the inverse of the magnitude of a second of said third signals; sign changing means connected thereto for inverting the sign of said inverse signal.

17. An electronic analog multiplier for producing an output signal having a magnitude substantially proportional to the product of the magnitudes of first and second input signals, comprising a plurality of first means for receiving said first and second input signals, second means responsive to said input signals for generating therefrom a plurality of third signals substantially equal to respective ones of a plurality of linear functions of the sum of said input signals and the square of their difference; a plurality of third means responsive to respective ones of said third signals and having a common output connection, for producing thereat a fourth signal substantially equal to a linear function of said square signal and the square of the sum of said input signals, said fourth signal being said output signal; wherein said second means includes first and second pluralities of bilaterally conductive nonlinear interpolating means responsive to said input signals each having a common output connection for producing thereat respective third signals, first and sec-ond fifth means connected to respective ones 15 of said output connections each for supplying a current to at least one conductive means of said respective plurality of conductive means at any given instant.

18. A four quadrant multiplier comprising the device as recited in claim 17; first and second sixth means for receiving first and second inverse input signals having magnitudes substantially equal to the negative of the magnitudes of said first and second input signals, respectively; wherein said first and second pluralities of conductive means are connected to respective ones of said first and second first and sixth means respectively.

References Cited by the Examiner UNITED STATES PATENTS Takeo Miura et al. 235-494 MALCOLM A. IMO-RRISON, Primary Examiner.

0 K. W. DOBYNS, Assistant Examiner.