US20260011695A1 - Isolation chip and signal transmission device - Google Patents

Isolation chip and signal transmission device

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Publication number
US20260011695A1
US20260011695A1 US19/324,252 US202519324252A US2026011695A1 US 20260011695 A1 US20260011695 A1 US 20260011695A1 US 202519324252 A US202519324252 A US 202519324252A US 2026011695 A1 US2026011695 A1 US 2026011695A1
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United States
Prior art keywords
coil
circuit
isolation chip
chip
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
US19/324,252
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English (en)
Inventor
Junichi SEKITO
Koji Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
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Rohm Co Ltd
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Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Publication of US20260011695A1 publication Critical patent/US20260011695A1/en
Pending legal-status Critical Current

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    • H01L25/072—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type
    • H01L23/49575—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/20—Inductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/811—Multiple chips on leadframes

Definitions

  • the present disclosure relates to an isolation chip and a signal transmission device.
  • a conventional signal transmission device is used for various applications such as a power supply device and a motor drive device and transmits pulse signals while electrically isolating the input and the output.
  • a known example of a signal transmission device is an isolated gate driver that applies a gate voltage to the gate of a switching element such as a transistor.
  • JP2018-78169A describes a known example of an isolation chip used for such a gate driver.
  • the isolation chip includes a first coil and a second coil arranged in an element insulation layer facing each other in the thickness-wise direction of the element insulation layer.
  • FIG. 1 is a schematic circuit diagram showing the configuration of a signal transmission device in accordance with an embodiment.
  • FIG. 2 is a schematic plan view showing the configuration of the signal transmission device shown in FIG. 1 .
  • FIG. 3 is a schematic cross-sectional view showing the configuration of the signal transmission device shown in FIG. 2 .
  • FIG. 4 is a schematic perspective view of the isolation chip shown in FIG. 2 .
  • FIG. 5 is a schematic plan view of the isolation chip shown in FIG. 4 .
  • FIG. 6 is an enlarged schematic plan view showing a portion of the isolation chip shown in FIG. 5 .
  • FIG. 7 is a schematic plan view of first coils of the isolation chip shown in FIG. 5 .
  • FIG. 8 is a schematic plan view of second coils of the isolation chip shown in FIG. 5 .
  • FIG. 9 is a schematic cross-sectional view of the isolation chip taken along line 9 - 9 in FIG. 5 .
  • FIG. 10 is a schematic cross-sectional view of the isolation chip taken along line 10 - 10 in FIG. 5 .
  • FIG. 11 is an enlarged schematic plan view showing a portion of the isolation chip shown in FIG. 5 .
  • FIG. 12 is a schematic cross-sectional view of the isolation chip taken along line 12 - 12 in FIG. 11 .
  • FIG. 13 is a schematic plan view showing the configuration of a first circuit chip shown in FIG. 2 .
  • FIG. 14 is a block diagram showing an exemplary configuration of a reception circuit in the signal transmission device shown in FIG. 1 .
  • FIG. 15 is a block diagram showing an exemplary configuration of the reception circuit shown in FIG. 14 .
  • FIG. 16 is a circuit diagram showing an exemplary configuration of a nonlinear amplifier and an envelope detection circuit shown in FIG. 15 .
  • FIG. 17 is a schematic diagram used to illustrate inspection of the isolation chip shown in FIG. 5 .
  • FIG. 18 is an enlarged schematic plan view showing a portion of an isolation chip in a modified example.
  • FIG. 19 is a schematic enlarged cross-sectional view showing a portion of the isolation chip taken along line 19 - 19 in FIG. 18 .
  • FIG. 20 is an enlarged schematic plan view showing a portion of an isolation chip in a modified example.
  • FIG. 21 is a schematic enlarged cross-sectional view showing a portion of the isolation chip taken along line 21 - 21 in FIG. 20 .
  • FIG. 22 is an enlarged schematic plan view showing a portion of an isolation chip in a modified example.
  • FIG. 23 is a schematic enlarged cross-sectional view showing a portion of the isolation chip taken along line 23 - 23 in FIG. 22 .
  • FIG. 24 is an enlarged schematic plan view showing a portion of an isolation chip in a modified example.
  • FIG. 25 is a schematic enlarged cross-sectional view showing a portion of the isolation chip taken along line 25 - 25 in FIG. 24 .
  • FIG. 26 is an enlarged schematic plan view showing a portion of an isolation chip in a modified example.
  • FIG. 27 is a schematic enlarged cross-sectional view showing a portion of the isolation chip taken along line 27 - 27 in FIG. 26 .
  • FIG. 28 is an enlarged schematic plan view showing a portion of an isolation chip in a modified example.
  • FIG. 29 is an enlarged schematic plan view showing a portion of an isolation chip in a modified example.
  • FIG. 30 is an enlarged schematic plan view showing a portion of an isolation chip in a modified example.
  • FIG. 31 is an enlarged schematic plan view showing a portion of an isolation chip in a modified example.
  • FIG. 32 is an enlarged schematic plan view showing a portion of an isolation chip in a modified example.
  • FIG. 33 is a schematic cross-sectional view of an isolation chip in a modified example.
  • FIG. 34 is a block diagram showing a reception circuit of a signal transmission device in a modified example.
  • FIG. 35 is a block diagram showing an exemplary configuration of the reception circuit shown in FIG. 34 .
  • FIG. 36 is a circuit diagram showing an exemplary configuration of an envelope detection circuit and an addition circuit shown in FIG. 35 .
  • FIG. 37 is a waveform diagram showing actions of a signal transmission device shown in FIG. 34 .
  • FIG. 38 is a circuit diagram showing an exemplary configuration of a high-pass filter and a DC bias circuit.
  • FIG. 39 is a circuit diagram showing a circuit equivalent to a high-pass filter.
  • FIG. 40 is a diagram showing the characteristics of output impedance of a buffer.
  • FIG. 41 is a waveform diagram showing an adding process of an addition circuit in a modified example.
  • FIG. 42 is a schematic plan view showing the configuration of a signal transmission device in a modified example.
  • FIG. 43 is a schematic circuit diagram showing the configuration of a signal transmission device in a modified example.
  • FIG. 44 is a schematic plan view showing the configuration of the signal transmission device shown in FIG. 43 .
  • FIG. 45 is a schematic plan view showing the configuration of a signal transmission device in a modified example.
  • FIG. 46 is a schematic plan view showing the configuration of a signal transmission device in a modified example.
  • FIG. 47 is a schematic plan view showing the configuration of a signal transmission device in a modified example.
  • phrases “at least one of” as used in this disclosure means “one or more” of a desired choice.
  • the phrase “at least one of” as used in this disclosure means “only one of the two choices” or “both of the two choices” in a case where the number of choices is two.
  • the phrase “at least one of” as used in this description means “only one single option” or “any combination of two or more options” if the number of options is three or more.
  • FIG. 1 is a schematic diagram showing a circuit configuration of the signal transmission device 100 .
  • FIG. 2 is a schematic diagram showing an example of the internal configuration (planar structure) of the signal transmission device 100 .
  • FIG. 3 is a schematic diagram showing an example of the internal configuration (cross-sectional structure) of the signal transmission device 100 . To simplify illustration, FIG. 3 does not show hatching lines.
  • the signal transmission device 100 includes a first circuit chip 60 , a second circuit chip 70 , and an isolation chip 80 .
  • the isolation chip 80 is connected between the first circuit chip 60 and the second circuit chip 70 .
  • the isolation chip 80 electrically isolates the first circuit chip 60 and the second circuit chip 70 .
  • the first circuit chip 60 includes a first circuit 10 configured to be activated by a first voltage V 1 .
  • the first circuit 10 includes a transmission circuit 11 and a reception circuit 12 .
  • the second circuit chip 70 includes a second circuit 20 configured to be activated by a second voltage V 2 .
  • the second circuit 20 includes a reception circuit 21 and a transmission circuit 22 .
  • the first voltage V 1 may be equal to or different from the second voltage V 2 .
  • the second voltage V 2 is equal to the first voltage V 1 .
  • the first circuit chip 60 has the same configuration as the second circuit chip 70 .
  • the first circuit chip 60 and the second circuit chip 70 may each be referred to as a controller chip.
  • the signal transmission device 100 may be referred to as a digital isolator.
  • the isolation chip 80 includes multiple transformers 40 .
  • the multiple transformers 40 include a first transformer 40 A and a second transformer 40 B that are connected to the transmission circuit 11 of the first circuit 10 , and a third transformer 40 A and a fourth transformer 40 B connected to the reception circuit 12 of the first circuit 10 .
  • the first transformer 40 A and the second transformer 40 B are electrically connected between the transmission circuit 11 of the first circuit chip 60 and the reception circuit 21 of the second circuit chip 70 .
  • the third transformer 40 A and the fourth transformer 40 B are electrically connected between the reception circuit 12 of the first circuit chip 60 and the transmission circuit 22 of the second circuit chip 70 .
  • the first to fourth transformers 40 A and 40 B each include a first coil 41 and a second coil 42 .
  • the first coils 41 of the first transformer 40 A and the second transformer 40 B are electrically connected to the transmission circuit 11 of the first circuit chip 60 .
  • the second coils 42 of the first transformer 40 A and the second transformer 40 B are electrically connected to the reception circuit 21 of the second circuit chip 70 .
  • the first coils 41 of the third transformer 40 A and the fourth transformer 40 B are electrically connected to the reception circuit 12 of the first circuit chip 60 .
  • the second coils 42 of the third transformer 40 A and the fourth transformer 40 B are electrically connected to the transmission circuit 22 of the second circuit chip 70 .
  • the transmission circuit 11 of the first circuit chip 60 applies pulsed drive to the first coil 41 of at least one of the first transformer 40 A and the second transformer 40 B.
  • the reception circuit 21 of the second circuit chip 70 outputs an output signal.
  • the transmission circuit 22 of the second circuit chip 70 applies pulsed drive to the second coil 42 of at least one of the third transformer 40 A and the fourth transformer 40 B.
  • the reception circuit 12 of the first circuit chip 60 outputs an output signal.
  • FIG. 2 shows an example of the internal structure of the signal transmission device 100 .
  • the circuit configuration of the signal transmission device 100 is simplified.
  • the number of external terminals of the signal transmission device 100 shown in FIG. 2 is greater than the number of external terminals of the signal transmission device 100 shown in FIG. 1 .
  • the external terminals of the signal transmission device 100 include a connection terminal configured to connect an electronic component disposed outside the signal transmission device 100 , and a power supply terminal configured to supply a power voltage to the first circuit chip 60 and the second circuit chip 70 of the signal transmission device 100 .
  • the external terminals may include a terminal configured not to be connected to an external component.
  • FIG. 3 is an example of a cross-sectional view showing the internal configuration of the signal transmission device 100 .
  • FIG. 3 is a simplified cross-sectional view showing the internal configuration of the signal transmission device 100 .
  • the cross-sectional structure of each of the chips 60 , 70 , and 80 is simplified in the drawing.
  • the cross-sectional structure of the isolation chip 80 shown in FIG. 3 differs from the cross-sectional structure of the isolation chip 80 described below.
  • the signal transmission device 100 is a semiconductor device in which the first circuit chip 60 , the second circuit chip 70 , and the isolation chip 80 are arranged in two packages.
  • the package type of the signal transmission device 100 is small outline (SO).
  • the signal transmission device 100 is a small outline package (SOP).
  • the package type of the signal transmission device 100 may be changed in any manner.
  • the package type is not limited to SOP and may be a quad for non lead package (QFN), a dual flat package (DFP), a dual inline package (DIP), a quad flat package (QFP), a single inline package (SIP), a small outline j-leaded package (SOJ), or other similar package structures.
  • the first circuit chip 60 is mounted on a first support member 210 .
  • the second circuit chip 70 is mounted on a second support member 220 .
  • the isolation chip 80 is mounted on the first support member 210 .
  • An encapsulation resin 230 encapsulates a portion of the first support member 210 , a portion of the second support member 220 , and the chips 60 , 70 , and 80 .
  • the encapsulation resin 230 is indicated by double-dashed lines to illustrate the internal structure of the signal transmission device 100 .
  • the encapsulation resin 230 is formed from an electrical insulating material.
  • An example of the resin includes an epoxy resin.
  • the resin may be colored black.
  • the encapsulation resin 230 has the form of a rectangular shape having a thickness-wise direction aligned with a Z-direction.
  • the encapsulation resin 230 includes four resin side surfaces 231 to 234 . More specifically, the resin side surfaces 231 and 232 are two end surfaces of the encapsulation resin 230 in an X-direction.
  • the resin side surfaces 233 and 234 are two end surfaces of the encapsulation resin 230 in a Y-direction. The X-direction and the Y-direction are orthogonal to the Z-direction.
  • the X-direction and the Y-direction are orthogonal to each other.
  • the X-direction corresponds to a “first direction.”
  • the Y-direction corresponds to a “second direction.”
  • a plan view means a view in the Z-direction.
  • the first support member 210 and the second support member 220 are each electrically conductive.
  • the first support member 210 and the second support member 220 are formed of a material including copper (Cu), iron (Fe), or the like.
  • the support members 210 and 220 each extend from the inside to the outside of the encapsulation resin 230 .
  • the first support member 210 includes a first die pad 211 disposed in the encapsulation resin 230 and multiple first lead terminals 212 extending from the inside to the outside of the encapsulation resin 230 .
  • the first circuit chip 60 and the isolation chip 80 are mounted on the first die pad 211 .
  • the first die pad 211 is arranged so that the center of the first die pad 211 in the Y-direction is located closer to the resin side surface 233 than the center of the encapsulation resin 230 in the Y-direction is.
  • the first die pad 211 is not exposed from the encapsulation resin 230 .
  • the first die pad 211 is rectangular so that the long sides extend in the X-direction and the short sides extend in the Y-direction.
  • the first lead terminals 212 are separated from each other in the X-direction.
  • the first lead terminals 212 include a first lead terminal 212 A integrated with the first die pad 211 .
  • Each of the first lead terminals 212 partially projects from the resin side surface 233 toward the outside of the encapsulation resin 230 .
  • the second support member 220 includes a second die pad 221 disposed in the encapsulation resin 230 and multiple second lead terminals 222 extending from the inside to the outside of the encapsulation resin 230 .
  • the second circuit chip 70 is mounted on the second die pad 221 .
  • the second die pad 221 is located closer in the Y-direction to the resin side surface 234 than the first die pad 211 is.
  • the second die pad 221 is not exposed from the encapsulation resin 230 .
  • the second die pad 221 is rectangular so that the long sides extend in the X-direction and the short sides extend in the Y-direction.
  • the first die pad 211 and the second die pad 221 are separated from each other in the Y-direction.
  • the Y-direction may be referred to as the arrangement direction of the die pads 211 and 221 .
  • the dimension of the first die pad 211 and the second die pad 221 in the Y-direction is set in accordance with the size and the number of semiconductor chips that are mounted.
  • the first circuit chip 60 and the isolation chip 80 are mounted on the first die pad 211 .
  • the second circuit chip 70 is mounted on the second die pad 221 .
  • the dimension of the first die pad 211 in the Y-direction is greater than the dimension of the second die pad 221 in the Y-direction.
  • the second lead terminals 222 are separated from each other in the X-direction.
  • the second lead terminals 222 include a second lead terminal 222 A integrated with the second die pad 221 .
  • Each of the second lead terminals 222 partially projects from the resin side surface 234 toward the outside of the encapsulation resin 230 .
  • the second lead terminals 222 are equal in number to the first lead terminals 212 . As shown in FIG. 2 , the first lead terminals 212 and the second lead terminals 222 are arranged in a direction (the X-direction) orthogonal to the arrangement direction (the Y-direction) of the first die pad 211 and the second die pad 221 . The number of the second lead terminals 222 and the number of the first lead terminals 212 may be changed in any manner.
  • the first support member 210 and the second support member 220 are each formed of a lead frame.
  • the first die pad 211 , the first lead terminals 212 , the second die pad 221 , and the second lead terminals 222 are formed of the same lead frame.
  • the lead frame includes an outer frame surrounding the first support member 210 and the second support member 220 .
  • the first lead terminals 212 and the second lead terminals 222 are joined to the outer frame.
  • the first lead terminals 212 and the second lead terminals 222 are separated from the outer frame.
  • the first die pad 211 is connected to the first lead terminal 212 A, which is one of the first lead terminals 212 .
  • the first die pad 211 and the first lead terminal 212 A are formed integrally as an integrated structure.
  • the first die pad 211 is supported by the first lead terminal 212 A.
  • the second die pad 221 is connected to the second lead terminal 222 A, which is one of the second lead terminals 222 .
  • the second die pad 221 and the second lead terminal 222 A are formed integrally as an integrated structure.
  • the second die pad 221 is supported by the second lead terminal 222 A.
  • the die pads 211 and 221 are not provided with a suspension lead exposed from the resin side surfaces 231 and 232 . This increases the insulation distance (creepage distance) between the first support member 210 and the second support member 220 .
  • first die pad 211 is supported by a single first lead terminal 212 A
  • the other first lead terminals 212 may be used as terminals that input or output a signal.
  • the second die pad 221 is supported by a single second lead terminal 222 A
  • the other second lead terminals 222 may be used as terminals that input or output a signal.
  • the first circuit chip 60 , the second circuit chip 70 , and the isolation chip 80 are separated from each other in the Y-direction. In the Y-direction, the first circuit chip 60 , the isolation chip 80 , and the second circuit chip 70 are arranged in this order in a direction from the first lead terminals 212 toward the second lead terminals 222 .
  • the first circuit chip 60 includes the first circuit 10 shown in FIG. 1 .
  • the first circuit chip 60 is rectangular and has short sides and long sides.
  • the first circuit chip 60 is mounted on the first die pad 211 such that the long sides extend in the X-direction and the short sides extend in the Y-direction.
  • the first circuit chip 60 includes a chip main surface 60 s and a chip back surface 60 r facing opposite directions in the Z-direction.
  • the chip back surface 60 r of the first circuit chip 60 is bonded to the first die pad 211 by a conductive bonding material SD.
  • the conductive bonding material SD is solder, silver (Ag) paste, or the like.
  • multiple first electrodes 61 , multiple second electrodes 62 , and multiple third electrodes 63 are formed on the chip main surface 60 s of the first circuit chip 60 .
  • the first electrodes 61 , the second electrodes 62 , and the third electrodes 63 are electrically connected to the first circuit 10 .
  • the first electrodes 61 are located on the chip main surface 60 s closer to the first lead terminals 212 than the center of the chip main surface 60 s in the Y-direction is.
  • the first electrodes 61 are arranged in the X-direction.
  • the second electrodes 62 are arranged on opposite ends of the chip main surface 60 s in the X-direction.
  • the third electrodes 63 are arranged on one of the two ends of the chip main surface 60 s in the Y-direction located closer to the isolation chip 80 .
  • the third electrodes 63 are arranged in the X-direction.
  • the second circuit chip 70 includes the second circuit 20 shown in FIG. 1 .
  • the second circuit chip 70 is rectangular and has short sides and long sides.
  • the second circuit chip 70 is mounted on the second die pad 221 such that the long sides extend in the X-direction and the short sides extend in the Y-direction.
  • the second circuit chip 70 includes a chip main surface 70 s and a chip back surface 70 r facing opposite directions in the Z-direction.
  • the chip back surface 70 r of the second circuit chip 70 is bonded to the second die pad 221 by the conductive bonding material SD.
  • first electrodes 71 , multiple second electrodes 72 , and multiple third electrodes 73 are formed in the chip main surface 70 s of the second circuit chip 70 .
  • the first electrodes 71 , the second electrodes 72 , and the third electrodes 73 are electrically connected to the second circuit 20 .
  • the multiple first electrodes 71 are arranged on one of the two ends of the chip main surface 70 s in the Y-direction located farther from the isolation chip 80 .
  • the multiple first electrodes 71 are arranged on one of the two ends of the chip main surface 70 s in the Y-direction located closer to the second lead terminals 222 .
  • the first electrodes 71 are arranged in the X-direction.
  • the second electrodes 72 are arranged on opposite ends of the chip main surface 70 s in the X-direction.
  • the third electrodes 73 are arranged on one of the two ends of the chip main surface 70 s in the Y-direction located closer to the isolation chip 80 .
  • the multiple third electrodes 73 are arranged in the X-direction.
  • the isolation chip 80 includes the transformers 40 shown in FIG. 1 .
  • the isolation chip 80 is rectangular and has short sides and long sides.
  • the isolation chip 80 is mounted on the first die pad 211 such that the long sides extend in the X-direction and the short sides extend in the Y-direction.
  • the isolation chip 80 is arranged next to the first circuit chip 60 in the Y-direction.
  • the isolation chip 80 is arranged closer to the second circuit chip 70 than the first circuit chip 60 is. In other words, the isolation chip 80 is located between the first circuit chip 60 and the second circuit chip 70 in the Y-direction.
  • the isolation chip 80 includes a chip main surface 80 s and a chip back surface 80 r facing opposite directions in the Z-direction.
  • the chip back surface 80 r of the isolation chip 80 is bonded to the first die pad 211 by the conductive bonding material SD.
  • the isolation chip 80 includes multiple first electrodes 81 and multiple second electrodes 82 .
  • the first electrodes 81 and the second electrodes 82 are arranged on the chip main surface 80 s of the isolation chip 80 .
  • the first electrodes 81 are arranged on one of the two ends of the isolation chip 80 in the Y-direction located closer to the first circuit chip 60 .
  • the first electrodes 81 are arranged in the X-direction.
  • the second electrodes 82 are arranged near the center of the isolation chip 80 in the Y-direction.
  • the second electrodes 82 are arranged in the X-direction.
  • the support members 210 and 220 are closest to each other at the first die pad 211 and the second die pad 221 . Therefore, the first die pad 211 and the second die pad 221 need to be separated from each other to allow the signal transmission device 100 to have a predetermined breakdown voltage. Hence, in plan view, the distance between the second circuit chip 70 and the isolation chip 80 is greater than the distance between the first circuit chip 60 and the isolation chip 80 .
  • Wires W 1 to W 4 are connected to the first circuit chip 60 , the isolation chip 80 , and the second circuit chip 70 .
  • Each of the wires W 1 to W 4 is a bonding wire formed by a wire bonder and is, for example, formed from a conductor including gold (Au), aluminum (Al), Cu, or the like.
  • the first circuit chip 60 is electrically connected to the first lead terminals 212 by the wires W 1 . More specifically, the first electrodes 61 and the second electrodes 62 of the first circuit chip 60 are connected to the first lead terminals 212 by the wires W 1 .
  • the second electrodes 62 of the first circuit chip 60 are electrically connected to the first lead terminal 212 A, which is one of the first lead terminals 212 integrated with the first die pad 211 , by the wires W 1 .
  • the first circuit 10 is electrically connected to the first lead terminals 212 .
  • the first lead terminal 212 A which is integrated with the first die pad 211 , serves as a ground terminal.
  • the first circuit 10 is electrically connected to the first die pad 211 by the wire W 1 .
  • the first die pad 211 has the same potential as a first ground GND 1 of the first circuit 10 .
  • the second circuit chip 70 is electrically connected to the second lead terminals 222 of the second support member 220 by the wires W 4 . More specifically, the multiple first electrodes 71 and the multiple second electrodes 72 of the second circuit chip 70 are connected to the second lead terminals 222 by the wires W 4 . Thus, the second circuit 20 is electrically connected to the second lead terminals 222 .
  • the second lead terminal 222 A which is integrated with the second die pad 221 , serves as a ground terminal.
  • the second circuit 20 is electrically connected to the second die pad 221 by the wire W 4 .
  • the second die pad 221 has the same potential as a second ground GND 2 of the second circuit 20 .
  • the isolation chip 80 is connected to the first circuit chip 60 by the wires W 2 .
  • the isolation chip 80 is connected to the second circuit chip 70 by the wires W 3 . More specifically, the first electrodes 81 of the isolation chip 80 are connected to the third electrodes 63 of the first circuit chip 60 by the wires W 2 .
  • the second electrodes 82 of the isolation chip 80 are connected to the third electrodes 73 of the second circuit chip 70 by the wires W 3 .
  • the first coils 41 (refer to FIG. 1 ) of the transformers 40 A and 40 B are electrically connected to the first ground GND 1 of the first circuit chip 60 by the wires W 2 .
  • the second coils 42 (refer to FIG. 1 ) of the transformers 40 A and 40 B are electrically connected to the second ground GND 2 of the second circuit chip 70 by the wires W 3 .
  • FIG. 1 shows an example of the configuration of the signal transmission device 100 .
  • the circuit configurations included in the first circuit chip 60 and the second circuit chip 70 may be changed.
  • the first circuit 10 may include only the transmission circuit 11
  • the second circuit 20 may include only the reception circuit 21 .
  • the first circuit 10 may include a circuit other than the transmission circuit 11 and the reception circuit 12 .
  • the second circuit 20 may include a circuit other than the reception circuit 21 and the transmission circuit 22 .
  • the first circuit 10 may include an analog-digital conversion circuit.
  • the signal transmission device 100 is used as an isolated A/D converter.
  • the second circuit 20 may include a driver circuit that drives the gate of a switching element.
  • the driver circuit may be connected to a terminal (e.g., second lead terminal 222 shown in FIG. 2 ) of the signal transmission device 100 .
  • the signal transmission device 100 is used as an isolated gate driver that drives the switching element.
  • the switching element may include a power semiconductor element such as a Si metal-oxide-semiconductor field-effect transistor (SiMOSFET), a SiCMOSFET, or an insulated gate bipolar transistor (IGBT).
  • SiMOSFET Si metal-oxide-semiconductor field-effect transistor
  • IGBT insulated gate bipolar transistor
  • the switching element is used for a motor driver circuit in an inverter device.
  • the driver circuit typically includes a half-bridge circuit where a low-side switching element and a high-side switching element are connected in a totem-pole configuration.
  • the signal transmission device 100 applies a drive voltage signal to a control terminal of a switching element.
  • the transmission circuit 11 of the first circuit 10 converts, for example, a control signal input from a control device into a pulse signal.
  • the reception circuit 21 receives a signal through the transformers 40 A and 40 B
  • the driver circuit of the second circuit 20 outputs a drive voltage signal to the control terminal of the switching element.
  • the transmission circuit 22 of the second circuit 20 and the reception circuit 12 of the first circuit 10 may be used to, for example, transmit a detection signal of a temperature sensor arranged in the vicinity of a motor to the controller.
  • the power voltage of the first circuit 10 configured to receive a signal from the controller is 5 V or 3.3 V with reference to the ground potential.
  • the second circuit 20 is connected to a high-side switching element and transiently receives a voltage (e.g., 600 V or higher) equivalent to the voltage applied to the drain of the high-side switching element.
  • the signal transmission device 100 needs a breakdown voltage between the first circuit 10 and the second circuit 20 ; more specifically, between the first coil 41 and the second coil 42 of the transformers 40 A and 40 B.
  • the breakdown voltage needed for the signal transmission device 100 is in a range of 2500 Vrms to 7500 Vrms, inclusive. In an example, the breakdown voltage of the signal transmission device 100 is approximately 5000 Vrms. However, the breakdown voltage of the signal transmission device 100 is not limited to these values and may be any specific numerical value.
  • the direction extending from the chip back surface 80 r of the isolation chip 80 toward the chip main surface 80 s will be referred to as the upward direction
  • the direction extending from the chip main surface 80 s toward the chip back surface 80 r will be referred to as the downward direction.
  • FIG. 4 is a perspective view showing the outer appearance of the isolation chip 80 .
  • FIG. 5 is a plan view of the isolation chip 80 .
  • the passivation film 160 is indicated by double-dashed lines, and the transformers 40 A and 40 B and a dummy wire 150 , which will be described later, are indicated by broken lines.
  • FIG. 6 is an enlarged plan view showing a portion of the isolation chip 80 shown in FIG. 5 .
  • the transformers 40 A and 40 B are enlarged.
  • FIG. 7 is a cross-sectional view of the isolation chip 80 cut along an XY-planar through a position of the first coil 41 in the Z-direction and shows the connection relationship of the first coil 41 .
  • FIG. 8 is a cross-sectional view of the isolation chip 80 cut along an XY-plane through a position of the second coil 42 in the Z-direction and shows the connection relationship of the second coil 42 .
  • FIG. 7 and FIG. 8 do not show hatching for clarity.
  • FIG. 9 is a cross-sectional view of the isolation chip 80 taken along line 9 - 9 in FIG. 5 showing cross-sectional structures of the first coil 41 , the second coil 42 , the dummy wire 150 , a first inner electrode 81 A, and a second inner electrode 82 A.
  • FIG. 10 is a cross-sectional view of the isolation chip 80 taken along line 10 - 10 in FIG. 5 showing cross-sectional structures of the dummy wire 150 , a first outer electrode 81 C, and a second outer electrode 82 C.
  • FIG. 9 and FIG. 10 do not show hatching lines for some of the components to simplify illustration.
  • FIG. 11 is a partial enlarged schematic plan view of the isolation chip 80 showing second inner electrodes 82 A, the first outer electrode 81 C, and second coils 42 .
  • FIG. 12 is a cross-sectional view of the isolation chip 80 taken along line 12 - 12 in FIG. 11 showing cross-sectional structures of the second coil 42 and the second inner electrode 82 A.
  • the isolation chip 80 includes four pairs of transformers 40 A and 40 B. More specifically, the isolation chip 80 is a single semiconductor chip including four pairs of transformers 40 A and 40 B. That is, the isolation chip 80 is arranged separately from the first circuit chip 60 and the second circuit chip 70 (refer to FIG. 2 ).
  • the transformers 40 A and 40 B are arranged near the center of the chip main surface 80 s in the Y-direction.
  • the first electrodes 81 and the second electrodes 82 are electrically connected to the transformers 40 A and 40 B.
  • the second electrodes 82 include the second inner electrodes 82 A, which overlap inner regions 42 A of the transformers 40 A and 40 B, and second outer electrodes 82 C, which are located outside the transformers 40 A and 40 B, in plan view.
  • Each second inner electrode 82 A is connected to an inner end wire 46 A connected to an inner end of the second coil 42 .
  • Each second outer electrode 82 C is connected to an outer end wire 46 C connected to an outer end of the second coil 42 .
  • the second inner electrode 82 A and the second outer electrode 82 C are formed from a material including one or more selected from Cu, Al, nickel (Ni), palladium (Pd), and tungsten (W).
  • the transformers 40 A and 40 B are each electrically connected to a second inner electrode 82 A.
  • the second electrodes 82 include a second inner electrode 82 A that is connected to a transformer 40 A and a second inner electrode 82 A that is connected to a transformer 40 B.
  • the second outer electrode 82 C is arranged between the transformer 40 A and the transformer 40 B.
  • the transformer 40 A and the transformer 40 B are electrically connected to a second outer electrode 82 C.
  • the second outer electrode 82 C may be referred to as a common pad of the two transformers 40 A and 40 B.
  • the second inner electrode 82 A is shaped so that the dimension in the Y-direction, which is orthogonal to the X-direction, is smaller than the dimension in the X-direction, in which the second electrodes 82 are arranged.
  • the second inner electrode 82 A is rectangular and elongated in the X-direction.
  • the second outer electrode 82 C is shaped so that the dimension in the X-direction, in which the second electrodes 82 are arranged, is equal to the dimension in the Y-direction.
  • the second outer electrode 82 C is square.
  • the first electrodes 81 are arranged so that two first electrodes 81 are aligned with one transformer 40 A with respect to the X-direction, two first electrodes 81 are aligned with one transformer 40 B with respect to the X-direction, and one first electrode 81 is located between the transformer 40 A and the transformer 40 B in the X-direction.
  • the first electrodes 81 are located closer in the Y-direction to a chip side surface 802 than the transformers 40 A and 40 B are. In other words, the first electrodes 81 are located between the chip side surface 802 and the transformers 40 A and 40 B in the Y-direction. In other words, in plan view, the first electrodes 81 are located closer to the first lead terminals 212 (refer to FIG. 2 ) than the transformers 40 A and 40 B are.
  • the first electrodes 81 include a first inner electrode 81 A corresponding to the second inner electrode 82 A of the second electrodes 82 and a first outer electrode 81 C corresponding to the second outer electrode 82 C of the second electrodes 82 .
  • the first inner electrode 81 A is connected to an inner end wire 44 A; that is, an inner end of the first coil 41 .
  • the first outer electrode 81 C is connected to an outer end wire 44 C; that is, an outer end of the first coil 41 .
  • the first inner electrode 81 A and the first outer electrode 81 C are formed from a material including one or more selected from Cu, Al, Ni, Pd, and W.
  • the transformers 40 A and 40 B are each electrically connected to a first inner electrode 81 A.
  • the isolation chip 80 includes a first inner electrode 81 A that is electrically connected to the transformer 40 A and a first inner electrode 81 A that is electrically connected to the transformer 40 B.
  • the transformers 40 A and the transformers 40 B are electrically connected to a first outer electrode 81 C.
  • the first outer electrode 81 C may be referred to as a common pad of the two transformers 40 A and 40 B.
  • the first inner electrode 81 A is shaped so that the dimension in the Y-direction, which is orthogonal to the X-direction, is smaller than the dimension in the X-direction, in which the first electrodes 81 are arranged.
  • the first inner electrode 81 A is rectangular and elongated in the X-direction.
  • the first outer electrode 81 C is shaped so that the dimension in the X-direction, in which the second electrodes 82 are arranged, is equal to the dimension in the Y-direction.
  • the first outer electrode 81 C is square.
  • the first inner electrode 81 A overlaps the transformers 40 A and 40 B as viewed in the Y-direction.
  • the first outer electrode 81 C overlaps a portion located between the transformer 40 A and the transformer 40 B in the X-direction.
  • the first electrodes 81 ( 81 A, 81 C) are aligned with each other with respect to the Y-direction and separated from each other in the X-direction.
  • One pair of transformers 40 A and 40 B has the same configuration as another pair of transformers 40 A and 40 B.
  • the transformer 40 B and the transformer 40 A have the same structure. Thus, the structure of the transformer 40 A will be described in detail, and the transformer 40 B will not be described.
  • the isolation chip 80 includes four chip side surfaces 801 , 802 , 803 , and 804 orthogonal to each of the chip main surface 80 s and the chip back surface 80 r.
  • the chip side surfaces 801 to 804 are arranged between the chip main surface 80 s and the chip back surface 80 r in the Z-direction.
  • the chip side surfaces 801 and 802 define opposite surfaces of the isolation chip 80 in the Y-direction.
  • the chip side surfaces 803 and 804 define opposite surfaces of the isolation chip 80 in the X-direction.
  • the chip side surfaces 801 and 802 define the long sides of the isolation chip 80 .
  • the chip side surfaces 803 and 804 define the short sides of the isolation chip 80 .
  • the chip side surface 801 is located closer to the second circuit chip 70 (refer to FIG. 2 ) than the chip side surface 802 is.
  • the chip side surface 802 is located closer to the first circuit chip 60 (refer to FIG. 2 ) than the chip side surface 801 is.
  • the isolation chip 80 includes a substrate 83 and an insulation layer 84 formed on the substrate 83 .
  • the substrate 83 is composed of, for example, a semiconductor substrate.
  • the substrate 83 is formed from a material including, for example, silicon (Si).
  • the Si substrate serving as the substrate 83 may be a semiconductor substrate formed from a single-crystal intrinsic semiconductor material, a p-type semiconductor substrate including an acceptor impurity, an n-type semiconductor substrate including a donor impurity, or the like.
  • the substrate 83 may be an epitaxial substrate including a Si substrate and an epitaxial layer formed on the Si substrate.
  • a functional device may be formed on the substrate 83 .
  • the functional device may include a passive element such as a resistor, an active element such as a transistor, a circuit network formed of multiple elements, and the like.
  • a wide-bandgap semiconductor or a compound semiconductor may be used for the substrate 83 .
  • the substrate 83 may be an insulating substrate formed from a material including glass.
  • the wide-bandgap semiconductor is a semiconductor substrate having a band gap that is greater than or equal to 2.0 eV.
  • the wide-bandgap semiconductor may include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga 2 O 3 ), or the like.
  • the compound semiconductor may be a group III-V compound semiconductor.
  • the compound semiconductor may include at least one of aluminum nitride (AlN), indium nitride (InN), GaN, and gallium arsenide (GaAs).
  • the substrate 83 includes a substrate main surface 83 s and a substrate back surface 83 r facing opposite directions in the Z-direction.
  • the substrate back surface 83 r includes the chip back surface 80 r of the isolation chip 80 .
  • the insulation layer 84 includes an upper surface 84 s and a lower surface 84 r that face in opposite directions.
  • the insulation layer 84 includes multiple insulation films 85 stacked on the substrate main surface 83 s of the substrate 83 in the Z-direction.
  • the Z-direction may be referred to as the thickness-wise direction of the insulation layer 84 .
  • the Z-direction may be referred to as a stacking direction of the insulation films 85 .
  • the insulation layer 84 is formed on the substrate main surface 83 s of the substrate 83 .
  • Each insulation film 85 includes a first insulation film 85 A and a second insulation film 85 B formed on the first insulation film 85 A.
  • the first insulation film 85 A is a thin film and is, for example, an etching stopper layer.
  • the first insulation film 85 A is formed from a material including silicon nitride (SiN), SiC, nitrogen-added silicon carbide (SiCN), or the like.
  • the first insulation film 85 A is formed from a material including SiN.
  • the second insulation film 85 B is, for example, an interlayer insulation film.
  • the second insulation film 85 B is formed from a material including silicon oxide (SiO 2 ).
  • the second insulation film 85 B is thicker than the first insulation film 85 A.
  • the thickness of the first insulation film 85 A may be greater than or equal to 100 nm and less than 1000 nm.
  • the thickness of the second insulation film 85 B may be in a range of 1000 nm to 3000 nm.
  • the thickness of the first insulation film 85 A is, for example, approximately 300 nm.
  • the thickness of the second insulation film 85 B is, for example, approximately 2000 nm.
  • the second insulation films 85 B include a lowermost insulation film 85 L, which is in contact with the substrate main surface 83 s of the substrate 83 , and an uppermost insulation film 85 U.
  • both the lowermost insulation film 85 L and the uppermost insulation film 85 U are thinner than the other insulation films 85 .
  • the thickness of each of the lowermost insulation film 85 L and the uppermost insulation film 85 U is in a range of the thickness of the first insulation film 85 A to the thickness of the second insulation film 85 B.
  • the thickness of the lowermost insulation film 85 L and the uppermost insulation film 85 U may be changed in any manner.
  • the thickness of each of the lowermost insulation film 85 L and the uppermost insulation film 85 U may be greater than the thickness of the second insulation film 85 B or may be greater than or equal to the thickness of an insulation film 85 that includes the first insulation film 85 A and the second insulation film 85 B.
  • the first coils 41 of the transformers 40 A and 40 B are formed of a first coil wire 43 .
  • the first coil wire 43 is annular and, for example, has a circular spiral shape.
  • the first coil 41 is formed from a material including one or more selected from titanium (Ti), titanium nitride (TiN), Au, Ag, Cu, Al, and W.
  • a first inner end wire 44 A is located at an inner side of the first coil wire 43 .
  • a first outer end wire 44 C is located at an outer side of the first coil wire 43 .
  • One end of the first coil wire 43 is electrically connected to the first inner end wire 44 A.
  • the other end of the first coil wire 43 is electrically connected to the first outer end wire 44 C.
  • the first inner end wire 44 A and the first outer end wire 44 C are formed from a material including one or more selected from Ti, TiN, Au, Ag, Cu, Al, and W.
  • the first outer end wire 44 C serves as a common end wire of the first coils 41 of the transformers 40 A and 40 B.
  • an outer end wire may be arranged for each of the first coils 41 of the transformers 40 A and 40 B.
  • the first inner end wire 44 A is connected to the first inner electrode 81 A by an interconnect 131 A.
  • the interconnect 131 A is formed from a material including one or more selected from Ti, TiN, Au, Ag, Cu, Al, and W.
  • the interconnect 131 A includes a first interconnect part 132 A extending through the insulation films 85 in the Z-direction and a second interconnect part 136 A extending in the Y-direction.
  • the first interconnect part 132 A is arranged to overlap the first inner electrode 81 A in plan view and is connected to the first inner electrode 81 A.
  • the first interconnect part 132 A extends through the insulation films 85 from the insulation film 85 that is located immediately below the uppermost insulation film 85 U to the insulation film 85 that is located above the lowermost insulation film 85 L with one insulation film 85 interposed.
  • the first interconnect part 132 A includes flat interconnect pieces 133 A and 134 A and multiple vias 135 A.
  • the interconnect pieces 133 A and 134 A are located at the same positions as the insulation films 851 and 852 in which the coils 41 and 42 are arranged.
  • the vias 135 A are arranged between the two interconnect pieces in the Z-direction, between the upper interconnect piece 134 A and the first inner electrode 81 A, and between the lower interconnect piece 133 A and the second interconnect part 136 A.
  • the interconnect pieces 133 A and 134 A are formed from the same conductive material as the first coil 41 and the second coil 42 .
  • the second interconnect part 136 A is located closer to the substrate 83 than the first interconnect part 132 A is.
  • the second interconnect part 136 A is located closer to the substrate 83 than the first coil 41 is.
  • the second interconnect part 136 A is arranged in the insulation film 85 located immediately above the lowermost insulation film 85 L among the insulation films 85 .
  • a first end is located closer to the chip side surface 802 of the isolation chip 80 and overlaps the first interconnect part 132 A in plan view.
  • the second interconnect part 136 A is connected to the first interconnect part 132 A.
  • the second interconnect part 136 A includes a second end opposite to the first end.
  • the second end is arranged to overlap the first coil 41 of the transformer 40 A. More specifically, in plan view, the second end overlaps the first inner end wire 44 A, which is connected to the first coil 41 of the transformer 40 A.
  • the second interconnect part 136 A includes multiple vias 137 A connecting the second interconnect part 136 A and the first inner end wire 44 A.
  • the first outer end wire 44 C is electrically connected to the first outer electrode 81 C by an interconnect 131 C.
  • the interconnect 131 C is formed from a material including one or more selected from Ti, TiN, Au, Ag, Cu, Al, and W.
  • the interconnect 131 C includes a first interconnect part 132 C extending through the insulation films 85 in the Z-direction and a second interconnect part 136 C extending in the Y-direction.
  • the first interconnect part 132 C and the first interconnect part 132 A of the interconnect 131 A have the same structure.
  • the first interconnect part 132 C is arranged to overlap the first outer electrode 81 C in plan view and is connected to the first outer electrode 81 C.
  • the first interconnect part 132 C extends through the insulation films 85 from the insulation film 85 that is located immediately below the uppermost insulation film 85 U to the insulation film 85 that is located above the lowermost insulation film 85 L with one insulation film 85 interposed.
  • the first interconnect part 132 C includes flat interconnect pieces 133 C and 134 C and multiple vias 135 C.
  • the interconnect pieces 133 C and 134 C are located at the same positions as the insulation films 851 and 852 in which the coils 41 and 42 are arranged.
  • the vias 135 C are arranged between the two interconnect pieces in the Z-direction, between the upper interconnect piece and the first outer electrode 81 C, and between the lower interconnect piece and the second interconnect part 136 C.
  • the interconnect pieces 133 C and 134 C are formed from the same conductive material as the first coil 41 and the second coil 42 .
  • the second interconnect part 136 C is located closer to the substrate 83 than the first interconnect part 132 C is.
  • the second interconnect part 136 C is located closer to the substrate 83 than the first coil 41 is.
  • the second interconnect part 136 C is arranged in the insulation film 85 located immediately above the lowermost insulation film 85 L among the insulation films 85 .
  • a first end is located closer to the chip side surface 802 of the isolation chip 80 and overlaps the first interconnect part 132 C in plan view.
  • the second interconnect part 136 C is connected to the first interconnect part 132 C.
  • the second interconnection piece 133 C has a second end opposite to the first end.
  • the second end does not overlap the first coil 41 of the transformer 40 A in plan view. More specifically, in plan view, the second end overlaps the first outer end wire 44 C, which is connected to the first coil 41 of the transformer 40 A.
  • the second interconnect part 136 C includes multiple vias 137 C connecting the second interconnect part 136 C and the first outer end wire 44 C.
  • the second interconnect part 136 C of the interconnect 131 C is electrically connected to the substrate 83 by vias 138 that extend through the lowermost insulation film 85 L.
  • the vias 138 may be omitted.
  • the second coils 42 of the transformers 40 A and 40 B each include a second coil wire 45 .
  • the second coil wire 45 is annular and, for example, has a circular spiral shape.
  • the second coil 42 is formed from a material including one or more selected from Ti, TiN, Au, Ag, Cu, Al, and W.
  • a second inner end wire 46 A is located in an inner region 42 A surrounded by the second coil wire 45 .
  • a second outer end wire 46 C is located at an outer side of the second coil wire 45 .
  • One end of the second coil wire 45 is electrically connected to the second inner end wire 46 A.
  • the other end of the second coil wire 45 is electrically connected to the second outer end wire 46 C.
  • the second inner end wire 46 A and the second outer end wire 46 C are formed from a material including one or more selected from Ti, TiN, Au, Ag, Cu, Al, and W.
  • the second outer end wire 46 C serves as a common end wire of the transformers 40 A and 40 B and the second coil 42 .
  • the second outer end wire 46 C may be arranged for each of the second coils 42 of the transformers 40 A and 40 B.
  • the second coil wire 45 has the same winding direction as the first coil wire 43 shown in FIG. 7 .
  • the second coil wire 45 has the same number of wiring turns as the first coil wire 43 .
  • the number of wiring turns may differ between the second coil wire 45 and the first coil wire 43 .
  • the first coil 41 and the second coil 42 of the transformer 40 A are opposed to each other in the Z-direction with one or more of the insulation films 85 interposed.
  • the first coil 41 and the second coil 42 are opposed to each other in the Z-direction with two or more of the insulation films 85 interposed.
  • the first coil 41 is formed as a conductive layer embedded in one of the insulation films 85 . More specifically, the first coil 41 is embedded in an insulation film 851 .
  • the insulation film 851 includes a wire groove 141 (first wire groove) extending through the first insulation film 85 A and the second insulation film 85 B in the Z-direction. A conductive layer is embedded in the wire groove 141 of the insulation film 851 to form the first coil 41 .
  • the insulation film 851 in which the first coil 41 is embedded, is covered by insulation films 85 located next to the insulation film 851 in the Z-direction. In other words, the first coil 41 is embedded in the insulation films 85 .
  • the second coil 42 is formed as a conductive layer embedded in one of the insulation films 85 . More specifically, the second coil 42 is embedded in an insulation film 852 .
  • the insulation film 852 includes a wire groove 142 (second wire groove) extending through the first insulation film 85 A and the second insulation film 85 B in the Z-direction. A conductive layer is embedded in the wire groove 142 of the insulation film 852 to form the second coil 42 .
  • the insulation film 852 in which the second coil 42 is embedded, is covered by insulation films 85 located next to the insulation film 852 in the Z-direction. In other words, the second coil 42 is embedded in the insulation films 85 .
  • the second coil 42 is located farther from the substrate 83 than the first coil 41 is in the Z-direction. That is, the second coil 42 is located upward from the first coil 41 . In other words, the first coil 41 is located closer to the substrate 83 than the second coil 42 is. A distance D 1 between the first coil 41 and the second coil 42 in the Z-direction is greater than the distance between the first coil 41 and the substrate main surface 83 s of the substrate 83 .
  • the first inner electrode 81 A is formed on the uppermost insulation film 85 U. That is, the first inner electrode 81 A is formed on the upper surface 84 s of the insulation layer 84 . Vias 91 A extend through the insulation film 85 U and electrically connect the first inner electrode 81 A to the interconnect piece 134 A of the first interconnect part 132 A.
  • the first outer electrode 81 C is formed on the uppermost insulation film 85 U. That is, the first outer electrode 81 C is formed on the upper surface 84 s of the insulation layer 84 . Vias 91 C extend through the insulation film 85 U and electrically connect the first outer electrode 81 C to the interconnect piece 134 C of the first interconnect part 132 C.
  • the second inner electrode 82 A is formed on the uppermost insulation film 85 U. That is, the second inner electrode 82 A is formed on the upper surface 84 s of the insulation layer 84 . Vias 92 A extend through the insulation film 85 U and electrically connect the second inner electrode 82 A to the second inner end wire 46 A.
  • the second outer electrode 82 C is formed on the uppermost insulation film 85 U. That is, the second outer electrode 82 C is formed on the upper surface 84 s of the insulation layer 84 . Vias 92 C extend through the insulation film 85 U and electrically connect the second outer electrode 82 C and the second outer end wire 46 C.
  • the isolation chip 80 includes the dummy wire 150 arranged around the first coils 41 of the transformers 40 A and 40 B.
  • the dummy wire 150 may be omitted.
  • the dummy wire 150 includes a first dummy wire 151 , a second dummy wire 152 , and a third dummy wire 153 .
  • the first dummy wire 151 , the second dummy wire 152 , and the third dummy wire 153 are formed from a material including one or more selected from Ti, TiN, Au, Ag, Cu, Al, and W.
  • the first dummy wire 151 is arranged in a region between the second coil 42 of the transformer 40 A and the second coil 42 of the transformer 40 B in the X-direction.
  • the first dummy wire 151 is patterned differently from the second coil 42 .
  • the first dummy wire 151 is electrically connected to the second outer end wire 46 C.
  • the first dummy wire 151 is a wiring pattern configured not to allow current to flow.
  • the first dummy wire 151 may be electrically connected to at least one of the four second outer end wires 46 C shown in FIG. 5 .
  • the first dummy wire 151 has the same potential as the second coil 42 .
  • the voltage of the first dummy wire 151 may become higher than the voltage of the first coil 41 in the same manner as the second coil 42 .
  • the first dummy wire 151 is located at the same position as the second dummy wire 152 and the third dummy wire 153 in the Z-direction.
  • the second dummy wire 152 and the third dummy wire 153 are located at the same position as the second coil 42 in the Z-direction. Therefore, although not shown in the drawings, the first dummy wire 151 is located at the same position as the second coil 42 in the Z-direction. That is, the first dummy wire 151 is located farther from the substrate 83 than the first coil 41 is.
  • the dummy wire 150 is arranged around the coils of the transformers 40 A and 40 B located closer to the chip main surface 80 s of the isolation chip 80 .
  • the voltage drop between the second coil 42 and the first dummy wire 151 is limited. This avoids concentration of an electric field on the second coil 42 .
  • the third dummy wire 153 surrounds the second coils 42 of the transformers 40 A and 40 B.
  • the third dummy wire 153 is electrically connected to the first dummy wire 151 .
  • the voltage of the third dummy wire 153 may become higher than the voltage of the first coil 41 .
  • the third dummy wire 153 is located at the same position as the second coil 42 in the Z-direction.
  • the third dummy wire 153 is located farther from the substrate 83 than the first coil 41 is.
  • the first to third dummy wires 151 to 153 are aligned with each other with respect to the Z-direction.
  • the voltage drop between the second coil 42 and the third dummy wire 153 is limited. This avoids concentration of an electric field on the second coil 42 .
  • the second dummy wire 152 surrounds the third dummy wire 153 .
  • the second dummy wire 152 is isolated from the second coil 42 . That is, the second dummy wire 152 may be electrically disconnected from the second coil 42 .
  • the second dummy wire 152 is aligned with the second coil 42 with respect to the Z-direction.
  • the second dummy wire 152 is located farther from the substrate 83 than the first coil 41 is.
  • the second dummy wire 152 limits increases in the electric field strength around the second coil 42 and limits concentration of the electric field on the second electrodes 82 (i.e., the second inner electrode 82 A and the second outer electrode 82 C).
  • the isolation chip 80 includes the fourth dummy wire 154 .
  • the fourth dummy wire 154 may be omitted.
  • the fourth dummy wire 154 is formed from a material including one or more selected from Ti, TiN, Au, Ag, Cu, Al, and W.
  • the fourth dummy wire 154 is arranged between the second coil 42 and the first electrodes 81 .
  • the fourth dummy wire 154 extends in the X-direction.
  • the fourth dummy wire 154 extends along the first electrodes 81 .
  • the fourth dummy wire 154 may include multiple wires.
  • the fourth dummy wire 154 is electrically isolated from the second coil 42 . In other words, the fourth dummy wire 154 is not electrically connected to the second coil 42 .
  • the fourth dummy wire 154 separates the first electrodes 81 from the second coil 42 .
  • the isolation chip 80 includes the passivation film 160 .
  • the passivation film 160 is formed on the upper surface 84 s of the insulation layer 84 .
  • the passivation film 160 protects the insulation layer 84 .
  • the passivation film 160 is a surface protection film for the isolation chip 80 .
  • the passivation film 160 is formed from a material including, for example, silicon oxide or silicon nitride.
  • the material including silicon nitride includes, for example, SiN and SiCN.
  • the passivation film 160 includes the chip main surface 80 s of the isolation chip 80 .
  • the first electrodes 81 and the second electrodes 82 are covered by the passivation film 160 .
  • the passivation film 160 includes openings that partially expose the first electrodes 81 and the second electrodes 82 .
  • the first electrodes 81 each have an exposed surface used to connect a wire W 2 .
  • the second electrodes 82 each have an exposed surface used to connect a wire W 3 .
  • the openings of the passivation film 160 are indicated by double-dashed lines.
  • the first electrodes 81 include the first inner electrode 81 A and the first outer electrode 81 C.
  • the passivation film 160 includes a first inner opening 161 partially exposing the first inner electrode 81 A and a first outer opening 162 partially exposing the first outer electrode 81 C.
  • the first inner electrode 81 A is rectangular and is longer in the X-direction than in the Y-direction.
  • the passivation film 160 includes two first inner openings 161 partially exposing the first inner electrode 81 A.
  • the two first inner openings 161 are arranged in the X-direction in conformance with the shape of the first inner electrode 81 A.
  • the two first inner openings 161 are each square and equal in length in the X-direction and the Y-direction.
  • the first inner electrode 81 A includes two exposed surfaces exposed from the two first inner openings 161 in the passivation film 160 .
  • the two exposed surfaces of the first inner electrode 81 A serve as first pads P 1 used for external connection of the first coil 41 .
  • the first inner electrode 81 A includes two first pads P 1 in the two first inner openings 161 .
  • the first outer electrode 81 C is square and has the same length in the Y-direction and the X-direction.
  • the passivation film 160 includes one first outer opening 162 partially exposing the first outer electrode 81 C.
  • the first outer opening 162 is square and has the same length in the X-direction and the Y-direction in conformance with the shape of the first outer electrode 81 C.
  • the first outer opening 162 is equal in size to the first inner opening 161 .
  • the first outer electrode 81 C includes one exposed surface exposed from the one first outer opening 162 in the passivation film 160 .
  • the exposed surface of the first outer electrode 81 C serves as a second pad P 2 used for external connection of the first coil 41 .
  • the first outer electrode 81 C includes one second pad P 2 in the one first outer opening 162 .
  • the second electrodes 82 include the second inner electrode 82 A and the second outer electrode 82 C.
  • the passivation film 160 includes a second inner opening 163 partially exposing the second inner electrode 82 A and a second outer opening 164 partially exposing the first outer electrode 81 C.
  • the second inner opening 163 corresponds to a “second opening.”
  • the second inner electrode 82 A is rectangular and is longer in the X-direction than in the Y-direction.
  • the passivation film 160 includes two second inner openings 163 partially exposing the second inner electrode 82 A.
  • the two second inner openings 163 are arranged in the X-direction in conformance with the shape of the second inner electrode 82 A.
  • the two second inner openings 163 are each square and equal in length in the X-direction and the Y-direction.
  • the second inner electrode 82 A includes two exposed surfaces exposed from the two second inner openings 163 in the passivation film 160 .
  • the two exposed surfaces of the second inner electrode 82 A serve as third pads P 3 used for external connection of the second coil 42 .
  • the second inner electrode 82 A includes two third pads P 3 in the two second inner openings 163
  • the second outer electrode 82 C is square and has the same length in the Y-direction and the X-direction.
  • the passivation film 160 includes one second outer opening 164 partially exposing the second outer electrode 82 C.
  • the second outer opening 164 is square and has the same length in the X-direction and the Y-direction in conformance with the shape of the second outer electrode 82 C. In an example, the second outer opening 164 is equal in size to the first inner opening 161 .
  • the second outer electrode 82 C includes one exposed surface exposed from the one second outer opening 164 in the passivation film 160 .
  • the exposed surface of the second outer electrode 82 C serves as a fourth pad P 4 used for external connection of the second coil 42 .
  • the second outer electrode 82 C includes one fourth pad P 4 in the second outer opening 164 .
  • the isolation chip 80 includes a resin layer 170 formed on the passivation film 160 .
  • the resin layer 170 is formed from, for example, a material including polyimide (PI).
  • the resin layer 170 is separated into an inner resin layer and an outer resin layer by a separation trench 173 . As shown in FIG. 4 , in plan view, the separation trench 173 extends around the transformers 40 A and 40 B.
  • the resin layer 170 includes a first resin opening 174 exposing the first electrode 81 and a second resin opening 175 exposing the second electrode 82 .
  • the second inner electrode 82 A is rectangular and longer in the X-direction than the Y-direction in plan view. In plan view, the second inner electrode 82 A overlaps the inner end wire 46 A.
  • the second inner electrode 82 A is electrically connected to the inner end wire 46 A. In plan view, the second inner electrode 82 A overlaps the inner region 42 A surrounded by the second coil 42 .
  • the inner region 42 A is circular in conformance with the circular spiral shape of the second coil 42 (second coil wire 45 ).
  • the second inner electrode 82 A is rectangular and elongated in the X-direction, in which the second coils 42 of the isolation chip 80 are arranged.
  • the second inner electrode 82 A has a length L 2 in the X-direction.
  • the inner region 42 A surrounded by the second coil 42 has a dimension L 1 in the X-direction.
  • the length L 2 is greater than the dimension L 1 .
  • the dimension of the inner region 42 A surrounded by the second coil 42 in the X-direction is smaller than the length of the second inner electrode 82 A in the X-direction.
  • the second inner electrode 82 A has opposite ends 82 AA and 82 AB overlapping the second coil 42 in plan view.
  • the second inner electrode 82 A includes a first overlap portion 82 A 1 overlapping the inner region 42 A surrounded by the second coil 42 and a second overlap portion 82 A 2 overlapping the second coil 42 .
  • the first overlap portion 82 A 1 corresponds to a “first region.”
  • the second overlap portion 82 A 2 corresponds to a “second region.”
  • the second inner electrode 82 A is arranged at a position overlapping the inner region 42 A and a region 42 B overlapping the second coil 42 .
  • the second overlap portion 82 A 2 is greater in area than the first overlap portion 82 A 1 .
  • the passivation film 160 includes two second inner openings 163 partially exposing the second inner electrode 82 A.
  • the two second inner openings 163 extend above the second inner electrode 82 A, and over the inner region 42 A and a region that overlaps the second coil 42 .
  • the second outer electrode 82 C is square and has the same length in the Y-direction and the X-direction. In plan view, the second outer electrode 82 C is located between the second coils 42 arranged in the X-direction. In plan view, the two second coils 42 are located at opposite sides of the second outer electrode 82 C, which is smaller in length in the X-direction than the second inner electrode 82 A.
  • the first inner electrode 81 A is rectangular and longer in the X-direction than the Y-direction in plan view.
  • the first inner electrode 81 A is equal to the second inner electrode 82 A in length in the X-direction.
  • the first inner electrode 81 A is located at the same position as the second inner electrode 82 A in the X-direction.
  • the first outer electrode 81 C is square and has the same length in the Y-direction and the X-direction. In an example, the first outer electrode 81 C is equal to the second outer electrode 82 C in length in the X-direction. The first outer electrode 81 C is located at the same position as the second outer electrode 82 C in the X-direction.
  • the first circuit chip 60 and the second circuit chip 70 will now be described.
  • the first circuit chip 60 and the second circuit chip 70 have the same configuration.
  • the first circuit chip 60 will be described below so that the description of the second circuit chip 70 is omitted.
  • FIG. 13 is a plan view showing the configuration of the first circuit chip 60 .
  • the functional blocks and the wires of the first circuit chip 60 are indicated by solid lines for the sake of illustration. This does not mean that the functional blocks and the wires are arranged above the first to third electrodes 61 to 63 .
  • the first circuit chip 60 has the shape of a rectangular box that is longer in the X-direction than in the Y-direction.
  • the first circuit chip 60 includes a chip main surface 60 s and a chip back surface 60 r facing opposite directions in the Z-direction.
  • the first circuit chip 60 includes four chip side surfaces 601 , 602 , 603 , and 604 orthogonal to the chip main surface 60 s and the chip back surface 60 r.
  • the chip side surfaces 601 and 602 define opposite end surfaces of the first circuit chip 60 in the Y-direction.
  • the chip side surfaces 603 and 604 define opposite end surfaces of the first circuit chip 60 in the X-direction.
  • the chip side surfaces 601 and 602 define the long sides of the first circuit chip 60
  • the chip side surfaces 603 and 604 define the short sides of the first circuit chip 60
  • the chip side surface 601 is located closer to the isolation chip 80 than the chip side surface 602 is.
  • the chip side surface 602 is located closer to the first lead terminals 212 , which are shown in FIG. 2 , than the chip side surface 601 is.
  • the first circuit chip 60 includes the first electrodes 61 , the second electrodes 62 , and the third electrodes 63 formed on the chip main surface 60 s.
  • the first electrodes 61 are arranged on the chip main surface 60 s along the chip side surface 602 .
  • the second electrodes 62 are arranged on the chip main surface 60 s along the chip side surfaces 603 and 604 .
  • the third electrodes 63 are arranged on the chip main surface 60 s along the chip side surface 601 .
  • the first circuit chip 60 includes the transmission circuits 11 A and 11 B and the reception circuits 12 A and 12 B as functional blocks.
  • the reception circuits 12 A and 12 B and the transmission circuits 11 A and 11 B are arranged between the first electrodes 61 and the third electrodes 63 .
  • the reception circuits 12 A and 12 B and the transmission circuits 11 A and 11 B are arranged in the first circuit chip 60 from the chip side surface 603 toward the chip side surface 604 .
  • the first electrodes 61 are electrically connected to the transmission circuits 11 A and 11 B.
  • the transmission circuits 11 A and 11 B receive a pulse signal from the first electrodes 61 .
  • Some of the first electrodes 61 are connected to the reception circuits 12 A and 12 B.
  • the reception circuits 12 A and 12 B output a pulse signal to the first electrodes 61 .
  • the second electrodes 62 include ground pads 62 G 1 and 62 G 2 electrically connected to the first grounds GND 1 (refer to FIG. 1 ) of the transmission circuits 11 A and 11 B and the reception circuits 12 A and 12 B.
  • the ground pads 62 G 1 and 62 G 2 correspond to a “grounding pad.”
  • the second electrodes 62 include power pads 62 V 1 and 62 V 2 configured to apply a first voltage (refer to FIG. 1 ) to the transmission circuits 11 A and 11 B and the reception circuits 12 A and 12 B.
  • the third electrodes 63 include transmission pads 63 A electrically connected to the transmission circuits 11 A and 11 B and reception pads 63 B electrically connected to the reception circuits 12 A and 12 B.
  • the third electrodes 63 include ground pads 63 C electrically connected to the ground pads 62 G 1 and 62 G 2 .
  • Two transmission pads 63 A connected to each of the transmission circuits 11 A and 11 B are located at opposite sides of a ground pad 63 C.
  • Two reception pads 63 B connected to the reception circuits 12 A and 12 B are located at opposite sides of a ground pad 63 C.
  • the transmission pad 63 A and the reception pad 63 B each correspond to a “signal pad.”
  • the isolation chip 80 includes three ground wires 64 A, 64 B, and 64 C.
  • the three ground wires 64 A, 64 B, and 64 C are electrically connected between the two ground pads 62 G 1 and 62 G 2 .
  • the first ground wire 64 A and the second ground wire 64 B each correspond to a “first grounding wire.”
  • the third ground wire 64 C corresponds to a “second grounding wire.”
  • the first ground wire 64 A corresponds to a “reception grounding wire.”
  • the second ground wire 64 B corresponds to a “transmission grounding wire.”
  • the three ground wires 64 A to 64 C may be electrically connected to one of the ground pad 62 G 1 and the ground pad 62 G 2 .
  • the three ground wires 64 A to 64 C are separated from each other between the two ground pads 62 G 1 and 62 G 2 . In other words, the three ground wires 64 A to 64 C are laid out in different paths between the two ground pads 62 G 1 and 62 G 2 . The three ground wires 64 A to 64 C are isolated from each other.
  • the reception circuits 12 A and 12 B are electrically connected to the first ground wire 64 A.
  • the transmission circuits 11 A and 11 B are electrically connected to the second ground wire 64 B.
  • the ground pads 63 C of the third electrodes 63 are electrically connected to the third ground wire 64 C.
  • two transmission pads 63 A electrically connected to each of the transmission circuits 11 A and 11 B are located at opposite sides of a ground pad 63 C.
  • a drive signal supplied to the first coil 41 of the transformer 40 A through the transmission pads 63 A has only a negligible effect on the potential of the transmission pads 63 A.
  • a drive signal supplied to the first coil 41 of the transformer 40 B through the transmission pads 63 A has only a negligible effect on the potential of the transmission pads 63 A.
  • mutual interferences between reception signals through the reception pads 63 B are reduced in the reception circuits 12 A and 12 B.
  • transmission properties of the signal transmission device 100 are improved.
  • the ground wire is the first ground GND 1 shown in FIG. 1 .
  • the transmission circuit 11 A uses an input pulse signal to drive the first coils 41 of the transformers 40 A and 40 B
  • the operation of the transmission circuit 11 A may result in fluctuation of the potential of the first ground GND 1 .
  • the ground wire is common to the transmission circuits 11 A and 11 B and the reception circuits 12 A and 12 B
  • the potential changes at the first ground GND 1 of the reception circuits 12 A and 12 B.
  • the change in the potential may cause erroneous operations of the reception circuits 12 A and 12 B.
  • the fluctuation in the potential of the first ground GND 1 results in fluctuation in the potential of the ground pads 63 C. This affects reception signals received by the first coils 41 of the transformers 40 A and 40 B. More specifically, an error may occur in a reception signal and an output pulse signal in the reception circuits 12 A and 12 B. This may adversely affect the transmission properties.
  • the fluctuation in the potential of the first ground GND 1 may also be caused by an operation of the reception circuits 12 A and 12 B. In this case, the fluctuation in the potential of the first ground GND 1 may cause erroneous operation of the transmission circuits 11 A and 11 B and an error in a drive signal output from the transmission circuits 11 A and 11 B.
  • the transmission circuits 11 A and 11 B, the reception circuits 12 A and 12 B, and the ground pads 63 C are electrically connected to the ground pads 62 G 1 and 62 G 2 by the first to third ground wires 64 A to 64 C, which are isolated from each other.
  • the fluctuation in the potential of the first ground GND 1 caused by an operation of the transmission circuits 11 A and 11 B has only a negligible effect on the reception circuits 12 A and 12 B.
  • the fluctuation in the potential of the first ground GND 1 caused by an operation of the reception circuits 12 A and 12 B has only a negligible effect on the transmission circuits 11 A and 11 B.
  • the effect on the drive signal and the output pulse signal is reduced.
  • the transmission properties of the signal transmission device 100 are improved.
  • FIG. 14 is a schematic diagram showing the electrical configuration of the signal transmission device 100 .
  • FIG. 14 shows the transmission circuit 11 of the first circuit chip 60 , the transformers 40 A and 40 B of the isolation chip 80 , and the reception circuit 21 of the second circuit chip 70 , which are shown in FIG. 1 .
  • the transmission circuit 22 of the second circuit chip 70 and the reception circuit 12 of the first circuit chip 60 which are shown in FIG. 1 , have the same configuration and thus will not be described and will not be shown in the drawing.
  • the transmission circuit 11 When receiving an input pulse signal Din, the transmission circuit 11 outputs a transmission pulse signal S 1 to the transformers 40 A and 40 B. Then, the transformers 40 A and 40 B transmit the transmission pulse signal S 1 as a reception pulse signal S 2 while isolating the transmission circuit 11 from the reception circuit 21 . When receiving the reception pulse signal S 2 from the transformers 40 A and 40 B, the reception circuit 21 outputs an output pulse signal Dout.
  • the reception circuit 21 includes a high-pass filter 301 , a DC bias circuit 302 , a nonlinear amplifier 303 , an envelope detection circuit 304 , a subtraction circuit 305 , and a comparison circuit 306 .
  • the high-pass filter 301 blocks low-frequency components of the reception pulse signal S 2 that are lower than a cut-off frequency fc, and passes high-frequency components of the reception pulse signal S 2 that are higher than the cut-off frequency fc to generate a filtered reception pulse signal S 3 .
  • the DC bias circuit 302 is connected to an output end of the high-pass filter 301 and sets a DC-bias of the filtered reception pulse signal S 3 .
  • the nonlinear amplifier 303 amplifies the filtered reception pulse signal S 3 in a nonlinear region to generate an amplified reception pulse signal S 4 .
  • the envelope detection circuit 304 detects an envelope of the amplified reception pulse signal S 4 and generates an envelope signal S 5 .
  • the subtraction circuit 305 mitigates undershoot of the envelope signal S 5 .
  • the subtraction circuit 305 When receiving the envelope signal S 5 , the subtraction circuit 305 generates a subtraction envelope signal S 6 .
  • the comparison circuit 306 compares the subtraction envelope signal S 6 with a predetermined threshold value to generate the output pulse signal Dout.
  • FIG. 15 is an example of a detailed electrical configuration of the signal transmission device 100 .
  • the signal transmission device 100 generates a first signal triggered by a rising edge of the input pulse signal Din and a second signal triggered by a falling edge of the input pulse signal Din.
  • the signal transmission device 100 processes the first signal and the second signal to output the output pulse signal Dout. That is, the signals S 1 to S 6 shown in FIG. 14 include signals corresponding to a “first signal” and a “second signal.”
  • a signal corresponding to the first signal is denoted by “R,” and a signal corresponding to the second signal is denoted by “F.”
  • the transmission circuit 11 When receiving the input pulse signal Din, the transmission circuit 11 generates each of a first transmission pulse signal S 1 R and a second transmission pulse signal S 1 F.
  • the transmission circuit 11 uses a rising edge of the input pulse signal Din as a trigger to generate the first transmission pulse signal S 1 R.
  • the first transmission pulse signal S 1 R may include one or more pulses.
  • the transmission circuit 11 uses a falling edge of the input pulse signal Din as a trigger to generate the second transmission pulse signal S 1 F.
  • the second transmission pulse signal S 1 F may include one or more pulses.
  • the reception circuit 21 processes a first reception pulse signal S 2 R and a second reception pulse signal S 2 F, which are output from the transformers 40 A and 40 B, to generate the output pulse signal Dout. In an example, the reception circuit 21 outputs a high-level output pulse signal Dout in accordance with pulse driving of the first reception pulse signal S 2 R. In an example, the reception circuit 21 outputs a low-level output pulse signal Dout in accordance with pulse driving of the second reception pulse signal S 2 F.
  • the transformers 40 A and 40 B transmit the first transmission pulse signal S 1 R as the first reception pulse signal S 2 R while isolating the transmission circuit 11 from the reception circuit 21 .
  • the transformers 40 A and 40 B transmit the second transmission pulse signal SIF as the second reception pulse signal S 2 F while isolating the transmission circuit 11 from the reception circuit 21 .
  • the reception circuit 21 includes high-pass filters 301 R and 301 F, DC bias circuits 302 R and 302 F, nonlinear amplifiers 303 R and 303 F, the envelope detection circuits 304 R and 304 F, the subtraction circuit 305 , and the comparison circuit 306 .
  • the high-pass filter 301 R blocks low-frequency components of the first reception pulse signal S 2 R that are lower than the cut-off frequency fc, and passes high-frequency components of the first reception pulse signal S 2 R that are higher than the cut-off frequency fc to generate a filtered first reception pulse signal S 3 R.
  • the high-pass filter 301 F blocks low-frequency components of the second reception pulse signal S 2 F that are lower than the cut-off frequency fc and passes high-frequency components of the second reception pulse signal S 2 F that are higher than the cut-off frequency fc to generate a filtered second reception pulse signal S 3 F.
  • the DC bias circuit 302 R is connected to an output end of the high-pass filter 301 R and sets a DC-bias of the filtered first reception pulse signal S 3 R.
  • the DC bias circuit 302 F is connected to an output end of the high-pass filter 301 F and sets a DC-bias of the filtered second reception pulse signal S 3 F.
  • the nonlinear amplifier 303 R amplifies the filtered first reception pulse signal S 3 R in a nonlinear region to generate a filtered first amplified reception pulse signal S 4 R.
  • the nonlinear amplifier 303 F amplifies the filtered second reception pulse signal S 3 F in a nonlinear region to generate a second amplified reception pulse signal S 4 F.
  • the envelope detection circuit 304 R detects a positive-side envelope (i.e., envelope of the first amplified received pulse signal S 4 R that lies at the positive side of the DC bias) from the first amplified reception pulse signal S 4 R, which oscillates positively and negatively with respect to the DC bias, to generate a first positive envelope signal S 5 R.
  • the envelope detection circuit 304 F detects a positive-side envelope (i.e., envelope of the second amplified reception pulse signal S 4 F that lies at the positive side of the DC bias) from the second amplified reception pulse signal S 4 F, which oscillates positively and negatively with respect to the DC bias, to generate a second positive envelope signal S 5 F.
  • the subtraction circuit 305 mitigates undershoot of the first positive envelope signal S 5 R and the second positive envelope signal S 5 F.
  • the subtraction circuit 305 When receiving the first positive envelope signal S 5 R and the second positive envelope signal S 5 F, the subtraction circuit 305 generates a first subtraction envelope signal S 6 R and a second subtraction envelope signal S 6 F.
  • the comparison circuit 306 also serves as an in-phase noise canceler for the first subtraction envelope signal S 6 R and the second subtraction envelope signal S 6 F.
  • FIG. 16 is a diagram showing an exemplary configuration of the nonlinear amplifier 303 R and the envelope detection circuit 304 R.
  • the nonlinear amplifier 303 R includes transistors 303 a and 303 b.
  • the transistor 303 a is, for example, an N-channel type MOSFET (NMOSFET).
  • the transistor 303 b is, for example, a P-channel type MOSFET (PMOSFET).
  • the filtered first reception pulse signal S 3 R is input into a gate terminal of the transistor 303 a.
  • a source terminal of the transistor 303 a is connected to the second ground GND 2 .
  • a drain terminal of the transistor 303 a is connected to a drain terminal of the transistor 303 b.
  • the second voltage V 2 is applied to a source terminal of the transistor 303 b.
  • a gate transistor of the transistor 303 b is connected to a drain terminal of the transistor 303 b.
  • the nonlinear amplifier 303 R generates the filtered first amplified reception pulse signal S 4 R having the levels of the gate terminal and the drain terminal of the transistor 303 b.
  • the envelope detection circuit 304 R includes a transistor 304 a, a high-pass filter 304 b , and a register 304 c.
  • the transistor 304 a is, for example, a PMOSFET.
  • the filtered first amplified reception pulse signal S 4 R is input to the high-pass filter 304 b.
  • the high-pass filter 304 b includes an output terminal connected to a gate terminal of the transistor 304 a.
  • the second voltage V 2 is applied to a source terminal of the transistor 304 a.
  • a drain terminal of the transistor 304 a is connected to a first end of the register 304 c.
  • the second ground GND 2 is connected to a second end of the register 304 c.
  • the envelope detection circuit 304 R generates the first positive envelope signal S 5 R having the level between the transistor 304 a and the register 304 c.
  • the nonlinear amplifier 303 F and the envelope detection circuit 304 F which are shown in FIG. 15 , basically have the same configuration as the nonlinear amplifier 303 R and the envelope detection circuit 304 R and thus will not be described and will not be shown in the drawing.
  • the signal transmission device 100 transmits the input pulse signal Din as the output pulse signal Dout while isolating the transmission circuit 11 from the reception circuit 21 .
  • isolation chip 80 and the signal transmission device 100 will now be described.
  • the isolation chip 80 includes the insulation layer 84 , the first coil 41 and the second coil 42 arranged in the insulation layer 84 , and the second electrode 82 electrically connected to the second coil 42 .
  • the second coil 42 is annular in plan view as viewed in the Z-direction.
  • the second electrode 82 includes the second inner electrode 82 A extending over the inner region 42 A surrounded by the second coil 42 and the region 42 B that overlaps the second coil 42 in plan view.
  • the passivation film 160 formed on the upper surface 84 s of the insulation layer 84 , includes the second inner opening 163 at least partially exposing the second inner electrode 82 A.
  • the second inner opening 163 extends above the second inner electrode 82 A, and over the inner region 42 A and the region 42 B, which overlaps the second coil 42 .
  • the isolation chip 80 having the configuration described above, the inner region 42 A surrounded by the second coil 42 is decreased in size in plan view as compared to, for example, a configuration in which the second coil 42 is formed to surround the second electrode 82 . Ultimately, the area of the second coil 42 in plan view is reduced. The first coil 41 is opposed to the second coil 42 in the Z-direction. This decreases the area of the first coil 41 in plan view.
  • the first coil 41 and the second coil 42 are magnetically coupled to each other in the Z-direction.
  • the magnetically coupling of the first coil 41 and the second coil 42 allows for transmission of a pulse signal.
  • the first coil 41 and the second coil 42 are opposed to each other in the Z-direction.
  • parasitic capacitance is formed between the first coil 41 and the second coil 42 .
  • the parasitic capacitance may cause noise in a signal transmitted between the first coil 41 and the second coil 42 .
  • CMTI common mode transient immunity
  • the isolation chip 80 of the embodiment With the isolation chip 80 of the embodiment, the area of the second coil 42 and the first coil 41 in plan view is reduced. Thus, the isolation chip 80 reduces the parasitic capacitance between the second coil 42 and the first coil 41 . This reduces noise on a signal transmitted between the first coil 41 and the second coil 42 , thereby improving the common mode transient immunity (CMTI) of signal transmission. In other words, the signal transmission property of the signal transmission the isolation chip 80 and the signal transmission device 100 is improved.
  • CMTI common mode transient immunity
  • the isolation chip 80 As described above, in the isolation chip 80 , the area of the second coil 42 and the first coil 41 in plan view is reduced. Hence, the isolation chip 80 is reduced in size. In addition, while minimizing an increase in the size of the isolation chip 80 , the number of the first coils 41 and the second coils 42 formed in the isolation chip 80 is increased. This allows for an increase in the number of signals transmitted in a single isolation chip 80 .
  • FIG. 17 is a schematic diagram used to illustrate inspection of the isolation chip 80 .
  • FIG. 17 shows the first coil 41 and the second coil 42 of the transformer 40 A and the first coil 41 and the second coil 42 of the transformer 40 B.
  • the first coil 41 of the transformer 40 A has a first end 411 A connected to pads P 11 and P 12 .
  • the first coil 41 of the transformer 40 A includes a second end 412 A connected to a pad P 13 .
  • the first coil 41 of the transformer 40 B includes a second end 412 B connected to the pad P 13 .
  • the first coil 41 of the transformer 40 B includes a first end 411 B connected to pads P 14 and P 15 .
  • the pads P 11 and P 12 correspond to “two first pads P 1 (refer to FIG. 11 ) of the first inner electrode 81 A connected to the transformer 40 A.”
  • the pads P 14 and P 15 correspond to “two first pads P 1 (refer to FIG. 11 ) of the first inner electrode 81 A connected to the transformer 40 B.”
  • the pad P 13 corresponds to the second pad P 2 shown in FIG. 11 .
  • the second coil 42 of the transformer 40 A includes a first end 421 A connected to the pads P 21 and P 22 .
  • the second coil 42 of the transformer 40 A includes a second end 422 A connected to a pad P 23 .
  • the second coil 42 of the transformer 40 B has a second end 422 B connected to the pad P 23 .
  • the second coil 42 of the transformer 40 B includes a first end 421 B connected to pads P 24 and P 25 .
  • the pads P 21 and P 22 correspond to “two third pads P 1 (refer to FIG. 11 ) of the second inner electrode 82 A connected to the transformer 40 A.”
  • the pads P 24 and P 25 correspond to “two third pads P 1 (refer to FIG. 11 ) of the second inner electrode 82 A connected to the transformer 40 B.”
  • the pad P 23 corresponds to the fourth pad P 4 shown in FIG. 11 .
  • a constant current source 901 and a voltmeter 902 are used to inspect the isolation chip 80 .
  • the constant current source 901 is used to sequentially apply a constant current to the first coil 41 and the second coil 42 of the transformer 40 A and the first coil 41 and the second coil 42 of the transformer 40 B.
  • the voltmeter 902 is used to sequentially measure the voltage (potential difference) between the first coil 41 and the second coil 42 of the transformer 40 A and the first coil 41 and the second coil 42 of the transformer 40 B.
  • the state (satisfactory or not satisfactory) of the isolation chip 80 is determined based on the measurement results.
  • the constant current source 901 is connected between the pad P 12 and the pad P 13 and applies a constant current to the first coil 41 of the transformer 40 A. As a result, a potential difference is generated between the pad P 12 and the pad P 13 in accordance with the constant current flowing to the first coil 41 and the resistance components of the pads P 12 and P 13 .
  • the voltmeter 902 is connected between the pad P 11 and the pad P 15 , and the voltage (potential difference) between the two terminals of the first coil 41 is measured by the voltmeter 902 . Based on the measured voltage, an anomaly in the resistance value of the first coil 41 of the transformer 40 A is determined. Examples of such an anomaly include a disconnection between the pads P 11 and P 15 and a short in the winding of the first coil 41 . With this inspection, a defective isolation chip 80 is appropriately rejected.
  • the second end 412 A of the first coil 41 may be provided with two pads.
  • the pad P 15 is connected to the second end 412 A of the first coil 41 of the transformer 40 A through the first coil 41 of the transformer 40 B.
  • the constant current flows to only the first coil 41 of the transformer 40 A and does not flow to the first coil 41 of the transformer 40 B.
  • the potential of the pad P 15 is substantially equal to the potential of the second end 412 A of the first coil 41 .
  • the isolation chip 80 is reduced in size as compared to when the second end of the first coil 41 is provided with two pads.
  • the constant current source 901 is connected between the pad P 14 and the pad P 13 and applies a constant current to the first coil 41 of the transformer 40 B.
  • the voltmeter 902 connected between the pad P 11 and the pad P 15 is used to measure the voltage (potential difference) between the two terminals of the first coil 41 .
  • the state of the first coil 41 of the transformer 40 B is determined. This dispenses with the task for changing the connection of the voltmeter 902 .
  • the state of the second coil 42 of the transformer 40 A is determined based on voltage measured by the voltmeter 902 connected to the pads P 21 and P 25 .
  • the state of the second coil 42 of the transformer 40 B is determined based on voltage measured by the voltmeter 902 connected to the pads P 21 and P 25 .
  • the signal transmission device 100 has the following advantages.
  • the isolation chip 80 having the configuration described above, the inner region 42 A surrounded by the second coil 42 is decreased in size in plan view as compared to, for example, a configuration in which the second coil 42 is formed to surround the second electrode 82 . Ultimately, the area of the second coil 42 in plan view is reduced. The first coil 41 is opposed to the second coil 42 in the Z-direction. This decreases the area of the first coil 41 in plan view.
  • the embodiments may be modified, for example, as follows.
  • the above embodiment and the modified examples described below may be combined as long as there is no technical contradiction.
  • the same reference characters are given to those components that are the same as the corresponding components of the above embodiments. Such components will not be described in detail.
  • the configuration of the isolation chip 80 may be changed.
  • an isolation chip 400 includes a second inner electrode 401 .
  • the second inner electrode 401 may include two electrode plates 402 and 403 .
  • the two electrode plates 402 and 403 each extend over the inner region 42 A surrounded by the second coil 42 and the region 42 B overlapping the second coil 42 in plan view.
  • the two electrode plates 402 and 403 each are electrically connected to the inner end wire 46 A by a via 92 A.
  • the second inner openings 163 are formed in the passivation film 160 to partially expose the two electrode plates 402 and 403 , respectively.
  • the second inner electrode 401 includes the two electrode plates 402 and 403
  • generation of an eddy current in the second inner electrode 401 is limited.
  • a transmission pulse signal causes current to flow through the first coil 41 and generates a magnetic flux
  • the magnetic flux causes a signal to transmit from the first coil 41 to the second coil 42 .
  • An eddy current results in a loss of the magnetic flux generated by the current flowing through the first coil 41 , thereby decreasing the efficiency of the magnetic coupling between the first coil 41 and the second coil 42 . Since generation of an eddy current is limited, the loss of the magnetic flux is reduced, and the efficiency of the magnetic coupling is improved. Thus, the transmission property between the first coil 41 and the second coil 42 is improved.
  • an isolation chip 410 includes the second inner electrode 401 and an inner end wire 411 .
  • the second inner electrode 401 includes two electrode plates 402 and 403 .
  • the inner end wire 411 has a slit 412 extending from a center C 1 of the second coil 42 to an outer side of the second coil 42 .
  • the slit 412 limits generation of an eddy current in the inner end wire 411 .
  • the transmission property between the first coil 41 and the second coil 42 is improved as compared to the isolation chip 410 shown in FIG. 18 and FIG. 19 .
  • an isolation chip 420 includes a second inner electrode 421 .
  • the second inner electrode 421 includes two electrode plates 422 and 423 and a narrow portion 424 between the two electrode plates 422 and 423 .
  • the narrow portion 424 has a smaller width than a portion of the second inner electrode 421 located between the second inner openings 163 , which partially expose the electrode plates 422 and 423 , where the second inner openings 163 are formed in the Y-direction.
  • the narrow portion 424 electrically connects the electrode plates 422 and 423 . This allows the electrode plates 422 and 423 to have the same potential.
  • the narrow portion 424 is displaced from the center C 1 of the second coil 42 in the Y-direction.
  • the narrow portion 424 overlaps the inner end wire 46 A in plan view.
  • the position of the narrow portion 424 may be changed.
  • the narrow portion 424 may be arranged, for example, so as not to overlap the inner end wire 46 A in plan view.
  • the isolation chip 420 limits generation of an eddy current in the second inner electrode 421 , thereby improving the transmission property between the first coil 41 and the second coil 42 .
  • an isolation chip 430 includes the second inner electrode 421 and the inner end wire 411 .
  • the second inner electrode 421 includes two electrode plates 422 and 423 and a narrow portion 424 between the two electrode plates 422 and 423 .
  • the inner end wire 411 has a slit 412 .
  • the isolation chip 430 further limits generation of an eddy current, thereby improving the transmission property between the first coil 41 and the second coil 42 .
  • the second inner electrode 82 A may be partially exposed from a single second inner opening 163 . That is, the passivation film 160 includes one second inner opening 163 partially exposing the second inner electrode 82 A. The second inner opening 163 extends above the second inner electrode 82 A, and over the inner region 42 A and the region 42 B, which overlaps the second coil 42 . The first inner electrode 81 A may be partially exposed from a single first inner opening 161 . The passivation film 160 includes one first inner opening 161 partially exposing the first inner electrode 81 A.
  • an isolation chip 450 includes a second inner electrode 451 .
  • the second inner electrode 451 may be rectangular and longer in the Y-direction than in the X-direction.
  • the second outer electrode 82 C which is located between the two second coils 42 , may be displaced from the center C 1 of the second coil 42 in the Y-direction.
  • the second outer electrode 82 C may coincide with the center C 1 of the second coil 42 in the Y-direction.
  • an isolation chip 460 includes a first inner electrode 461 and a second inner electrode 462 .
  • the first inner electrode 461 may be square and equal in length in the X-direction and the Y-direction. In the same manner as the embodiment, the first inner electrode 461 may be rectangular and elongated in the X-direction.
  • the second inner electrode 462 may be square and equal in length in the X-direction and the Y-direction. In this configuration, the second inner electrode 462 is displaced from the center C 1 of the second coil 42 in the X-direction. In an example, the second inner electrode 462 is located toward the second outer electrode 82 C.
  • the second inner electrode 462 may be displaced from the center C 1 of the second coil 42 toward a side opposite to the second outer electrode 82 C. In other words, the second inner electrode 462 is located away from the second outer electrode 82 C. In the X-direction, the position of the first inner electrode 461 may be the same as or different from the position of the second inner electrode 462 .
  • an isolation chip 470 includes a first inner electrode 471 and a second inner electrode 472 .
  • the first inner electrode 471 may be square and equal in length in the X-direction and the Y-direction. In the same manner as the embodiment, the first inner electrode 471 may be rectangular and elongated in the X-direction.
  • the second inner electrode 472 may be square and equal in length in the X-direction and the Y-direction.
  • the second inner electrode 472 may be displaced from the center C 1 of the second coil 42 in the Y-direction. In an example, the second inner electrode 472 may be displaced from the center C 1 of the second coil 42 toward a side opposite to the first inner electrode 471 . In other words, the second inner electrode 472 is located away from the first inner electrode 471 .
  • the position of the first inner electrode 471 may be the same as or different from the position of the second inner electrode 472 .
  • the second coil 42 may have any shape in plan view.
  • an isolation chip 480 includes transformers 40 A and 40 B, each of which includes a first coil 481 and a second coil 482 .
  • the first coil 481 and the second coil 482 may each have an oblong spiral shape that is greater in the Y-direction than the X-direction.
  • the shape of the first coil 41 and the second coil 42 in plan view may be a circle, an oblong, an ellipse, a polygon (octagon), or any other shape.
  • an isolation chip 490 includes transformers 40 A and 40 B, each of which includes a first coil 491 and a second coil 492 .
  • the second coil 492 may overlap the second outer electrode 82 C in plan view.
  • the number of wiring turns in the first coil 491 and the second coil 492 is increased to increase the amount of magnetic flux, thereby improving the magnetic coupling.
  • the size of the first coil 491 and the second coil 492 may be the same as the size of the first coil 41 and the second coil 42 in the embodiment. In this case, the distance between the second coil 492 of the transformer 40 A and the second coil 492 of the transformer 40 B may be shortened to reduce the size of the isolation chip 490 .
  • an isolation chip 500 includes a first inner electrode 501 and a second inner electrode 502 .
  • the first inner electrode 501 and the second inner electrode 502 are formed on the upper surface 84 s of the insulation layer 84 .
  • the insulation film 85 U of the insulation layer 84 includes an opening 85 U 1 partially exposing the upper surface of the interconnect piece 134 A.
  • the first inner electrode 501 is in contact with the upper surface of the interconnect piece 134 A in the opening 85 U 1 of the insulation film 85 U and is electrically connected to the interconnect piece 134 A.
  • the insulation film 85 U of the insulation layer 84 includes an opening 85 U 2 partially exposing the upper surface of the inner end wire 46 A.
  • the second inner electrode 502 is in contact with the upper surface of the inner end wire 46 A in the opening 85 U 2 of the insulation film 85 U and is electrically connected to the inner end wire 46 A.
  • the first outer electrode 81 C may have the same configuration as the first inner electrode 501 .
  • the second outer electrode 82 C may have the same configuration as the second inner electrode 502 .
  • the electrical configuration of the first circuit chip 60 and the second circuit chip 70 may be changed in any manner.
  • FIG. 34 is a schematic diagram showing the electrical configuration of a signal transmission device 600 in a modified example.
  • the signal transmission device 600 of the modified example includes the transmission circuit 11 , transformers 40 ( 40 A, 40 B), and a reception circuit 610 .
  • the reception circuit 610 is included in the second circuit chip 70 shown in FIG. 1 .
  • the reception circuit 12 of the first circuit chip 60 shown in FIG. 1 may have the same configuration as the reception circuit 610 .
  • the transmission circuit 11 uses at least one of a rising edge and a falling edge of the input pulse signal Din as a trigger to generate the transmission pulse signal S 11 .
  • the transmission pulse signal S 11 may include at least one of a first transmission pulse signal S 11 R generated when the trigger is the rising edge of the input pulse signal Din and a second transmission pulse signal S 11 F generated when the trigger is the falling edge of the input pulse signal Din.
  • the transformers 40 transmit the transmission pulse signal S 11 as a reception pulse signal S 12 while electrically isolating the transmission circuit 11 from the reception circuit 610 .
  • the reception pulse signal S 12 may include at least one of a first reception pulse signal S 12 R corresponding to the first transmission pulse signal S 11 R and a second reception pulse signal S 12 F corresponding to the second transmission pulse signal S 11 F.
  • the reception circuit 610 includes a high-pass filter 611 , a DC bias circuit 612 , an envelope detection circuit 613 , an addition circuit 614 , and a comparison circuit 615 .
  • the high-pass filter 611 blocks low-frequency components of the reception pulse signal S 12 that are lower than the cut-off frequency fc, and passes high-frequency components of the reception pulse signal S 12 that are higher than the cut-off frequency fc to generate a filtered reception pulse signal S 13 .
  • the filtered reception pulse signal S 13 may include a filtered reception pulse signal S 13 R corresponding to the first reception pulse signal S 12 R and a filtered reception pulse signal S 13 F corresponding to the second reception pulse signal S 12 F.
  • the DC bias circuit 612 is connected to an output end of the high-pass filter 611 and sets a DC-bias of the filtered reception pulse signal S 13 .
  • the envelope detection circuit 613 generates a positive envelope signal S 14 P and a negative envelope signal S 14 N from the filtered reception pulse signal S 13 .
  • the envelope detection circuit 613 includes, for example, a positive envelope detection circuit exhibiting high responsiveness to only a positive voltage waveform of the filtered reception pulse signal S 13 with respect to the DC bias, and a negative envelope detection circuit exhibiting high responsiveness to only a negative voltage waveform of the filtered reception pulse signal S 13 with respect to the DC bias.
  • the addition circuit 614 receives the positive envelope signal S 14 P and the negative envelope signal S 14 N to generate the addition envelope signal S 15 .
  • the addition circuit 614 may be, for example, an addition amplifier that inverts one of the positive envelope signal S 14 P and the negative envelope signal S 14 N and adds the inverted signal to the other to generate the addition envelope signal S 15 .
  • the comparison circuit 615 compares the addition envelope signal S 15 with a predetermined threshold value to generate the output pulse signal Dout.
  • FIG. 35 is an example of a detailed electrical configuration of the signal transmission device 600 shown in FIG. 34 .
  • the transmission circuit 11 generates the first transmission pulse signal S 11 R when the trigger is the rising edge of the input pulse signal Din, and the second transmission pulse signal S 11 F when the trigger is the falling edge of the input pulse signal Din.
  • the first transmission pulse signal S 11 R may include one or more pulses.
  • the second transmission pulse signal S 11 F may include one or more pulses.
  • the transformers 40 transmit the first transmission pulse signal S 11 R as the first reception pulse signal S 12 R while electrically isolating the transmission circuit 11 from the reception circuit 610 .
  • the transformers 40 B transmit the second transmission pulse signal S 11 F to the second reception pulse signal S 12 F while electrically isolating the transmission circuit 11 from the reception circuit 610 .
  • the reception circuit 610 includes high-pass filters 611 R and 611 F, DC bias circuits 612 R and 612 F, envelope detection circuits 613 R and 613 F, an addition circuit 614 , and a comparison circuit 615 .
  • the high-pass filter 611 R blocks low-frequency components of the first reception pulse signal S 12 R that are lower than the cut-off frequency fc, and passes high-frequency components of the first reception pulse signal S 12 R that are higher than the cut-off frequency fc to generate a filtered first reception pulse signal S 13 R.
  • the high-pass filter 611 F blocks low-frequency components of the second reception pulse signal S 12 F that are lower than the cut-off frequency fc and passes high-frequency components of the second reception pulse signal S 12 F that are higher than the cut-off frequency fc to generate a filtered second reception pulse signal S 13 F.
  • the DC bias circuit 612 R is connected to an output end of the high-pass filter 611 R and sets a DC-bias of the filtered first reception pulse signal S 13 R.
  • the DC bias circuit 612 F is connected to an output end of the high-pass filter 611 F and sets a DC-bias of the filtered second reception pulse signal S 13 F.
  • the envelope detection circuit 613 R detects a positive-side envelope from the filtered first reception pulse signal S 13 R, which oscillates positively and negatively with respect to the DC bias as the reference potential, to generate a first positive envelope signal S 14 RP.
  • the envelope detection circuit 613 R also detects a negative-side envelope from the filtered first reception pulse signal S 13 R, which oscillates positively and negatively with respect to the DC bias as the reference potential, to generate a first negative envelope signal S 14 RN.
  • the envelope detection circuit 613 F detects a positive-side envelope from the filtered second reception pulse signal S 13 F, which oscillates positively and negatively with respect to the DC bias as the reference potential, to generate a second positive envelope signal S 14 FP.
  • the envelope detection circuit 613 F also detects a negative-side envelope from the filtered first reception pulse signal S 13 F, which oscillates positively and negatively with respect to the DC bias as the reference potential, to generate a second negative envelope signal S 14 FN.
  • the addition circuit 614 is configured to receive the first positive envelope signal S 14 RP, the first negative envelope signal S 14 RN, the second positive envelope signal S 14 FP, and the second negative envelope signal S 14 FN and serves as a signal amplifier and an in-phase noise canceler.
  • the addition circuit 614 inverts and adds the second positive envelope signal S 14 FP to the first positive envelope signal S 14 RP to generate a first addition envelope signal S 15 R.
  • the addition circuit 614 inverts and adds the second negative envelope signal S 14 FN to the first negative envelope signal S 14 RN to generate a second addition envelope signal S 15 F.
  • the addition circuit 614 may be, for example, a differential-input addition amplifier.
  • the comparison circuit 615 may include a differential-input hysteresis comparator.
  • the comparison circuit 615 also serves as an in-phase noise canceler for each of the first addition envelope signal S 15 R and the second addition envelope signal S 15 F.
  • the reception circuit 610 of the comparative example which differs from the reception circuit 21 (refer to FIG. 15 ) of the nonlinear amplifiers 303 R and 303 F, does not experience undershoot during application of a signal. This eliminates the need for measures (e.g., subtraction circuit 305 described above) for mitigating undershoot.
  • FIG. 36 is a diagram showing an exemplary configuration of the envelope detection circuit 613 and the addition circuit 614 .
  • the envelope detection circuit 613 R includes transistors 613 a and 613 b, current sources 613 c and 613 d, and capacitors 613 e and 613 f.
  • the transistor 613 a is, for example, an NPN transistor.
  • the transistor 613 b is, for example, a PNP transistor.
  • the second voltage V 2 is applied to a collector terminal of the transistor 613 a.
  • the filtered first reception pulse signal S 13 R is input to a gate terminal of the transistor 613 a.
  • An emitter terminal of the transistor 613 a is connected to a first end of the current source 613 c and a first end of the capacitor 613 e.
  • the current source 613 c generates a constant current that is set to a sufficiently small value.
  • the capacitor 613 e may be a parasitic capacitance.
  • a second end of the current source 613 c and a second end of the capacitor 613 e are connected to the second ground GND 2 .
  • the second ground GND 2 is connected to a collector terminal of the transistor 613 b.
  • the filtered first reception pulse signal S 13 R is input to a gate terminal of the transistor 613 b.
  • An emitter terminal of the transistor 613 b is connected to a second end of the current source 613 d and a second end of the capacitor 613 f.
  • the second voltage V 2 is applied to a first end of the current source 613 d and a first end of the capacitor 613 f.
  • the current source 613 d generates a constant current that is set to a sufficiently small value.
  • the capacitor 613 f may be a parasitic capacitance.
  • the positive envelope detection circuit 613 RP and the negative envelope detection circuit 613 RN each include an emitter follower to achieve high responsiveness.
  • the transistors 613 a and 613 b may each be a MOSFET.
  • the positive envelope detection circuit 613 RP and the negative envelope detection circuit 613 RN may each include a source follower.
  • the positive envelope detection circuit 613 RP and the negative envelope detection circuit 613 RN which have the circuit configuration described above, differ in drive performance in accordance with the positive and negative polarities of the filtered first reception pulse signal S 13 R.
  • the positive envelope detection circuit 613 RP is highly responsive to only a positive voltage of the filtered first reception pulse signal S 13 R with respect to the DC bias to generate the first positive envelope signal S 14 RP.
  • the negative envelope detection circuit 613 RN is highly responsive to only a negative voltage of the filtered first reception pulse signal S 13 R with respect to the DC bias to generate the first negative envelope signal S 14 RN.
  • the envelope detection circuit 613 F basically has the same configuration as the envelope detection circuit 613 R.
  • the envelope detection circuit 613 F responds to the filtered second reception pulse signal S 13 F to generate the second positive envelope signal S 14 FP and the second negative envelope signal S 14 FN.
  • the addition circuit 614 includes transistors 614 a to 614 h and current sources 614 i and a 614 j.
  • the transistors 614 a to 614 f each are, for example, a PNP transistor.
  • the transistors 614 g and 614 h each are, for example, an NPN transistor.
  • the second voltage V 2 is applied to a first end of the current source 614 i.
  • a second end of the current source 614 i is connected to an emitter terminal of each of the transistors 614 a and 614 b.
  • the first negative envelope signal S 14 RN is input to a base terminal of the transistor 614 a .
  • the second negative envelope signal S 14 FN is input to a base terminal of the transistor 614 b.
  • a collector terminal of the transistor 614 a is connected to a collector terminal of the transistor 614 f .
  • a collector terminal of the transistor 614 b is connected to a collector terminal of the transistor 614 c.
  • the second voltage V 2 is applied to an emitter terminal of each of the transistors 614 c to 614 f.
  • a base terminal of each of the transistors 614 c and 614 d is connected to a collector terminal of the transistor 614 d.
  • a collector terminal of the transistor 614 d is connected to a collector terminal of the transistor 614 g.
  • a base of each of the transistors 614 e and 614 f is connected to a collector terminal of the transistor 614 e.
  • a collector terminal of the transistor 614 e is connected to a collector terminal of the transistor 614 h.
  • An emitter terminal of each of the transistors 614 g and 614 h is connected to a first end of the current source 614 j.
  • the second ground GND 2 is connected to a second end of the current source 614 j.
  • the first positive envelope signal S 14 RP is input to a base terminal of the transistor 614 g.
  • the second positive envelope signal S 14 FP is input to a base terminal of the transistor 614 h.
  • the addition circuit 614 outputs the first addition envelope signal S 15 R from a connection point of the collector terminal of each of the transistors 614 b and 614 c and outputs the second addition envelope signal S 15 F from a connection point of the collector terminal of each of the transistors 614 a and 614 f.
  • the input stage of the addition circuit 614 includes a differential pair of the transistors 614 a and 614 b and a differential pair of the transistors 614 g and 614 h.
  • the transistors 614 a , 614 b, 614 g, and 614 h are each a bipolar transistor.
  • the addition circuit 614 limits variations in offset and sensitivity as compared to the reception circuit 21 (refer to FIG. 15 ) using the nonlinear amplifiers 303 R and 303 F.
  • the addition circuit 614 in the modified example also cancels in-phase noise superimposed on each of the filtered first reception pulse signal S 13 R and the filtered second reception pulse signal S 13 F. This obtains high CMTI.
  • FIG. 37 is an example of signal transmission behavior in the signal transmission device 600 shown in FIG. 35 .
  • FIG. 37 shows, sequentially from above, the input pulse signal Din, the first transmission pulse signal S 11 R, the second transmission pulse signal S 11 F, the filtered first reception pulse signal S 13 R, the filtered second reception pulse signal S 13 F, the first positive envelope signal S 14 RP, the first negative envelope signal S 14 RN, the second positive envelope signal S 14 FP, the second negative envelope signal S 14 FN, the first addition envelope signal S 15 R, the second addition envelope signal S 15 F, and the output pulse signal Dout.
  • the filtered first reception pulse signal S 13 R is indicated by broken lines on each of the first positive envelope signal S 14 RP and the first negative envelope signal S 14 RN.
  • the filtered second reception pulse signal S 13 F is indicated by broken lines on each of the second positive envelope signal S 14 FP and the second negative envelope signal S 14 FN.
  • the first transmission pulse signal S 11 R When the input pulse signal Din rises from the low level to the high level, the first transmission pulse signal S 11 R is generated.
  • the filtered first reception pulse signal S 13 R oscillates positively and negatively, and the first positive envelope signal S 14 RP and the first negative envelope signal S 14 RN are each generated.
  • the second transmission pulse signal S 11 F is generated.
  • the filtered second reception pulse signal S 13 F oscillates positively and negatively, and the second positive envelope signal S 14 FP and the second negative envelope signal S 14 FN are generated.
  • the first addition envelope signal S 15 R has a voltage waveform obtained by inverting and adding the second positive envelope signal S 14 FP to the first positive envelope signal S 14 RP.
  • the second addition envelope signal S 15 F has a voltage waveform obtained by inverting and adding the second negative envelope signal S 14 FN to the first negative envelope signal S 14 RN.
  • the output pulse signal Dout rises from the low level to the high level.
  • the output pulse signal Dout falls from the high level to the low level.
  • a positive envelope and a negative envelope of the filtered first reception pulse signal S 13 R and the filtered second reception pulse signal S 13 F, which oscillate positively and negatively, are separately detected and added together. This increases the signal amplitude, thereby obtaining high CMTI.
  • FIG. 38 shows an example of the configuration of the high-pass filter 611 R and the DC bias circuit 612 R.
  • the high-pass filter 611 R includes a capacitor 611 a and a buffer circuit 611 b .
  • the buffer circuit 611 b may be considered to be an element of the DC bias circuit 612 R.
  • the first reception pulse signal S 12 R is input to a first end of the capacitor 611 a.
  • the buffer circuit 611 b includes an output terminal connected to a second end of the capacitor 611 a .
  • the output terminal of the buffer circuit 611 b is connected to an inverting input terminal of the buffer circuit 611 b.
  • the buffer circuit 611 b includes a non-inverting input terminal connected to a positive terminal of a bias power supply 612 a.
  • the second ground GND 2 is connected to a negative terminal of the bias power supply 612 a.
  • the bias power supply 612 a applies a bias voltage Vb to the non-inverting input terminal of the buffer circuit 611 b.
  • the high-pass filter 611 F and the DC bias circuit 612 F basically have the same configuration as described above and will not be described in detail.
  • FIG. 39 shows a circuit equivalent to the high-pass filter 611 R.
  • the buffer circuit 611 b shown in FIG. 38 is equivalent to an output impedance model that includes an inductance 611 c and a resistor 611 d.
  • the high-pass filter 611 R may be considered to be a second-order LCR filter.
  • FIG. 40 shows the output impedance characteristic of the buffer circuit 611 b. As shown in FIG. 40 , the horizontal axis represents a frequency f, and the vertical axis represents an output impedance Zo of the buffer circuit 611 ⁇ b.
  • the buffer circuit 611 b acts as a resistive load in an in-phase noise region.
  • the buffer circuit 611 b has an output impedance Zo that is constant and independent from the frequency f.
  • the buffer circuit 611 b acts as an inductive load in an in-phase noise region. More specifically, the output impedance Zo of the buffer circuit 611 b is increased as the frequency f increases.
  • the high-pass filters 611 R and 611 F are combined with the DC bias circuits 612 R and 612 F (i.e., active pass filter).
  • the adding process of the addition circuit 614 may be changed.
  • FIG. 41 is a diagram showing a modified example of the adding process of the addition circuit 614 .
  • FIG. 41 shows, sequentially from above, the input pulse signal Din, the first transmission pulse signal S 11 R, the second transmission pulse signal S 11 F, the filtered first reception pulse signal S 13 R, the filtered second reception pulse signal S 13 F, the first positive envelope signal S 14 RP, the first negative envelope signal S 14 RN, the second positive envelope signal S 14 FP, the second negative envelope signal S 14 FN, the first addition envelope signal S 15 R, and the second addition envelope signal S 15 F.
  • the filtered first reception pulse signal S 13 R is indicated by broken lines on each of the first positive envelope signal S 14 RP and the first negative envelope signal S 14 RN.
  • the filtered second reception pulse signal S 13 F is indicated by broken lines on each of the second positive envelope signal S 14 FP and the second negative envelope signal S 14 FN.
  • the addition circuit 614 may invert and add the first negative envelope signal S 14 RN to the first positive envelope signal S 14 RP to generate the first addition envelope signal S 15 R.
  • the addition circuit 614 may invert and add the second positive envelope signal S 14 FP to the second negative envelope signal S 14 FN to generate the second addition envelope signal S 15 F.
  • the comparison circuit 615 may be a single-input comparator.
  • the first support member 210 and the second support member 220 may be changed.
  • FIG. 42 is a schematic plan view showing the configuration of a signal transmission device 700 in a modified example.
  • the signal transmission device 700 of the modified example differs in the shapes of the first support member 210 and the second support member 220 from the signal transmission device 100 shown in FIG. 2 .
  • the first die pad 211 is connected to the first lead terminal 212 A and a first lead terminal 212 B located at a side of the first die pad 211 opposite from the first lead terminal 212 in the X-direction.
  • the first die pad 211 and the first lead terminals 212 A and 212 B are formed integrally as an integrated structure. As viewed in the Y-direction, the first die pad 211 is located between the first lead terminals 212 A and 212 B.
  • the second die pad 221 is connected to the second lead terminal 222 A and a second lead terminal 222 B located at a side of the second die pad 221 opposite from the second lead terminal 222 A in the X-direction.
  • the second die pad 221 and the second lead terminals 222 A and 222 B are formed integrally as an integrated structure. As viewed in the Y-direction, the second die pad 221 is located between the second lead terminals 222 A and 222 B.
  • the first die pad 211 is supported by two first lead terminals 212 A and 212 B.
  • the first circuit chip 60 and the isolation chip 80 are readily mounted on the first die pad 211 .
  • the second die pad 221 is supported by the two second lead terminals 222 A and 222 B.
  • the second circuit chip 70 is readily mounted on the second die pad 221 .
  • the configuration of the signal transmission device may be changed.
  • Multiple isolation chips may be used to transmit a signal between the first circuit chip 60 and the second circuit chip 70 .
  • FIG. 43 shows an example of the electrical configuration of a signal transmission device 710 in a modified example.
  • FIG. 44 shows the schematic configuration of the signal transmission device 710 shown in FIG. 43 .
  • the signal transmission device 710 includes the first circuit chip 60 , the second circuit chip 70 , and second isolation chips 711 and 712 .
  • the two isolation chips 711 and 712 have the same configuration as the isolation chip 80 .
  • a pulse signal is output from the transmission circuit 11 in the first circuit chip 60 and is transmitted to the reception circuit 21 of the second circuit chip 70 through the transformers 40 A and 40 B of the first isolation chip 711 and the transformers 40 A and 40 B of the second isolation chip 712 .
  • a pulse signal is output from the transmission circuit 22 in the second circuit chip 70 and is transmitted to the reception circuit 12 of the first circuit chip 60 through the transformers 40 A and 40 B of the second isolation chip 712 and the transformers 40 A and 40 B of the first isolation chip 711 .
  • the first circuit chip 60 , the first isolation chip 711 , the second isolation chip 712 , and the second circuit chip 70 are separated from each other in the Y-direction.
  • the first circuit chip 60 , the first isolation chip 711 , the second isolation chip 712 , and the second circuit chip 70 are arranged in the X-direction, in which the first die pad 211 and the second die pad 221 are arranged.
  • the first circuit chip 60 , the first isolation chip 711 , the second isolation chip 712 , and the second circuit chip 70 are arranged in this order from the first lead terminals 212 toward the second lead terminals 222 .
  • the first circuit chip 60 and the first isolation chip 711 are mounted on the first die pad 211 of the first support member 210 .
  • the second circuit chip 70 and the second isolation chip 712 are mounted on the second die pad 221 of the second support member 220 .
  • the first electrodes 81 of the second isolation chip 712 are electrically connected to the second circuit chip 70 by wires W 3 .
  • the second electrodes 82 of the second isolation chip 712 are electrically connected to the second electrodes 82 of the first isolation chip 711 by wires W 5 .
  • the first isolation chip 711 and the second isolation chip 712 are connected to each other in series between the first circuit chip 60 and the second circuit chip 70 .
  • the second isolation chip 712 has the same configuration as the first isolation chip 711 .
  • the second isolation chip 712 and the first isolation chip 711 have a similar breakdown voltage.
  • the signal transmission device 710 has a breakdown voltage corresponding to the breakdown voltages of the first isolation chip 711 and the second isolation chip 712 , which are connected in series.
  • a signal transmission device 720 differs in the shapes of the first support member 210 and the second support member 220 from the signal transmission device 710 shown in FIG. 44 .
  • the first die pad 211 may be connected to the two first lead terminals 212 A and 212 B.
  • the second die pad 221 may be connected to the two second lead terminals 222 A and 222 B.
  • FIG. 46 shows a signal transmission device 730 that includes an isolation chip 731 mounted on the first die pad 211 and the second circuit chip 70 mounted on the second die pad 221 .
  • the isolation chip 731 includes a first circuit 732 and the multiple transformers 40 .
  • the first circuit 732 may include the transmission circuit 11 and the reception circuit 12 shown in FIG. 1 .
  • the isolation chip 731 includes the first electrodes 61 , the second electrodes 62 , and the second electrodes 82 in the same manner as the first circuit chip 60 and the isolation chip 80 shown in FIG. 2 .
  • the isolation chip 731 may include the third electrodes 63 and the first electrodes 81 shown in FIG. 2 .
  • the isolation chip 731 and the second circuit chip 70 are mounted on the first die pad 211 and the second die pad 221 , respectively. This simplifies the mounting.
  • the isolation chip 731 includes the transformers 40 and the first circuit 732 . This eliminates the need for the wires W 2 shown in FIG. 2 .
  • FIG. 47 shows a signal transmission device 740 that includes a first isolation chip 741 mounted on the first die pad 211 and a second isolation chip 742 mounted on the second die pad 221 .
  • the first isolation chip 741 includes a first circuit 743 and the multiple transformers 40 .
  • the first circuit 743 may include the transmission circuit 11 and the reception circuit 12 shown in FIG. 1 .
  • the first isolation chip 741 includes the first electrodes 61 , the second electrodes 62 , the first electrodes 81 , and the second electrodes 82 in the same manner as the first circuit chip 60 and the isolation chip 80 shown in FIG. 2 .
  • the first isolation chip 741 may include the third electrodes 63 of the first circuit chip 60 shown in FIG. 2 .
  • the second isolation chip 742 includes the second circuit 744 and the multiple transformers 40 .
  • the second circuit 744 may include the reception circuit 21 and the transmission circuit 22 shown in FIG. 1 .
  • the second isolation chip 742 includes the first electrodes 71 , the second electrodes 72 , the first electrodes 81 , and the second electrodes 82 in the same manner as the second circuit chip 70 and the isolation chip 80 shown in FIG. 2 .
  • the second isolation chip 742 may include the third electrodes 73 of the second circuit chip 70 shown in FIG. 2 .
  • the first isolation chip 741 and the second isolation chip 742 are mounted on the first die pad 211 and the second die pad 221 , respectively. This simplifies the mounting.
  • the first isolation chip 741 includes the transformers 40 and the first circuit 743 .
  • the second isolation chip 742 includes the transformers 40 and the second circuit 744 . This eliminates the need for the wires W 2 and W 3 shown in FIG. 44 .
  • the term “on” includes the meaning of “above” in addition to the meaning of “on” unless otherwise clearly indicated in the context. Accordingly, a phrase such as “first layer formed on second layer” may mean that the first layer is formed directly contacting the second layer in one embodiment and that the first layer is located above the second layer without contacting the second layer in another embodiment. Thus, the word “on” will also allow for a structure in which another layer is arranged between the first layer and the second layer.
  • the Z-axis direction as referred to in the present disclosure does not necessarily have to be the vertical direction and does not necessarily have to fully conform to the vertical direction.
  • “upward” and “downward” in the Z-axis direction as referred to in the present description are not limited to “upward” and “downward” in the vertical direction.
  • the X-axis direction may be the vertical direction.
  • the Y-axis direction may be the vertical direction.

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