JPWO2024195396A1 - - Google Patents
Info
- Publication number
- JPWO2024195396A1 JPWO2024195396A1 JP2025508236A JP2025508236A JPWO2024195396A1 JP WO2024195396 A1 JPWO2024195396 A1 JP WO2024195396A1 JP 2025508236 A JP2025508236 A JP 2025508236A JP 2025508236 A JP2025508236 A JP 2025508236A JP WO2024195396 A1 JPWO2024195396 A1 JP WO2024195396A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/20—Inductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/811—Multiple chips on leadframes
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2023043192 | 2023-03-17 | ||
| PCT/JP2024/005817 WO2024195396A1 (ja) | 2023-03-17 | 2024-02-19 | 絶縁チップおよび信号伝達装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPWO2024195396A1 true JPWO2024195396A1 (https=) | 2024-09-26 |
| JPWO2024195396A5 JPWO2024195396A5 (https=) | 2025-12-05 |
Family
ID=92841358
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2025508236A Pending JPWO2024195396A1 (https=) | 2023-03-17 | 2024-02-19 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US20260011695A1 (https=) |
| JP (1) | JPWO2024195396A1 (https=) |
| WO (1) | WO2024195396A1 (https=) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8665054B2 (en) * | 2012-04-20 | 2014-03-04 | Infineon Technologies Austria Ag | Semiconductor component with coreless transformer |
| KR20150096391A (ko) * | 2012-12-19 | 2015-08-24 | 르네사스 일렉트로닉스 가부시키가이샤 | 반도체장치 |
| DE112018004478B4 (de) * | 2017-10-13 | 2025-03-27 | Rohm Co., Ltd. | Elektronikkomponente |
| WO2022210541A1 (ja) * | 2021-03-29 | 2022-10-06 | ローム株式会社 | 絶縁トランス |
-
2024
- 2024-02-19 WO PCT/JP2024/005817 patent/WO2024195396A1/ja not_active Ceased
- 2024-02-19 JP JP2025508236A patent/JPWO2024195396A1/ja active Pending
-
2025
- 2025-09-10 US US19/324,252 patent/US20260011695A1/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| US20260011695A1 (en) | 2026-01-08 |
| WO2024195396A1 (ja) | 2024-09-26 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20250910 |