US20220148951A1 - Semiconductor device including an antenna - Google Patents

Semiconductor device including an antenna Download PDF

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Publication number
US20220148951A1
US20220148951A1 US17/544,221 US202117544221A US2022148951A1 US 20220148951 A1 US20220148951 A1 US 20220148951A1 US 202117544221 A US202117544221 A US 202117544221A US 2022148951 A1 US2022148951 A1 US 2022148951A1
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Prior art keywords
semiconductor chip
semiconductor device
antenna
layer
conductive layer
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US17/544,221
Inventor
Ngoc-Hoa Huynh
Franz-Xaver Muehlbauer
Claus Waechter
Veronika Theyerl
Dominic Maier
Thomas Kilger
Saverio Trotta
Ashutosh Baheti
Georg Meyer-Berg
Maciej Wojnowski
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Infineon Technologies AG
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Infineon Technologies AG
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Priority to US17/544,221 priority Critical patent/US20220148951A1/en
Assigned to INFINEON TECHNOLOGIES AG reassignment INFINEON TECHNOLOGIES AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HUBER, VERONIKA, Waechter, Claus, KILGER, THOMAS, MAIER, DOMINIC, MUEHLBAUER, FRANZ-XAVER, WOJNOWSKI, MACIEJ, Baheti, Ashutosh, HUYNH, NGOC-HOA, MEYER-BERG, GEORG, TROTTA, SAVERIO
Publication of US20220148951A1 publication Critical patent/US20220148951A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q21/00—Antenna arrays or systems
    • H01Q21/06—Arrays of individually energised antenna units similarly polarised and spaced apart
    • H01Q21/061—Two dimensional planar arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q21/00—Antenna arrays or systems
    • H01Q21/06—Arrays of individually energised antenna units similarly polarised and spaced apart
    • H01Q21/061—Two dimensional planar arrays
    • H01Q21/065—Patch antenna array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q9/00—Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
    • H01Q9/04—Resonant antennas
    • H01Q9/0407—Substantially flat resonant element parallel to ground plane, e.g. patch antenna
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q9/00—Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
    • H01Q9/04—Resonant antennas
    • H01Q9/16—Resonant antennas with feed intermediate between the extremities of the antenna, e.g. centre-fed dipole
    • H01Q9/28—Conical, cylindrical, cage, strip, gauze, or like elements having an extended radiating surface; Elements comprising two conical surfaces having collinear axes and adjacent apices and fed by two-conductor transmission lines
    • H01Q9/285—Planar dipole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6683—High-frequency adaptations for monolithic microwave integrated circuit [MMIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q9/00—Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
    • H01Q9/04—Resonant antennas
    • H01Q9/16—Resonant antennas with feed intermediate between the extremities of the antenna, e.g. centre-fed dipole
    • H01Q9/26—Resonant antennas with feed intermediate between the extremities of the antenna, e.g. centre-fed dipole with folded element or elements, the folded parts being spaced apart a small fraction of operating wavelength
    • H01Q9/265—Open ring dipoles; Circular dipoles

Definitions

  • An eWLB package provides a fan-out area to provide more space for interconnect routing compared to semiconductor device packages without a fan-out area.
  • antennas are used to transmit and receive radio frequency (RF) signals.
  • the antennas may be integrated on a printed circuit board on which an RF semiconductor chip is attached. Integrating antennas on a printed circuit board may be expensive.
  • One example of a semiconductor device includes a semiconductor chip and a redistribution layer on a first side of the semiconductor chip.
  • the redistribution layer is electrically coupled to the semiconductor chip.
  • the semiconductor device includes a dielectric layer and an antenna on the dielectric layer. The dielectric layer is between the antenna and the semiconductor chip.
  • FIG. 1A is a cross-sectional view and FIG. 1B is a top view illustrating of one example of a semiconductor device.
  • FIG. 2A is a cross-sectional view and FIG. 2B is a top view illustrating another example of a semiconductor device.
  • FIG. 3A is a cross-sectional view illustrating another example of a semiconductor device.
  • FIG. 3B is a cross-sectional view illustrating another example of a semiconductor device.
  • FIG. 4 is a cross-sectional view illustrating another example of a semiconductor device.
  • FIG. 5 is a cross-sectional view illustrating another example of a semiconductor device.
  • FIGS. 6A-6D are cross-sectional views illustrating one example of a method for fabricating the semiconductor device illustrated in FIG. 5 .
  • FIGS. 7A-7F illustrate example antenna structures.
  • electrically coupled is not meant to mean that the elements must be directly coupled together and intervening elements may be provided between the “electrically coupled” elements.
  • Electrically coupled elements have a metallic or other electrically conductive material path between the “electrically coupled” elements such that a current may flow from one element to the other element.
  • electromagnetically coupled elements are coupled through an electromagnetic field without a metallic or other electrically conductive material path between the “electromagnetically coupled” elements such that a current cannot flow from one element to the other element.
  • FIG. 1A is a cross-sectional view and FIG. 1B is a top view illustrating one example of a semiconductor device 100 .
  • Semiconductor device 100 is an embedded wafer level ball grid array (eWLB) semiconductor device.
  • Semiconductor device 100 includes a semiconductor chip 102 , an encapsulant material 106 (e.g., a mold compound, a polymer, an epoxy, BT, or a hydrocarbon/ceramic laminate), a redistribution layer 112 , a conductive layer 114 (e.g., ground plane, reflector, or shielding), dielectric layers 108 , 110 , and 126 , patch antennas 118 for transmitting RF signals, patch antennas 130 for receiving RF signals, and solder balls 128 .
  • semiconductor chip 102 is a radio frequency (RF) semiconductor chip for a millimeter wave application, such as gesture sensing at 60 GHz or another suitable application.
  • RF radio frequency
  • a front side (i.e., active side) of semiconductor chip 102 includes contacts 104 .
  • Contacts 104 may be composed of Cu, Al, Au, Ag, W, and/or another suitable metal.
  • Semiconductor chip 102 is laterally surrounded by encapsulant material 106 , such as a mold compound or another suitable encapsulation material, which provides a fan-out area for electrical connections to semiconductor chip 102 .
  • the top surface of dielectric layer 108 contacts the bottom surface of encapsulant material 106 and the front side of semiconductor chip 102 .
  • the bottom surface of dielectric layer 108 contacts the top surface of dielectric layer 110 .
  • each dielectric layer 108 and 110 may be composed of SiO 2 , Si 3 N 4 , or another suitable dielectric material.
  • Redistribution layer 112 is formed on and/or within dielectric layers 108 and 110 .
  • Redistribution layer 112 may be composed of Cu, Al, Au, Ag, W, and/or other suitable metals. Redistribution layer 112 electrically couples contacts 104 to conductive layer 114 , solder balls 128 , and patch antennas 118 and 130 .
  • conductive layer 114 contacts the back side of semiconductor chip 102 and the top surface of encapsulant material 106 .
  • conductive layer 114 covers semiconductor chip 102 and encapsulant material 106 except where electrical connections to patch antennas 118 and 130 extend through conductive layer 114 .
  • Conductive layer 114 is electrically coupled to redistribution layer 112 through vias 116 , which extend through encapsulant material 106 .
  • Conductive layer 114 and vias 116 may be composed of Cu, Al, Au, Ag, W, and/or other suitable metals.
  • dielectric layer 126 contacts the top surface of conductive layer 114 .
  • dielectric layer 126 may be composed of a laminate, an encapsulant material, an imide material, or another suitable dielectric material.
  • a ground line 115 and patch antennas 118 and 130 contact the top surface of dielectric layer 126 .
  • Ground line 115 is electrically coupled to conductive layer 114 through vias 117 (one via 117 is visible in FIG. 1A ), which extend through dielectric layer 126 .
  • Each patch antenna 118 is electrically coupled to redistribution layer 112 through a via 120 , which extends through encapsulant material 106 , a conductive pad 121 on the top surface of encapsulant material 106 , a via 122 , which extends through dielectric layer 126 , and a conductive pad 124 and conductive trace 125 on the top surface of dielectric layer 126 .
  • Each patch antenna 130 is electrically coupled to redistribution layer 112 through a via through encapsulant material 106 (not shown), a conductive pad on the top surface of encapsulant material 106 (not shown), a via through dielectric layer 126 (not shown), and a conductive pad 132 and a conductive trace 133 on the top surface of dielectric layer 126 .
  • vias 120 and 122 , conductive pads 121 , 124 , and 132 , conductive traces 125 and 133 , and patch antennas 118 and 130 may be composed of Cu, Al, Au, Ag, W, and/or other suitable metals.
  • Each via 116 , 120 , and 122 may be rectangular in shape with dimensions (length by width by height) between 50 ⁇ m by 10 ⁇ m by 50 ⁇ m and 150 ⁇ m by 10 ⁇ m by 450 ⁇ m.
  • Each via 116 , 120 , and 122 may be formed using a photolithography, etching, and deposition process; a laser drilling and deposition process; or another suitable process.
  • patch antennas 118 and 130 are within the footprint of semiconductor chip 102 .
  • Patch antennas 118 for transmitting RF signals include two patch antennas separated by ground line 115 .
  • Each patch antenna 118 is arranged at a corner of semiconductor chip 102 .
  • Patch antennas 130 for receiving RF signals include four patch antennas arranged in a square configuration. Patch antennas 130 are separated from patch antennas 118 by ground line 115 . In other examples, patch antennas 118 and 130 may have another suitable arrangement.
  • a compact semiconductor device 100 including integrated RF functionally may be provided. In this way, an application board on which semiconductor device 100 is installed does not require antennas to implement RF functionality.
  • antennas 118 and 130 may include dipole antennas ( FIG. 7A ), folded dipole antennas ( FIG. 7B ), ring antennas ( FIG. 7C ), rectangular loop antennas ( FIG. 7D ), coplanar patch antennas ( FIG. 7F ), slot antennas, or monopole antennas.
  • FIG. 2A is a cross-sectional view and FIG. 2B is a top view illustrating another example of a semiconductor device 200 .
  • Semiconductor device 200 is an eWLB semiconductor device.
  • Semiconductor device 200 includes a semiconductor chip 202 , an encapsulant material 206 , a redistribution layer 212 , a conductive layer 214 (e.g., reflector, ground plane, or shielding), dielectric layers 108 and 110 , dipole antennas 218 for transmitting RF signals, dipole antennas 230 for receiving RF signals, and solder balls 228 .
  • semiconductor chip 202 is a RF semiconductor chip for a millimeter wave application, such as gesture sensing at 60 GHz or another suitable application.
  • a front side (i.e., active side) of semiconductor chip 202 includes contacts 204 .
  • Contacts 204 may be composed of Cu, Al, Au, Ag, W, and/or another suitable metal.
  • Semiconductor chip 202 is laterally surrounded by encapsulant material 206 , such as a mold compound or another suitable encapsulation material, which provides a fan-out area for electrical connections to semiconductor chip 202 .
  • the top surface of dielectric layer 208 contacts a bottom surface of encapsulant material 206 and the front side of semiconductor chip 202 .
  • the bottom surface of dielectric layer 208 contacts the top surface of dielectric layer 210 .
  • each dielectric layer 208 and 210 may be composed of SiO 2 , Si 3 N 4 , or another suitable dielectric material.
  • Redistribution layer 212 is formed on and/or within dielectric layers 208 and 210 .
  • Redistribution layer 212 may be composed of Cu, Al, Au, Ag, W, and/or other suitable metals. Redistribution layer 212 electrically couples contacts 204 to solder balls 226 and to dipole antennas 218 and 230 .
  • the bottom surface of conductive layer 214 contacts the back side of semiconductor chip 202 .
  • Conductive layer 214 may be low ohmic (e.g., less than 1 Ohm) contacted to the bulk silicon of semiconductor chip 202 and thereby grounded.
  • conductive layer 214 is isolated from semiconductor chip 202 via another material.
  • conductive layer 214 covers semiconductor chip 202 .
  • Conductive layer 214 may be composed of Cu, Al, Au, Ag, W, and/or another suitable metal.
  • redistribution layer 212 includes conductive layer portions (not shown) in the fan-out area of encapsulant material 206 .
  • Encapsulant material 206 contacts the top surface of conductive layer 214 .
  • Dipole antennas 218 and 230 contact the top surface of encapsulant material 206 .
  • Each dipole antenna 230 is electrically coupled to redistribution layer 212 through differential transmission lines including a via connection 216 and conductive pads 232 and conductive traces 233 on the top surface of via connection 216 and the top surface of encapsulant material 206 .
  • Each dipole antenna 218 is electrically coupled to redistribution layer 212 through differential transmission lines including a via connection (not shown) and conductive pads 224 and conductive traces 225 on the top surface of encapsulant material 206 .
  • conductive pads 224 and 232 , conductive traces 225 and 233 , and dipole antennas 218 and 230 may be composed of Cu, Al, Au, Ag, W, and/or other suitable metals.
  • via connection 216 is an embedded Z-line (EZL) via connection.
  • EZL via connection 216 is fabricated using eWLB lateral X-Y structures that serve as vertical Z structures after sawing and flipping the structures 90°.
  • Via connection 216 includes a dielectric material 217 in which vias 220 are formed.
  • via connection 216 is embedded in encapsulant material 206 .
  • Via connection 216 is then exposed by grinding encapsulant material 206 to provide the top surface of encapsulant material 206 as illustrated in FIG. 2A .
  • dipole antennas 218 are outside the footprint of semiconductor chip 202 and dipole antennas 230 are within the footprint of semiconductor chip 202 .
  • Dipole antennas 218 for transmitting RF signals include two dipole antennas on opposing sides of semiconductor chip 202 .
  • Dipole antennas 230 for receiving RF signals include four dipole antennas arranged in a square configuration. In other examples, dipole antennas 218 and 230 may have another suitable arrangement. By arranging dipole antennas 230 above semiconductor chip 202 and dipole antennas 218 above the fan-out area, a compact semiconductor device 200 including integrated RF functionally may be provided. In this way, an application board on which semiconductor device 200 is installed does not require antennas to implement RF functionality.
  • antennas 218 and 230 may include folded dipole antennas ( FIG. 7B ), ring antennas ( FIG. 7C ), rectangular loop antennas ( FIG. 7D ), patch antennas ( FIG. 7E ), coplanar patch antennas ( FIG. 7F ), slot antennas, or monopole antennas.
  • FIG. 3A is a cross-sectional view illustrating another example of a semiconductor device 300 .
  • Semiconductor device 300 is an eWLB semiconductor device.
  • Semiconductor device 300 includes a semiconductor chip 302 , an encapsulant material 306 , a redistribution layer 312 including a conductive layer 314 (e.g., ground plane, reflector, or shielding), dielectric layers 308 , 309 , 310 , and 326 , patch antennas 118 for transmitting RF signals, patch antennas (not shown) for receiving RF signals, a heat sink 327 , and solder balls 328 .
  • semiconductor chip 302 is a RF semiconductor chip for a millimeter wave application, such as gesture sensing at 60 GHz or another suitable application.
  • a front side (i.e., active side) of semiconductor chip 302 includes contacts 304 .
  • Contacts 304 may be composed of Cu, Al, Au, Ag, W, and/or another suitable metal.
  • Semiconductor chip 302 is laterally surrounded by encapsulant material 306 , such as a mold compound or another suitable encapsulation material, which provides a fan-out area for electrical connections to semiconductor chip 302 .
  • the bottom surface of dielectric layer 308 contacts the top surface of encapsulant material 306 and the front side of semiconductor chip 302 .
  • the top surface of dielectric layer 308 contacts the bottom surface of dielectric layer 310 .
  • each dielectric layer 308 and 310 may be composed of SiO 2 , Si 3 N 4 , or another suitable dielectric material.
  • Redistribution layer 312 is formed on and/or within dielectric layers 308 and 310 .
  • Redistribution layer 312 may be composed of Cu, Al, Au, Ag, W, and/or other suitable metals. Redistribution layer 312 electrically couples contacts 304 to solder balls 328 through vias 316 , which extend through encapsulant material 306 , provides RF signal feeds 313 , and provides conductive layer 314 .
  • the top surface of dielectric layer 309 contacts the back side of semiconductor chip 302 and the bottom surface of encapsulant material 306 .
  • Dielectric layer 309 may be composed of the same dielectric material as dielectric layer 308 or 310 .
  • the top surface of heat sink 327 contacts the bottom surface of dielectric layer 309 .
  • Heat sink 327 may be electrically coupled to conductive layer 314 through redistribution layer 312 and vias (not shown), which extend through encapsulant material 306 .
  • Heat sink 327 may be composed of Cu, Al, Au, Ag, W, and/or another suitable metal.
  • conductive layer 314 contacts the top surface of dielectric layer 310 .
  • conductive layer 314 covers semiconductor chip 302 and encapsulant material 306 except where slots 315 are arranged.
  • the top surface of conductive layer 314 contacts the bottom surface of dielectric layer 326 .
  • dielectric layer 326 may be composed of a laminate, an encapsulant material, an imide material, or another suitable dielectric material.
  • Patch antennas 318 contact the top surface of dielectric layer 326 . Patch antennas 318 are aligned with slots 315 of conductive layer 314 to provide aperture coupled patch antennas 318 to RF signal feeds 313 . By using aperture coupled patch antennas, an electrical connection between semiconductor chip 302 and patch antennas 318 is not required. Rather, patch antennas 318 are electromagnetically coupled to semiconductor chip 302 through slots 315 in conductive layer 314 .
  • Patch antennas 118 may be composed of Cu, Al, Au, Ag, W, and/or another suitable metal.
  • FIG. 3B is a cross-sectional view illustrating another example of a semiconductor device 350 .
  • Semiconductor device 350 is similar to semiconductor device 300 previously described and illustrated with reference to FIG. 3A , except that in semiconductor device 350 , conductive layer 314 is removed.
  • patch antennas 318 are proximity coupled to RF signal feeds 313 . By using proximity coupled patch antennas, an electrical connection between semiconductor chip 302 and patch antennas 318 is not required. Rather, patch antennas 318 are electromagnetically coupled to semiconductor chip 302 .
  • FIG. 4 is a cross-sectional view illustrating another example of a semiconductor device 400 .
  • Semiconductor device 400 is an eWLB semiconductor device.
  • Semiconductor device 400 includes a semiconductor chip 402 , an encapsulant material 406 , a redistribution layer 412 , a conductive layer 414 (e.g., ground plane, reflector, or shielding), dielectric layers 408 , 410 , and 426 , patch antennas 418 for transmitting RF signals, patch antennas (not shown) for receiving RF signals, and solder balls 428 .
  • semiconductor chip 402 is a RF semiconductor chip for a millimeter wave application, such as gesture sensing at 60 GHz or another suitable application.
  • a front side (i.e., active side) of semiconductor chip 402 includes contacts 404 .
  • Contacts 404 may be composed of Cu, Al, Au, Ag, W, and/or another suitable metal.
  • Semiconductor chip 402 is laterally surrounded by encapsulant material 406 , such as a mold compound or another suitable encapsulation material, which provides a fan-out area for electrical connections to semiconductor chip 402 .
  • the top surface of dielectric layer 408 contacts the bottom surface of encapsulant material 406 and the front side of semiconductor chip 402 .
  • the bottom surface of dielectric layer 408 contacts the top surface of dielectric layer 410 .
  • each dielectric layer 408 and 410 may be composed SiO 2 , Si 3 N 4 , or another suitable dielectric material.
  • Redistribution layer 412 is formed on and/or within dielectric layers 408 and 410 .
  • Redistribution layer 412 may be composed of Cu, Al, Au, Ag, W, and/or other suitable metals. Redistribution layer 412 electrically couples contacts 404 to conductive layer 414 and solder balls 428 and provides RF signal feeds 413 .
  • conductive layer 414 contacts the back side of semiconductor chip 402 and the top surface of encapsulant material 406 .
  • Conductive layer 414 is electrically coupled to redistribution layer 412 through vias 416 , which extend through encapsulant material 406 .
  • Conductive layer 414 and vias 416 may be composed of Cu, Al, Au, Ag, W, and/or other suitable metals.
  • conductive layer 414 covers semiconductor chip 402 and encapsulant material 406 except where slots 415 are arranged.
  • the top surface of conductive layer 414 contacts the bottom surface of dielectric layer 426 .
  • dielectric layer 426 may be composed of a laminate, an encapsulant material, an imide material, or another suitable dielectric material.
  • Patch antennas 418 contact the top surface of dielectric layer 426 .
  • Patch antennas 418 are aligned with slots 415 of conductive layer 414 to provide aperture coupled patch antennas 418 to RF signal feeds 413 .
  • an electrical connection between semiconductor chip 402 and patch antennas 418 is not required.
  • patch antennas 418 are electromagnetically coupled to semiconductor chip 402 through slots 415 in conductive layer 414 .
  • patch antennas 418 may be proximity coupled antennas (not shown), which are electromagnetically coupled to semiconductor chip 402 .
  • Patch antennas 418 may be composed of Cu, Al, Au, Ag, W, and/or another suitable metal.
  • FIG. 5 is a cross-sectional view illustrating another example of a semiconductor device 500 .
  • Semiconductor device 500 is an eWLB semiconductor device.
  • Semiconductor device 500 includes a semiconductor chip 502 , an encapsulant material 506 , a redistribution layer 512 , a conductive layer 514 (e.g., ground plane, reflector, or shielding), dielectric layers 508 , 510 , and 526 , patch antennas 518 for transmitting RF signals, patch antennas (not shown) for receiving RF signals, a die attach foil 516 , and solder balls 528 and 529 .
  • semiconductor chip 502 is a RF semiconductor chip for a millimeter wave application, such as gesture sensing at 60 GHz or another suitable application.
  • a front side (i.e., active side) of semiconductor chip 502 includes contacts 504 .
  • Contacts 504 may be composed of Cu, Al, Au, Ag, W, and/or another suitable metal.
  • Semiconductor chip 502 is laterally surrounded by encapsulant material 506 , such as a mold compound or another suitable encapsulation material, which provides a fan-out area for electrical connections to semiconductor chip 502 .
  • the top surface of dielectric layer 508 contacts the bottom surface of encapsulant material 506 and the front side of semiconductor chip 502 .
  • the bottom surface of dielectric layer 508 contacts the top surface of dielectric layer 510 .
  • each dielectric layer 508 and 510 may be composed of SiO 2, Si 3 N 4 , or another suitable dielectric material.
  • Redistribution layer 512 is formed on and/or within dielectric layers 508 and 510 .
  • Redistribution layer 512 may be composed of Cu, Al, Au, Ag, W, and/or other suitable metals. Redistribution layer 512 electrically couples contacts 504 to solder balls 528 and provides RF signal feeds 513 .
  • the bottom surface of die attach foil 516 contacts the back side of semiconductor chip 502 and the top surface of encapsulant material 506 .
  • the top surface of die attach foil 516 contacts the bottom surface of conductive layer 514 .
  • Conductive layer 514 is electrically coupled to solder balls 529 , which are laterally adjacent to semiconductor chip 502 and encapsulant material 506 and which are larger than solder balls 528 .
  • Solder balls 529 have a diameter greater than a sum of the thicknesses of semiconductor chip 502 and redistribution layer 512 . By using solder balls 529 , vias to electrically couple conductive layer 514 to redistribution layer 512 are not needed.
  • Conductive layer 514 may be composed of Cu, Al, Au, Ag, W, and/or another suitable metal. In one example, conductive layer 514 covers semiconductor chip 502 and encapsulant material 506 except where slots 515 are arranged. The top surface of conductive layer 514 contacts the bottom surface of dielectric layer 526 .
  • dielectric layer 526 may be composed of a laminate, an encapsulant material, an imide material, or another suitable dielectric material.
  • Patch antennas 518 contact the top surface of dielectric layer 526 .
  • Patch antennas 518 are aligned with slots 515 of conductive layer 514 to provide aperture coupled patch antennas 518 to RF signal feeds 513 .
  • aperture coupled patch antennas an electrical connection between semiconductor chip 502 and patch antennas 518 is not required. Rather, patch antennas 518 are electromagnetically coupled to semiconductor chip 502 through slots 515 in conductive layer 514 .
  • patch antennas 518 may be proximity coupled antennas (not shown), which are electromagnetically coupled to semiconductor chip 502 .
  • Patch antennas 518 may be composed of Cu, Al, Au, Ag, W, and/or another suitable metal.
  • FIGS. 6A-6D are cross-sectional views illustrating one example of a method for fabricating semiconductor device 500 illustrated in FIG. 5 .
  • FIG. 6A is a cross-sectional view illustrating one example of a semiconductor device 550 after a first stage of the fabrication process.
  • Semiconductor device 550 is one semiconductor device in an eWLB wafer.
  • Semiconductor device 550 includes a semiconductor chip 502 , a redistribution layer 512 , dielectric layers 508 and 510 , and an encapsulant material 506 .
  • Encapsulant material 506 covers the back side of semiconductor chip 502 and laterally surrounds semiconductor chip 502 to provide a fan-out area for electrical connections.
  • Kerfs 552 are cut through dielectric layers 510 and 508 and into encapsulant material 506 prior to dicing and grinding the eWLB wafer to provide a plurality of separated semiconductor devices.
  • FIG. 6B is a cross-sectional view illustrating one example of a semiconductor device 560 after a second stage of the fabrication process.
  • the back side of semiconductor device 550 illustrated in FIG. 6A is subjected to grinding to remove encapsulant material 506 to expose the back side of semiconductor chip 502 and to singulate the eWLB wafer to provide semiconductor device 560 having an eWLB package.
  • FIG. 6C is a cross-sectional view illustrating one example of a carrier 570 .
  • Carrier 570 includes a dielectric layer 526 , a conductive layer 514 , patch antennas 518 for transmitting RF signals, and patch antennas (not shown) for receiving RF signals.
  • Conductive layer 514 is formed on a first side of dielectric layer 526 via a plating process, a deposition process, or anther suitable process.
  • Conductive layer 514 includes slots 515 .
  • Patch antennas 518 are formed on a second side of dielectric layer 526 opposite to the first side via a plating process, a deposition process, or another suitable process. Each patch antenna 518 is aligned with a slot 515 of conductive layer 514 .
  • FIG. 6D is a cross-sectional view illustrating one example of a semiconductor device 580 after attaching carrier 570 previously described and illustrated with reference to FIG. 6C to semiconductor device 560 previously described and illustrated with reference to FIG. 6B .
  • Carrier 570 is attached to the back side of semiconductor chip 502 and to encapsulant material 506 via a die attach foil 516 .
  • carrier 570 is attached to the back side of semiconductor chip 502 and to encapsulant material 506 using an adhesive material or another suitable die attach material.
  • Solder balls 528 are then electrically coupled to redistribution layer 512 and solder balls 529 are electrically coupled to conductive layer 514 to provide semiconductor device 500 previously described and illustrated with reference to FIG. 5 .
  • the semiconductor devices described herein including antennas in an eWLB package enable the use of less expensive application boards rather than more expensive RF application boards.
  • the package size and thus the cost of the semiconductor devices is reduced.
  • the eWLB package provides excellent RF performance due to low parasitic inductance and ohmic losses.

Abstract

A semiconductor device includes a semiconductor chip and a redistribution layer on a first side of the semiconductor chip. The redistribution layer is electrically coupled to the semiconductor chip. The semiconductor device includes a dielectric layer and an antenna on the dielectric layer. The dielectric layer is between the antenna and the semiconductor chip.

Description

    CROSS REFERENCE TO RELATED APPLICATION
  • This Utility Patent Application is a continuation application of U.S. patent application Ser. No. 15/045,687 filed Feb. 17, 2016, which is incorporated herein by reference.
    • BACKGROUND
  • One type of semiconductor device package is an embedded wafer level ball grid array (eWLB) package. An eWLB package provides a fan-out area to provide more space for interconnect routing compared to semiconductor device packages without a fan-out area. For millimeter wave applications, antennas are used to transmit and receive radio frequency (RF) signals. The antennas may be integrated on a printed circuit board on which an RF semiconductor chip is attached. Integrating antennas on a printed circuit board may be expensive.
  • For these and other reasons, there is a need for the present invention.
    • SUMMARY
  • One example of a semiconductor device includes a semiconductor chip and a redistribution layer on a first side of the semiconductor chip. The redistribution layer is electrically coupled to the semiconductor chip. The semiconductor device includes a dielectric layer and an antenna on the dielectric layer. The dielectric layer is between the antenna and the semiconductor chip.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1A is a cross-sectional view and FIG. 1B is a top view illustrating of one example of a semiconductor device.
  • FIG. 2A is a cross-sectional view and FIG. 2B is a top view illustrating another example of a semiconductor device.
  • FIG. 3A is a cross-sectional view illustrating another example of a semiconductor device.
  • FIG. 3B is a cross-sectional view illustrating another example of a semiconductor device.
  • FIG. 4 is a cross-sectional view illustrating another example of a semiconductor device.
  • FIG. 5 is a cross-sectional view illustrating another example of a semiconductor device.
  • FIGS. 6A-6D are cross-sectional views illustrating one example of a method for fabricating the semiconductor device illustrated in FIG. 5.
  • FIGS. 7A-7F illustrate example antenna structures.
    •  DETAILED DESCRIPTION
  • In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the disclosure may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims.
  • It is to be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically noted otherwise.
  • As used herein, the term “electrically coupled” is not meant to mean that the elements must be directly coupled together and intervening elements may be provided between the “electrically coupled” elements. “Electrically coupled” elements have a metallic or other electrically conductive material path between the “electrically coupled” elements such that a current may flow from one element to the other element.
  • As used herein, “electromagnetically coupled” elements are coupled through an electromagnetic field without a metallic or other electrically conductive material path between the “electromagnetically coupled” elements such that a current cannot flow from one element to the other element.
  • FIG. 1A is a cross-sectional view and FIG. 1B is a top view illustrating one example of a semiconductor device 100. Semiconductor device 100 is an embedded wafer level ball grid array (eWLB) semiconductor device. Semiconductor device 100 includes a semiconductor chip 102, an encapsulant material 106 (e.g., a mold compound, a polymer, an epoxy, BT, or a hydrocarbon/ceramic laminate), a redistribution layer 112, a conductive layer 114 (e.g., ground plane, reflector, or shielding), dielectric layers 108, 110, and 126, patch antennas 118 for transmitting RF signals, patch antennas 130 for receiving RF signals, and solder balls 128. In one example, semiconductor chip 102 is a radio frequency (RF) semiconductor chip for a millimeter wave application, such as gesture sensing at 60 GHz or another suitable application.
  • A front side (i.e., active side) of semiconductor chip 102 includes contacts 104. Contacts 104 may be composed of Cu, Al, Au, Ag, W, and/or another suitable metal. Semiconductor chip 102 is laterally surrounded by encapsulant material 106, such as a mold compound or another suitable encapsulation material, which provides a fan-out area for electrical connections to semiconductor chip 102. The top surface of dielectric layer 108 contacts the bottom surface of encapsulant material 106 and the front side of semiconductor chip 102. The bottom surface of dielectric layer 108 contacts the top surface of dielectric layer 110. In one example, each dielectric layer 108 and 110 may be composed of SiO2, Si3N4, or another suitable dielectric material. Redistribution layer 112 is formed on and/or within dielectric layers 108 and 110. Redistribution layer 112 may be composed of Cu, Al, Au, Ag, W, and/or other suitable metals. Redistribution layer 112 electrically couples contacts 104 to conductive layer 114, solder balls 128, and patch antennas 118 and 130.
  • The bottom surface of conductive layer 114 contacts the back side of semiconductor chip 102 and the top surface of encapsulant material 106. In one example, conductive layer 114 covers semiconductor chip 102 and encapsulant material 106 except where electrical connections to patch antennas 118 and 130 extend through conductive layer 114. Conductive layer 114 is electrically coupled to redistribution layer 112 through vias 116, which extend through encapsulant material 106. Conductive layer 114 and vias 116 may be composed of Cu, Al, Au, Ag, W, and/or other suitable metals.
  • The bottom surface of dielectric layer 126 contacts the top surface of conductive layer 114. In one example, dielectric layer 126 may be composed of a laminate, an encapsulant material, an imide material, or another suitable dielectric material. A ground line 115 and patch antennas 118 and 130 contact the top surface of dielectric layer 126. Ground line 115 is electrically coupled to conductive layer 114 through vias 117 (one via 117 is visible in FIG. 1A), which extend through dielectric layer 126. Each patch antenna 118 is electrically coupled to redistribution layer 112 through a via 120, which extends through encapsulant material 106, a conductive pad 121 on the top surface of encapsulant material 106, a via 122, which extends through dielectric layer 126, and a conductive pad 124 and conductive trace 125 on the top surface of dielectric layer 126. Each patch antenna 130 is electrically coupled to redistribution layer 112 through a via through encapsulant material 106 (not shown), a conductive pad on the top surface of encapsulant material 106 (not shown), a via through dielectric layer 126 (not shown), and a conductive pad 132 and a conductive trace 133 on the top surface of dielectric layer 126. In one example, vias 120 and 122, conductive pads 121, 124, and 132, conductive traces 125 and 133, and patch antennas 118 and 130 may be composed of Cu, Al, Au, Ag, W, and/or other suitable metals. Each via 116, 120, and 122 may be rectangular in shape with dimensions (length by width by height) between 50 μm by 10 μm by 50 μm and 150 μm by 10 μm by 450 μm. Each via 116, 120, and 122 may be formed using a photolithography, etching, and deposition process; a laser drilling and deposition process; or another suitable process.
  • As shown in FIG. 1B, patch antennas 118 and 130 are within the footprint of semiconductor chip 102. Patch antennas 118 for transmitting RF signals include two patch antennas separated by ground line 115. Each patch antenna 118 is arranged at a corner of semiconductor chip 102. Patch antennas 130 for receiving RF signals include four patch antennas arranged in a square configuration. Patch antennas 130 are separated from patch antennas 118 by ground line 115. In other examples, patch antennas 118 and 130 may have another suitable arrangement. By arranging patch antennas 118 and 130 above semiconductor chip 102, a compact semiconductor device 100 including integrated RF functionally may be provided. In this way, an application board on which semiconductor device 100 is installed does not require antennas to implement RF functionality.
  • In other examples, any one of various types of planar antennas may be used in place of patch antennas 118 and 130. For example, antennas 118 and 130 may include dipole antennas (FIG. 7A), folded dipole antennas (FIG. 7B), ring antennas (FIG. 7C), rectangular loop antennas (FIG. 7D), coplanar patch antennas (FIG. 7F), slot antennas, or monopole antennas.
  • FIG. 2A is a cross-sectional view and FIG. 2B is a top view illustrating another example of a semiconductor device 200. Semiconductor device 200 is an eWLB semiconductor device. Semiconductor device 200 includes a semiconductor chip 202, an encapsulant material 206, a redistribution layer 212, a conductive layer 214 (e.g., reflector, ground plane, or shielding), dielectric layers 108 and 110, dipole antennas 218 for transmitting RF signals, dipole antennas 230 for receiving RF signals, and solder balls 228. In one example, semiconductor chip 202 is a RF semiconductor chip for a millimeter wave application, such as gesture sensing at 60 GHz or another suitable application.
  • A front side (i.e., active side) of semiconductor chip 202 includes contacts 204. Contacts 204 may be composed of Cu, Al, Au, Ag, W, and/or another suitable metal. Semiconductor chip 202 is laterally surrounded by encapsulant material 206, such as a mold compound or another suitable encapsulation material, which provides a fan-out area for electrical connections to semiconductor chip 202. The top surface of dielectric layer 208 contacts a bottom surface of encapsulant material 206 and the front side of semiconductor chip 202. The bottom surface of dielectric layer 208 contacts the top surface of dielectric layer 210. In one example, each dielectric layer 208 and 210 may be composed of SiO2, Si3N4, or another suitable dielectric material. Redistribution layer 212 is formed on and/or within dielectric layers 208 and 210. Redistribution layer 212 may be composed of Cu, Al, Au, Ag, W, and/or other suitable metals. Redistribution layer 212 electrically couples contacts 204 to solder balls 226 and to dipole antennas 218 and 230.
  • In one example, the bottom surface of conductive layer 214 contacts the back side of semiconductor chip 202. Conductive layer 214 may be low ohmic (e.g., less than 1 Ohm) contacted to the bulk silicon of semiconductor chip 202 and thereby grounded. In another example, conductive layer 214 is isolated from semiconductor chip 202 via another material. In one example, conductive layer 214 covers semiconductor chip 202. Conductive layer 214 may be composed of Cu, Al, Au, Ag, W, and/or another suitable metal. In one example, redistribution layer 212 includes conductive layer portions (not shown) in the fan-out area of encapsulant material 206. Encapsulant material 206 contacts the top surface of conductive layer 214. Dipole antennas 218 and 230 contact the top surface of encapsulant material 206.
  • Each dipole antenna 230 is electrically coupled to redistribution layer 212 through differential transmission lines including a via connection 216 and conductive pads 232 and conductive traces 233 on the top surface of via connection 216 and the top surface of encapsulant material 206. Each dipole antenna 218 is electrically coupled to redistribution layer 212 through differential transmission lines including a via connection (not shown) and conductive pads 224 and conductive traces 225 on the top surface of encapsulant material 206. In one example, conductive pads 224 and 232, conductive traces 225 and 233, and dipole antennas 218 and 230 may be composed of Cu, Al, Au, Ag, W, and/or other suitable metals.
  • In one example, via connection 216 is an embedded Z-line (EZL) via connection. EZL via connection 216 is fabricated using eWLB lateral X-Y structures that serve as vertical Z structures after sawing and flipping the structures 90°. Via connection 216 includes a dielectric material 217 in which vias 220 are formed. When fabricating semiconductor device 200, via connection 216 is embedded in encapsulant material 206. Via connection 216 is then exposed by grinding encapsulant material 206 to provide the top surface of encapsulant material 206 as illustrated in FIG. 2A.
  • As shown in FIG. 2B, dipole antennas 218 are outside the footprint of semiconductor chip 202 and dipole antennas 230 are within the footprint of semiconductor chip 202. Dipole antennas 218 for transmitting RF signals include two dipole antennas on opposing sides of semiconductor chip 202. Dipole antennas 230 for receiving RF signals include four dipole antennas arranged in a square configuration. In other examples, dipole antennas 218 and 230 may have another suitable arrangement. By arranging dipole antennas 230 above semiconductor chip 202 and dipole antennas 218 above the fan-out area, a compact semiconductor device 200 including integrated RF functionally may be provided. In this way, an application board on which semiconductor device 200 is installed does not require antennas to implement RF functionality.
  • In other examples, any one of various types of planar antennas may be used in place of dipole antennas 218 and 230. For example, antennas 218 and 230 may include folded dipole antennas (FIG. 7B), ring antennas (FIG. 7C), rectangular loop antennas (FIG. 7D), patch antennas (FIG. 7E), coplanar patch antennas (FIG. 7F), slot antennas, or monopole antennas.
  • FIG. 3A is a cross-sectional view illustrating another example of a semiconductor device 300. Semiconductor device 300 is an eWLB semiconductor device. Semiconductor device 300 includes a semiconductor chip 302, an encapsulant material 306, a redistribution layer 312 including a conductive layer 314 (e.g., ground plane, reflector, or shielding), dielectric layers 308, 309, 310, and 326, patch antennas 118 for transmitting RF signals, patch antennas (not shown) for receiving RF signals, a heat sink 327, and solder balls 328. In one example, semiconductor chip 302 is a RF semiconductor chip for a millimeter wave application, such as gesture sensing at 60 GHz or another suitable application.
  • A front side (i.e., active side) of semiconductor chip 302 includes contacts 304. Contacts 304 may be composed of Cu, Al, Au, Ag, W, and/or another suitable metal. Semiconductor chip 302 is laterally surrounded by encapsulant material 306, such as a mold compound or another suitable encapsulation material, which provides a fan-out area for electrical connections to semiconductor chip 302. The bottom surface of dielectric layer 308 contacts the top surface of encapsulant material 306 and the front side of semiconductor chip 302. The top surface of dielectric layer 308 contacts the bottom surface of dielectric layer 310. In one example, each dielectric layer 308 and 310 may be composed of SiO2, Si3N4, or another suitable dielectric material. Redistribution layer 312 is formed on and/or within dielectric layers 308 and 310. Redistribution layer 312 may be composed of Cu, Al, Au, Ag, W, and/or other suitable metals. Redistribution layer 312 electrically couples contacts 304 to solder balls 328 through vias 316, which extend through encapsulant material 306, provides RF signal feeds 313, and provides conductive layer 314.
  • The top surface of dielectric layer 309 contacts the back side of semiconductor chip 302 and the bottom surface of encapsulant material 306. Dielectric layer 309 may be composed of the same dielectric material as dielectric layer 308 or 310. The top surface of heat sink 327 contacts the bottom surface of dielectric layer 309. Heat sink 327 may be electrically coupled to conductive layer 314 through redistribution layer 312 and vias (not shown), which extend through encapsulant material 306. Heat sink 327 may be composed of Cu, Al, Au, Ag, W, and/or another suitable metal.
  • The bottom surface of conductive layer 314 contacts the top surface of dielectric layer 310. In one example, conductive layer 314 covers semiconductor chip 302 and encapsulant material 306 except where slots 315 are arranged. The top surface of conductive layer 314 contacts the bottom surface of dielectric layer 326. In one example, dielectric layer 326 may be composed of a laminate, an encapsulant material, an imide material, or another suitable dielectric material. Patch antennas 318 contact the top surface of dielectric layer 326. Patch antennas 318 are aligned with slots 315 of conductive layer 314 to provide aperture coupled patch antennas 318 to RF signal feeds 313. By using aperture coupled patch antennas, an electrical connection between semiconductor chip 302 and patch antennas 318 is not required. Rather, patch antennas 318 are electromagnetically coupled to semiconductor chip 302 through slots 315 in conductive layer 314. Patch antennas 118 may be composed of Cu, Al, Au, Ag, W, and/or another suitable metal.
  • FIG. 3B is a cross-sectional view illustrating another example of a semiconductor device 350. Semiconductor device 350 is similar to semiconductor device 300 previously described and illustrated with reference to FIG. 3A, except that in semiconductor device 350, conductive layer 314 is removed. In this example, patch antennas 318 are proximity coupled to RF signal feeds 313. By using proximity coupled patch antennas, an electrical connection between semiconductor chip 302 and patch antennas 318 is not required. Rather, patch antennas 318 are electromagnetically coupled to semiconductor chip 302.
  • FIG. 4 is a cross-sectional view illustrating another example of a semiconductor device 400. Semiconductor device 400 is an eWLB semiconductor device. Semiconductor device 400 includes a semiconductor chip 402, an encapsulant material 406, a redistribution layer 412, a conductive layer 414 (e.g., ground plane, reflector, or shielding), dielectric layers 408, 410, and 426, patch antennas 418 for transmitting RF signals, patch antennas (not shown) for receiving RF signals, and solder balls 428. In one example, semiconductor chip 402 is a RF semiconductor chip for a millimeter wave application, such as gesture sensing at 60 GHz or another suitable application.
  • A front side (i.e., active side) of semiconductor chip 402 includes contacts 404. Contacts 404 may be composed of Cu, Al, Au, Ag, W, and/or another suitable metal. Semiconductor chip 402 is laterally surrounded by encapsulant material 406, such as a mold compound or another suitable encapsulation material, which provides a fan-out area for electrical connections to semiconductor chip 402. The top surface of dielectric layer 408 contacts the bottom surface of encapsulant material 406 and the front side of semiconductor chip 402. The bottom surface of dielectric layer 408 contacts the top surface of dielectric layer 410. In one example, each dielectric layer 408 and 410 may be composed SiO2, Si3N4, or another suitable dielectric material. Redistribution layer 412 is formed on and/or within dielectric layers 408 and 410. Redistribution layer 412 may be composed of Cu, Al, Au, Ag, W, and/or other suitable metals. Redistribution layer 412 electrically couples contacts 404 to conductive layer 414 and solder balls 428 and provides RF signal feeds 413.
  • The bottom surface of conductive layer 414 contacts the back side of semiconductor chip 402 and the top surface of encapsulant material 406. Conductive layer 414 is electrically coupled to redistribution layer 412 through vias 416, which extend through encapsulant material 406. Conductive layer 414 and vias 416 may be composed of Cu, Al, Au, Ag, W, and/or other suitable metals. In one example, conductive layer 414 covers semiconductor chip 402 and encapsulant material 406 except where slots 415 are arranged. The top surface of conductive layer 414 contacts the bottom surface of dielectric layer 426. In one example, dielectric layer 426 may be composed of a laminate, an encapsulant material, an imide material, or another suitable dielectric material. Patch antennas 418 contact the top surface of dielectric layer 426. Patch antennas 418 are aligned with slots 415 of conductive layer 414 to provide aperture coupled patch antennas 418 to RF signal feeds 413. By using aperture coupled patch antennas, an electrical connection between semiconductor chip 402 and patch antennas 418 is not required. Rather, patch antennas 418 are electromagnetically coupled to semiconductor chip 402 through slots 415 in conductive layer 414. In other examples, patch antennas 418 may be proximity coupled antennas (not shown), which are electromagnetically coupled to semiconductor chip 402. Patch antennas 418 may be composed of Cu, Al, Au, Ag, W, and/or another suitable metal.
  • FIG. 5 is a cross-sectional view illustrating another example of a semiconductor device 500. Semiconductor device 500 is an eWLB semiconductor device. Semiconductor device 500 includes a semiconductor chip 502, an encapsulant material 506, a redistribution layer 512, a conductive layer 514 (e.g., ground plane, reflector, or shielding), dielectric layers 508, 510, and 526, patch antennas 518 for transmitting RF signals, patch antennas (not shown) for receiving RF signals, a die attach foil 516, and solder balls 528 and 529. In one example, semiconductor chip 502 is a RF semiconductor chip for a millimeter wave application, such as gesture sensing at 60 GHz or another suitable application.
  • A front side (i.e., active side) of semiconductor chip 502 includes contacts 504. Contacts 504 may be composed of Cu, Al, Au, Ag, W, and/or another suitable metal. Semiconductor chip 502 is laterally surrounded by encapsulant material 506, such as a mold compound or another suitable encapsulation material, which provides a fan-out area for electrical connections to semiconductor chip 502. The top surface of dielectric layer 508 contacts the bottom surface of encapsulant material 506 and the front side of semiconductor chip 502. The bottom surface of dielectric layer 508 contacts the top surface of dielectric layer 510. In one example, each dielectric layer 508 and 510 may be composed of SiO2, Si3N4, or another suitable dielectric material. Redistribution layer 512 is formed on and/or within dielectric layers 508 and 510. Redistribution layer 512 may be composed of Cu, Al, Au, Ag, W, and/or other suitable metals. Redistribution layer 512 electrically couples contacts 504 to solder balls 528 and provides RF signal feeds 513.
  • The bottom surface of die attach foil 516 contacts the back side of semiconductor chip 502 and the top surface of encapsulant material 506. The top surface of die attach foil 516 contacts the bottom surface of conductive layer 514. Conductive layer 514 is electrically coupled to solder balls 529, which are laterally adjacent to semiconductor chip 502 and encapsulant material 506 and which are larger than solder balls 528. Solder balls 529 have a diameter greater than a sum of the thicknesses of semiconductor chip 502 and redistribution layer 512. By using solder balls 529, vias to electrically couple conductive layer 514 to redistribution layer 512 are not needed. Conductive layer 514 may be composed of Cu, Al, Au, Ag, W, and/or another suitable metal. In one example, conductive layer 514 covers semiconductor chip 502 and encapsulant material 506 except where slots 515 are arranged. The top surface of conductive layer 514 contacts the bottom surface of dielectric layer 526.
  • In one example, dielectric layer 526 may be composed of a laminate, an encapsulant material, an imide material, or another suitable dielectric material. Patch antennas 518 contact the top surface of dielectric layer 526. Patch antennas 518 are aligned with slots 515 of conductive layer 514 to provide aperture coupled patch antennas 518 to RF signal feeds 513. By using aperture coupled patch antennas, an electrical connection between semiconductor chip 502 and patch antennas 518 is not required. Rather, patch antennas 518 are electromagnetically coupled to semiconductor chip 502 through slots 515 in conductive layer 514. In other examples, patch antennas 518 may be proximity coupled antennas (not shown), which are electromagnetically coupled to semiconductor chip 502. Patch antennas 518 may be composed of Cu, Al, Au, Ag, W, and/or another suitable metal.
  • FIGS. 6A-6D are cross-sectional views illustrating one example of a method for fabricating semiconductor device 500 illustrated in FIG. 5. FIG. 6A is a cross-sectional view illustrating one example of a semiconductor device 550 after a first stage of the fabrication process. Semiconductor device 550 is one semiconductor device in an eWLB wafer. Semiconductor device 550 includes a semiconductor chip 502, a redistribution layer 512, dielectric layers 508 and 510, and an encapsulant material 506. Encapsulant material 506 covers the back side of semiconductor chip 502 and laterally surrounds semiconductor chip 502 to provide a fan-out area for electrical connections. Kerfs 552 are cut through dielectric layers 510 and 508 and into encapsulant material 506 prior to dicing and grinding the eWLB wafer to provide a plurality of separated semiconductor devices.
  • FIG. 6B is a cross-sectional view illustrating one example of a semiconductor device 560 after a second stage of the fabrication process. The back side of semiconductor device 550 illustrated in FIG. 6A is subjected to grinding to remove encapsulant material 506 to expose the back side of semiconductor chip 502 and to singulate the eWLB wafer to provide semiconductor device 560 having an eWLB package.
  • FIG. 6C is a cross-sectional view illustrating one example of a carrier 570. Carrier 570 includes a dielectric layer 526, a conductive layer 514, patch antennas 518 for transmitting RF signals, and patch antennas (not shown) for receiving RF signals. Conductive layer 514 is formed on a first side of dielectric layer 526 via a plating process, a deposition process, or anther suitable process. Conductive layer 514 includes slots 515. Patch antennas 518 are formed on a second side of dielectric layer 526 opposite to the first side via a plating process, a deposition process, or another suitable process. Each patch antenna 518 is aligned with a slot 515 of conductive layer 514.
  • FIG. 6D is a cross-sectional view illustrating one example of a semiconductor device 580 after attaching carrier 570 previously described and illustrated with reference to FIG. 6C to semiconductor device 560 previously described and illustrated with reference to FIG. 6B. Carrier 570 is attached to the back side of semiconductor chip 502 and to encapsulant material 506 via a die attach foil 516. In other examples, carrier 570 is attached to the back side of semiconductor chip 502 and to encapsulant material 506 using an adhesive material or another suitable die attach material. Solder balls 528 are then electrically coupled to redistribution layer 512 and solder balls 529 are electrically coupled to conductive layer 514 to provide semiconductor device 500 previously described and illustrated with reference to FIG. 5.
  • The semiconductor devices described herein including antennas in an eWLB package enable the use of less expensive application boards rather than more expensive RF application boards. In addition, by arranging at least a portion of the antennas above the RF semiconductor chip, the package size and thus the cost of the semiconductor devices is reduced. Further, the eWLB package provides excellent RF performance due to low parasitic inductance and ohmic losses.
  • Although specific examples have been illustrated and described herein, a variety of alternate and/or equivalent implementations may be substituted for the specific examples shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the specific examples discussed herein. Therefore, it is intended that this disclosure be limited only by the claims and the equivalents thereof.

Claims (26)

1. A semiconductor device comprising:
a semiconductor chip having a first side and a second side;
a redistribution layer on the first side of the semiconductor chip, the redistribution layer electrically coupled to the semiconductor chip;
a first dielectric layer;
a conductive layer between the semiconductor chip and the first dielectric layer; and
an antenna on the first dielectric layer, where the antenna is electromagnetically coupled to the semiconductor chip via the conductive layer.
2. The semiconductor device of claim 1, where the antenna is electromagnetically coupled to the semiconductor chip through slots in the conductive layer.
3. The semiconductor device of claim 2, further comprising:
an encapsulant material laterally surrounding the semiconductor chip.
4. The semiconductor device of claim 3, further comprising:
where the conductive layer covers the semiconductor chip and the encapsulant material except where the slots are arranged.
5. The semiconductor device of claim 1, further comprising:
where the antenna includes one or more patch antennas.
6. The semiconductor device of claim 1, the redistribution layer including an RF signal feed, the conductive layer including a slot, where the RF signal feed and the slot are aligned between the antenna and the semiconductor chip to electromagnetically couple the antenna to the semiconductor chip.
7. The semiconductor device of claim 1, comprising:
a heat sink on a second side of the semiconductor chip opposite to the first side; and
a solder ball coupled to the heat sink.
8. The semiconductor device of claim 67, comprising:
an encapsulation layer surrounding the semiconductor chip, wherein the redistribution layer is coupled to the solder ball through a via in the encapsulation layer.
9. The semiconductor device of claim 1, wherein the antenna comprises a dipole antenna, a folded dipole antenna, a ring antenna, a rectangular loop antenna, a patch antenna, or a coplanar patch antenna.
10. The semiconductor device of claim 1, further comprising:
an encapsulant material laterally surrounding the semiconductor chip;
wherein the redistribution layer, the conductive layer, and the antenna are on the first side of the semiconductor chip and the encapsulant material.
11. A semiconductor device comprising:
a semiconductor chip having a first side and a second side;
a redistribution layer on the first side of the semiconductor chip, the redistribution layer electrically coupled to the semiconductor chip;
a first dielectric layer;
a conductive layer between the semiconductor chip and the first dielectric layer, the conductive layer including a slot; and
an antenna on the first dielectric layer, where the antenna is electromagnetically coupled to the semiconductor chip through the first slot in the conductive layer.
12. The semiconductor device of claim 11, where the redistribution layer including an RF signal feed.
13. The semiconductor device of claim 12, wherein the first slot and the RF signal feed are aligned between the antenna and the semiconductor chip.
14. The semiconductor device of claim 11, wherein the antenna comprises one or more patch antennas.
15. The semiconductor device of claim 11, comprising:
a heat sink on the second side of the semiconductor chip opposite to the first side; and
a solder ball coupled to the heat sink.
16. The semiconductor device of claim 1, the heat sink comprising a first heat sink and a second heat sink, where the first heat sink is located directly below the semiconductor chip, and the second heat sink is spaced from the first heat sink.
17. The semiconductor device of claim 16, further comprising:
an encapsulant material laterally surrounding the semiconductor chip; and
where the redistribution layer is coupled to the second heat sink through a via in the encapsulation material.
18. The semiconductor device of claim 11, wherein the redistribution layer comprises the conductive layer.
19. The semiconductor device of claim 11, comprising a second dielectric layer between the conductive layer and the redistribution layer.
20. The semiconductor device of claim 19, further comprising:
an encapsulant material laterally surrounding the semiconductor chip; and
a third dielectric layer between the redistribution layer and the encapsulant material and the semiconductor chip.
21. The semiconductor device of claim 20, comprising:
a fourth dielectric layer on the encapsulant material and semiconductor chip, on the second side of the semiconductor chip opposite the third dielectric material.
22. The semiconductor device of claim 11, comprising one or more contacts located on the semiconductor chip, where the redistributrion layer electrically couples contacts to solder balls through one or more vias located in the encapsulation layer.
23. The semiconductor device of claim 11, where the semiconductor chip is a radio frequency semiconductor chip.
24. A method for fabricating a semiconductor device package, the method comprising:
fabricating an embedded wafer level ball grid array package comprising a radio frequency semiconductor chip laterally surrounded by an encapsulant material;
fabricating a redistribution layer on the semiconductor chip and the encapsulant material, the semiconductor chip having a first side and a second side;
fabricating a first dielectric layer;
fabricating a conductive layer between the semiconductor chip and the first dielectric layer, the conductive layer including a slot; and
locating an antenna on the first dielectric layer, where the antenna is electromagnetically coupled to the semiconductor chip through the first slot in the conductive layer.
25. The method of claim 24, comprising fabricating the redistribution layer to include an RF signal feed, and aligning the first slot and the RF signal feed between the antenna and the semiconductor chip.
26. The method of claim 25, comprising:
providing a carrier; and
attaching the embedded wafer level ball grid array package to the carrier.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200212536A1 (en) * 2018-12-31 2020-07-02 Texas Instruments Incorporated Wireless communication device with antenna on package

Families Citing this family (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10770795B2 (en) * 2016-05-27 2020-09-08 Taiwan Semiconductor Manufacturing Co., Ltd. Antenna device and method for manufacturing antenna device
US10181653B2 (en) * 2016-07-21 2019-01-15 Infineon Technologies Ag Radio frequency system for wearable device
DE102016014649A1 (en) * 2016-12-08 2018-06-14 Inova Semiconductors Gmbh Compact light-emitting diode arrangement
DE102017200121A1 (en) * 2017-01-05 2018-07-05 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Wafer Level Package with at least one integrated antenna element
DE102017200127A1 (en) * 2017-01-05 2018-07-05 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Module assembly with embedded components and an integrated antenna, device with modular arrangements and method of manufacture
DE102017200124A1 (en) 2017-01-05 2018-07-05 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Wafer Level Packages with integrated or embedded antenna
DE102017200122B4 (en) 2017-01-05 2020-07-23 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Wafer level package with integrated antennas and means for shielding, system for this and method for its production
DE102017200126A1 (en) 2017-01-05 2018-07-05 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Module assembly with integrated antenna and embedded components, and method for making a module assembly
US10541464B2 (en) * 2017-01-17 2020-01-21 Sony Corporation Microwave antenna coupling apparatus, microwave antenna apparatus and microwave antenna package
WO2018173750A1 (en) * 2017-03-21 2018-09-27 株式会社村田製作所 Antenna module and communication device
US20180294569A1 (en) * 2017-04-07 2018-10-11 Skyworks Solutions, Inc. Radio-frequency module with integrated shield layer antenna and integrated cavity-based antenna
US11069978B2 (en) 2017-04-07 2021-07-20 Skyworks Solutions, Inc. Method of manufacturing a radio-frequency module with a conformal shield antenna
US10460987B2 (en) * 2017-05-09 2019-10-29 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package device with integrated antenna and manufacturing method thereof
US10186492B1 (en) * 2017-07-18 2019-01-22 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and manufacturing method thereof
KR102117463B1 (en) * 2017-08-18 2020-06-02 삼성전기주식회사 Antenna embedded semiconductor package
US10511080B2 (en) 2017-08-18 2019-12-17 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
US10510693B2 (en) * 2017-09-28 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package structure
US11024979B2 (en) * 2017-09-29 2021-06-01 Taiwan Semiconductor Manufacturing Co., Ltd. 3D IC antenna array with laminated high-k dielectric
DE112017007887T5 (en) * 2017-09-29 2020-05-07 Intel Corporation ANTENNA PACKAGE WITH BALL MOUNT ARRAY TO CONNECT ANTENNA AND BASE SUBSTRATES
CN111149255B (en) * 2017-10-04 2021-06-29 华为技术有限公司 Multi-band antenna system
CN107910320A (en) * 2017-12-07 2018-04-13 中芯长电半导体（江阴）有限公司 Semiconductor structure with antenna module and preparation method thereof
US10784563B2 (en) * 2018-02-21 2020-09-22 International Business Machines Corporation Scalable phased array package
CN110401008B (en) * 2018-04-25 2022-02-25 华为技术有限公司 Packaging structure with packaged antenna and communication equipment
US11201119B2 (en) * 2018-06-06 2021-12-14 At&S Austria Technologie & Systemtechnik Aktiengesellschaft RF functionality and electromagnetic radiation shielding in a component carrier
US11081453B2 (en) * 2018-07-03 2021-08-03 Mediatek Inc. Semiconductor package structure with antenna
CN110828962B (en) 2018-08-09 2021-08-03 财团法人工业技术研究院 Antenna array module and manufacturing method thereof
US10971461B2 (en) 2018-08-16 2021-04-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US10804229B2 (en) * 2018-08-20 2020-10-13 Sj Semiconductor (Jiangyin) Corporation Fan-out antenna package structure and packaging method
US10580745B1 (en) * 2018-08-31 2020-03-03 Globalfoundries Inc. Wafer level packaging with integrated antenna structures
JP7091961B2 (en) * 2018-09-13 2022-06-28 Tdk株式会社 On-chip antenna
US10840197B2 (en) * 2018-10-30 2020-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and manufacturing method thereof
US10734704B2 (en) * 2018-11-20 2020-08-04 Advanced Semiconductor Engineering, Inc. Antenna package and method of manufacturing the same
KR102499038B1 (en) * 2018-12-06 2023-02-13 삼성전자주식회사 Antenna module
WO2020157916A1 (en) * 2019-01-31 2020-08-06 三菱電機株式会社 Antenna device and radar device
US10818588B2 (en) * 2019-01-31 2020-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device, package structure and method of fabricating the same
DE102019202715A1 (en) 2019-02-28 2020-09-03 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. FILM-BASED PACKAGE WITH DISTANCE COMPENSATION
DE102019202716B4 (en) * 2019-02-28 2020-12-24 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. FLEX FILM PACKAGE WITH COPLANAR TOPOLOGY FOR HIGH FREQUENCY SIGNALS AND PROCESS FOR MANUFACTURING SUCH A FLEX FILM PACKAGE
DE102019202718B4 (en) 2019-02-28 2020-12-24 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Thin dual foil package and method of making the same
DE102019202721B4 (en) 2019-02-28 2021-03-25 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. 3D FLEX FILM PACKAGE
DE102019110840A1 (en) * 2019-04-26 2020-10-29 Infineon Technologies Ag RF DEVICES WITH COMPLIANT ANTENNAS AND METHODS OF MANUFACTURING THEREOF
US11233328B2 (en) * 2019-09-10 2022-01-25 Plume Design, Inc. Dual-band antenna, device and method for manufacturing
CN112908977A (en) * 2019-11-19 2021-06-04 富泰华工业（深圳）有限公司 Packaged antenna, packaged antenna array and manufacturing method of packaged antenna
CN110911835B (en) * 2019-12-02 2022-07-22 青岛歌尔智能传感器有限公司 Antenna device and manufacturing method thereof
CN111063673A (en) * 2019-12-04 2020-04-24 上海先方半导体有限公司 Substrate-free integrated antenna packaging structure and manufacturing method thereof
CN110943054A (en) * 2019-12-06 2020-03-31 上海先方半导体有限公司 Multichannel AiP packaging structure and preparation method thereof
CN111128909A (en) * 2019-12-10 2020-05-08 中国电子科技集团公司第五十八研究所 Radio frequency system micro packaging structure and preparation method thereof
US11456227B2 (en) * 2019-12-17 2022-09-27 Nxp Usa, Inc. Topside heatsinking antenna launcher for an integrated circuit package
US11296424B2 (en) * 2020-01-21 2022-04-05 Rockwell Collins, Inc. Bump mounted radiating element architecture
CN111681998A (en) * 2020-05-15 2020-09-18 华南理工大学 Chip carrier assembly, communication chip carrier assembly and communication system
JP6985477B1 (en) 2020-09-25 2021-12-22 アオイ電子株式会社 Semiconductor devices and methods for manufacturing semiconductor devices
EP4044366B1 (en) * 2021-02-12 2023-10-25 Sivers Wireless AB An integrated circuit package comprising a crossed dipole antenna
WO2023121524A1 (en) * 2021-12-22 2023-06-29 Telefonaktiebolaget Lm Ericsson (Publ) Thermal interconnect for integrated circuitry
TWI793024B (en) * 2022-05-26 2023-02-11 矽品精密工業股份有限公司 Electronic package and manufacturing method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120286049A1 (en) * 2011-05-12 2012-11-15 Waveconnex, Inc. Scalable high-bandwidth connectivity
US20140145883A1 (en) * 2012-11-26 2014-05-29 International Business Machines Corporation Millimeter-wave radio frequency integrated circuit packages with integrated antennas
US20140266947A1 (en) * 2013-03-15 2014-09-18 Advanced Semiconductor Engineering, Inc. Semiconductor structure having aperture antenna

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5314889B2 (en) * 2007-12-27 2013-10-16 新光電気工業株式会社 Electronic device, manufacturing method thereof, wiring board, and manufacturing method thereof
US7852281B2 (en) 2008-06-30 2010-12-14 Intel Corporation Integrated high performance package systems for mm-wave array applications
US8278749B2 (en) 2009-01-30 2012-10-02 Infineon Technologies Ag Integrated antennas in wafer level package
US9007273B2 (en) * 2010-09-09 2015-04-14 Advances Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
CN102324416B (en) 2010-09-16 2015-07-22 日月光半导体制造股份有限公司 Integrated shielding film and semiconductor packaging member of antenna
US20130093067A1 (en) 2011-10-13 2013-04-18 Flipchip International, Llc Wafer level applied rf shields
US8786060B2 (en) 2012-05-04 2014-07-22 Advanced Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
US8952521B2 (en) 2012-10-19 2015-02-10 Infineon Technologies Ag Semiconductor packages with integrated antenna and method of forming thereof
US9431369B2 (en) 2012-12-13 2016-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Antenna apparatus and method
US9419667B2 (en) * 2013-04-16 2016-08-16 Skyworks Solutions, Inc. Apparatus and methods related to conformal coating implemented with surface mount devices
US9252077B2 (en) * 2013-09-25 2016-02-02 Intel Corporation Package vias for radio frequency antenna connections
EP3080841A4 (en) 2013-12-09 2017-08-23 Intel Corporation Antenna on ceramics for a packaged die
US9362234B2 (en) 2014-01-07 2016-06-07 Freescale Semiconductor, Inc. Shielded device packages having antennas and related fabrication methods
US9472859B2 (en) 2014-05-20 2016-10-18 International Business Machines Corporation Integration of area efficient antennas for phased array or wafer scale array antenna applications
US10317512B2 (en) * 2014-12-23 2019-06-11 Infineon Technologies Ag RF system with an RFIC and antenna system
CN204732450U (en) 2015-06-01 2015-10-28 天津钜远科技发展有限公司 A kind of high luminous efficiency diode

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120286049A1 (en) * 2011-05-12 2012-11-15 Waveconnex, Inc. Scalable high-bandwidth connectivity
US20140145883A1 (en) * 2012-11-26 2014-05-29 International Business Machines Corporation Millimeter-wave radio frequency integrated circuit packages with integrated antennas
US20140266947A1 (en) * 2013-03-15 2014-09-18 Advanced Semiconductor Engineering, Inc. Semiconductor structure having aperture antenna

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200212536A1 (en) * 2018-12-31 2020-07-02 Texas Instruments Incorporated Wireless communication device with antenna on package

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