CN110943054A - Multichannel AiP packaging structure and preparation method thereof - Google Patents
Multichannel AiP packaging structure and preparation method thereof Download PDFInfo
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- CN110943054A CN110943054A CN201911240764.7A CN201911240764A CN110943054A CN 110943054 A CN110943054 A CN 110943054A CN 201911240764 A CN201911240764 A CN 201911240764A CN 110943054 A CN110943054 A CN 110943054A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
Abstract
The invention discloses a multi-channel AiP packaging structure, which comprises: a first antenna; the first plastic package layer is arranged below the first antenna; a first re-layout wiring layer disposed below the first plastic encapsulation layer; a second plastic encapsulation layer disposed below the first re-layout wiring layer; the second plastic packaging layer conductive through hole penetrates through the upper surface and the lower surface of the second plastic packaging layer and is electrically connected with the first re-layout wiring layer; the chip is coated by the second plastic packaging layer, and pins on the front surface of the chip leak out of the bottom surface of the second plastic packaging layer; a second re-layout wiring layer disposed below the second plastic package layer and electrically connected to the second plastic package layer conductive vias and the pins of the chip; and an external solder ball disposed below the second re-layout wiring layer and electrically connected to the second re-layout wiring layer.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a multichannel AiP (Antenna-in-Package) packaging structure of a radio frequency communication technology and a preparation method thereof.
Background
Antennas are important components in wireless systems, both in isolation and in integration. Separate antennas are common, and integrated antennas have also silently entered our line of sight. Integrated antennas include both on-chip antennas (AoC) and packaged Antennas (AiP).
AiP is a technology for integrating antenna and chip in package based on packaging material and process to realize system-level wireless function. AiP technology is in line with the trend of increasing the integration level of silicon-based semiconductor technology, and provides a good antenna solution for system-level wireless chips, thus being popular with the manufacturers of chips and packages. AiP technology has a good compromise between antenna performance, cost and volume, and represents an important achievement in antenna technology in recent years. In addition, AiP technology extends antenna antennas to the fields of integrated circuits, packaging, materials and processes, and calls for multidisciplinary collaborative design and system level optimization.
The SiP technology can improve system performance and reduce system power consumption, but different materials and processes are adopted for manufacturing functional modules and packages of the existing Aip antenna, which can cause problems of reduced system reliability, increased system cost and the like.
Disclosure of Invention
To address the problems in the prior art, according to one embodiment of the present invention, there is provided a multi-channel AiP package structure, including:
a first antenna;
the first plastic package layer is arranged below the first antenna;
a first re-layout wiring layer disposed below the first plastic encapsulation layer;
a second plastic encapsulation layer disposed below the first re-layout wiring layer;
the second plastic packaging layer conductive through hole penetrates through the upper surface and the lower surface of the second plastic packaging layer and is electrically connected with the first re-layout wiring layer;
the chip is coated by the second plastic packaging layer, and pins on the front surface of the chip leak out of the bottom surface of the second plastic packaging layer;
a second re-layout wiring layer disposed below the second plastic package layer and electrically connected to the second plastic package layer conductive vias and the pins of the chip; and
and the external solder balls are arranged below the second re-layout wiring layer and are electrically connected to the second re-layout wiring layer.
In an embodiment of the invention, the first re-layout wiring layer comprises a side sub-antenna structure.
In an embodiment of the present invention, the side sub-antenna structure is a yagi antenna structure.
In an embodiment of the present invention, the multi-channel AiP package structure further includes a first molding layer conductive via disposed in the first molding layer, the first molding layer conductive via and a portion of the second molding layer conductive via together forming two arms of a side dipole antenna.
In an embodiment of the present invention, the conductive material of the first plastic package layer conductive via and/or the second plastic package layer conductive via is a copper pillar or a silver paste.
In an embodiment of the present invention, the first antenna is a patch antenna, and the first redistribution routing layer includes a ground layer of the first antenna.
In an embodiment of the present invention, the patch antenna is a single antenna, or a series-fed or parallel-fed antenna array.
In accordance with another embodiment of the present invention, a method of manufacturing a multi-channel AiP package structure is provided,
the method comprises the following steps:
carrying out plastic package on the chip to form a first plastic package layer for coating the chip;
forming a first re-layout wiring layer on the lower surface of the first plastic packaging layer and the surface of the chip;
forming a first plastic packaging layer conductive through hole in the first plastic packaging layer;
forming a second re-layout wiring layer on the upper surface of the first plastic packaging layer;
forming a second plastic packaging layer above the second re-layout wiring layer;
forming a top surface antenna on the upper surface of the second plastic packaging layer; and
and forming an external solder ball electrically connected with the first re-layout wiring layer.
In another embodiment of the present invention, the second re-layout wiring layer includes an under-ground metal layer of the top antenna; the second re-layout routing layer also includes a yagi antenna structure.
In another embodiment of the present invention, the method for manufacturing the multi-channel AiP package structure further includes forming a second molding layer conductive via in the second molding layer, wherein the second molding layer conductive via and a portion of the first molding layer conductive via together form two arms of a side dipole antenna.
The invention provides a multichannel AiP packaging structure and a preparation method thereof, which adopts a multi-layer plastic packaging layer structure (such as a fan-out structure, Fanout), forms an antenna and a bottom connecting layer on the upper surface and the lower surface of a top layer plastic packaging layer, and forms a sub-antenna on the side surface by adopting single-layer metal or multi-layer metal, thereby forming a multi-direction multi-path radiation packaging structure of a multichannel AiP antenna. The multi-channel AiP packaging structure realizes wafer-level packaging by combining a double-layer fan-out process and plastic packaging layer conductive copper Pillar (Mega Pillar) processing, and has the advantages of small thickness, multiple channels, multiple directions and low cost.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.
Fig. 1 illustrates a cross-sectional schematic view of a multi-channel AiP package structure 100, according to one embodiment of the invention.
Fig. 2A-2F illustrate cross-sectional views of a process for forming such a multi-channel AiP package structure 100, according to one embodiment of the invention.
Fig. 3 illustrates a flow diagram 300 for forming such a multi-channel AiP package structure 100 according to one embodiment of the invention.
Fig. 4 illustrates a cross-sectional schematic view of a multi-channel AiP package structure 400 according to yet another embodiment of the invention.
Fig. 5 illustrates a flow diagram 500 for forming such a multi-channel AiP package structure 400 according to yet another embodiment of the invention.
Detailed Description
In the following description, the invention is described with reference to various embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention may be practiced without specific details. Further, it should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
Reference in the specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
It should be noted that, in the embodiments of the present invention, the process steps are described in a specific order, however, this is only for convenience of distinguishing the steps, and the order of the steps is not limited, and in different embodiments of the present invention, the order of the steps may be adjusted according to the adjustment of the process.
The invention provides a multichannel AiP packaging structure and a preparation method thereof, which adopts a multi-layer plastic packaging layer structure (such as a fan-out structure, Fanout), forms an antenna and a bottom connecting layer on the upper surface and the lower surface of a top layer plastic packaging layer, and forms a sub-antenna on the side surface by adopting single-layer metal or multi-layer metal, thereby forming a multi-direction multi-path radiation packaging structure of a multichannel AiP antenna. The multi-channel AiP packaging structure realizes wafer-level packaging by combining a double-layer fan-out process and plastic packaging layer conductive copper Pillar (Mega Pillar) processing, and has the advantages of small thickness, multiple channels, multiple directions and low cost.
A multi-channel AiP package structure according to one embodiment of the invention is described in detail below with reference to fig. 1. Fig. 1 illustrates a cross-sectional schematic view of a multi-channel AiP package structure 100, according to one embodiment of the invention. As shown in fig. 1, the multi-channel AiP package 100 further includes a first antenna 110, a first molding compound layer 120, a first molding compound layer conductive via 130, a first redistribution layer 140, a second molding compound layer 150, a second molding compound layer conductive via 160, a chip 170, a second redistribution layer 180, and an external solder ball 190.
The first antenna 110 is disposed on the top surface of the multi-channel AiP package 100, and the first antenna 110 may be a patch antenna, a slot antenna, or another antenna using a coupled feed line. In one embodiment of the present invention, the first antenna 110 is disposed over the top surface of the first molding layer 120. In yet another embodiment of the present invention, the first antenna 110 is partially or completely embedded from the upper surface of the first molding layer 120. In yet another embodiment of the present invention, the first antenna 110 is located inside the first molding layer 120 adjacent to the upper surface.
The first plastic package layer conductive via 130 is located inside the first plastic package layer 120, and the material of the first plastic package layer conductive via 130 may be conductive metal such as copper, aluminum, or other conductive materials such as cured conductive silver paste. In one embodiment of the present invention, the first molding compound conductive via 130 is a super copper Pillar (Mega pilar) penetrating the upper and lower surfaces of the first molding compound 120.
The first re-layout wiring layer 140 is located under the first molding layer 120, and further includes a conductive trace 140-1 and a first antenna ground layer 140-2. In one embodiment of the present invention, the conductive traces 140-1 of the first re-layout wiring layer 140 are electrically connected to the first molding layer conductive vias 130. In yet another embodiment of the present invention, the first re-layout wiring layer 140 includes a multi-layer wiring layer structure, which is determined according to design requirements.
The second molding layer 150 is disposed under the first re-layout wiring layer 140. The second molding compound layer 150 is mainly used for wafer reconfiguration of the chip 170 therein to realize fan-out (Fanout).
The second molding layer conductive via 160 is disposed inside the second molding layer 150 and penetrates the second molding layer 150. In one embodiment of the present invention, the second molding layer conductive via 160 further includes an interconnect via 160-1 and an antenna arm 160-2 that mates with the first molding layer conductive via 130, thereby forming two arms of a sub-antenna. In a particular embodiment of the invention, the sub-antennas are dipole antennas.
The chip 170 is disposed to be covered by the second molding layer 150. In one embodiment of the present invention, the top and side surfaces of the chip 170 are covered by the second molding layer 150, and the bottom surface leaks from the bottom surface of the second molding layer 150, thereby realizing the lead-out of the electrode.
The second re-layout wiring layer 180 is disposed on the bottom surface of the second molding layer 150, and is electrically connected to the pads of the chip 170 and the second molding layer conductive vias 160, so as to implement electrical and/or signal interconnection and communication. In one embodiment of the present invention, the second re-layout wiring layer 180 has a single layer or a plurality of layers.
In addition, dielectric layers are disposed between the same metal layers of the first and/or second re-layout wiring layers 140 and 180, and between adjacent metal layers, so as to perform insulating and mechanical supporting functions.
The process of forming such a multi-channel AiP package structure 100 is described in detail below in conjunction with fig. 2A-2F and fig. 3. Fig. 2A-2F illustrate cross-sectional views of a process for forming such a multi-channel AiP package structure 100 according to one embodiment of the invention; fig. 3 illustrates a flow diagram 300 for forming such a multi-channel AiP package structure 100 according to one embodiment of the invention.
First, in step 310, as shown in fig. 2A, the chip 201 is subjected to plastic molding to form a first molding layer 202 covering the chip 201. In an embodiment of the present invention, the step may be completed by attaching the chip 201 to a temporary carrier plate that can be detachably bonded, and after the step of molding, removing the temporary carrier plate by detaching the bonding, which is a conventional wafer reconfiguration process in a fan-out process.
Next, at step 320, as shown in fig. 2B, a first re-layout wiring layer 203 is formed on the lower surface of the first molding layer 202 and the surface of the chip 201, and the first re-layout wiring layer 203 forms electrical and/or signal interconnections with the chip 201. In an embodiment of the present invention, the first re-layout wiring layer 203 may be formed by patterned plating, and the first re-layout wiring layer 203 may be a single layer or multiple layers according to design requirements, wherein an external connection pad (not shown in the figure) is further disposed on the outermost wiring layer.
Then, in step 330, as shown in fig. 2C, a first molding layer conductive via 204 is formed inside the first molding layer 202, and a second re-layout wiring layer 205 is formed on the upper surface of the first molding layer 202. In one embodiment of the present invention, the first molding layer conductive via 204 further includes an interconnect via 204-1 and an antenna arm 204-2 of the sub-antenna; the second redistribution routing layer 205 further includes an interconnection line 205-1 and a top antenna ground layer 205-2, and a dielectric layer is disposed between the normal metal and the adjacent metal of the second redistribution routing layer 205. In an embodiment of the present invention, the first molding compound layer conductive via 204 may be a metal via formed by a via, electroplating, or the like, or a conductive via formed by a via, filled with a conductive silver paste, or the like.
Next, in step 340, as shown in fig. 2D, a second molding layer 206 is formed over the second re-layout wiring layer 205.
Then, in step 350, as shown in fig. 2E, a second molding layer conductive via 207 is formed inside the second molding layer 206, and the top antenna 208 is formed on the upper surface of the second molding layer 206. The top antenna 208 may be a patch antenna, a slot antenna, or other antenna using a coupled feed line. In one embodiment of the present invention, the top antenna 208 is disposed over the top surface of the second molding layer 206. In yet another embodiment of the present invention, the top antenna 208 is partially or fully embedded from the top surface of the second molding layer 206. In yet another embodiment of the present invention, the top antenna 208 is located inside the second molding layer 206 adjacent to the upper surface. In one embodiment of the present invention, the top antenna 208 is formed by performing patterned plating through processes such as sputtering a plating seed layer, photolithography to form a plating mask, plating, removing the photolithography mask, removing the plating seed layer, and the like. In another embodiment of the present invention, the second molding layer conductive via 207 is similar to the first molding layer conductive via 204, and may be a metal via formed by a via, electroplating, or the like, or a conductive via formed by a via, filled with a conductive silver paste, or the like.
Finally, in step 360, as shown in fig. 2F, external solder balls 209 electrically connected to the first re-layout wiring layer 203 are formed. In an embodiment of the invention, external solder balls may be formed on the external pads (not shown) of the first redistribution layer 203 by ball-planting or electroplating, in combination with a reflow process.
A multi-channel AiP package structure according to yet another embodiment of the invention is described below in conjunction with fig. 4. Fig. 4 illustrates a cross-sectional schematic view of a multi-channel AiP package structure 400 according to yet another embodiment of the invention. As shown in fig. 4, the multi-channel AiP package structure 400 further includes a first antenna 410, a first molding compound layer 420, a first redistribution layer 430, a second planar antenna 440, a second molding compound layer 450, a second molding compound layer conductive via 460, a chip 470, a second redistribution layer 480, and an external solder ball 490.
The multi-channel AiP package 400 differs from the multi-channel AiP package 100 described above only in that the second planar antenna 440 is used instead of a dipole antenna, and thus conductive vias do not need to be fabricated within the first molding layer 420 as antenna arms of the dipole antenna. In one embodiment of the present invention, the second planar antenna 440 is a yagi antenna.
The process of forming such a multi-channel AiP package structure 400 is briefly described below in conjunction with fig. 5. Fig. 5 illustrates a flow diagram 500 for forming such a multi-channel AiP package structure 400 according to yet another embodiment of the invention.
First, in step 510, a chip is plastic-packaged to form a first plastic-packaging layer covering the chip.
Next, in step 520, a first re-layout wiring layer is formed on the lower surface of the first molding compound layer and the surface of the chip.
Then, in step 530, a first molding layer conductive via is formed inside the first molding layer, and a second re-layout wiring layer and a second planar antenna are formed on the upper surface of the first molding layer.
Next, at step 540, a second molding layer is formed over the second re-layout wiring layer.
Then, in step 550, a top antenna is formed on the upper surface of the second molding layer.
Finally, at step 560, external solder balls electrically connected to the first re-layout wiring layer are formed.
Based on the multichannel AiP packaging structure and the preparation method thereof provided by the invention, a multi-layer plastic packaging layer structure (such as a fan-out structure, Fanout) is adopted, antennas and bottom connection layers are formed on the upper surface and the lower surface of a top layer plastic packaging layer, and sub-antennas are formed on the side surfaces by adopting single-layer metal or multi-layer metal, so that the multi-direction multi-path radiation packaging structure of the multichannel AiP antenna is formed. The multi-channel AiP packaging structure realizes wafer-level packaging by combining a double-layer fan-out process and plastic packaging layer conductive copper Pillar (Mega Pillar) processing, and has the advantages of small thickness, multiple channels, multiple directions and low cost.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various combinations, modifications, and changes can be made thereto without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims (10)
1. A multi-channel AiP package structure, comprising:
a first antenna;
the first plastic package layer is arranged below the first antenna;
a first re-layout wiring layer disposed below the first plastic encapsulation layer;
a second plastic encapsulation layer disposed below the first re-layout wiring layer;
the second plastic packaging layer conductive through hole penetrates through the upper surface and the lower surface of the second plastic packaging layer and is electrically connected with the first re-layout wiring layer;
the chip is coated by the second plastic packaging layer, and pins on the front surface of the chip leak out of the bottom surface of the second plastic packaging layer;
a second re-layout wiring layer disposed below the second plastic package layer and electrically connected to the second plastic package layer conductive vias and the pins of the chip; and
and the external solder balls are arranged below the second re-layout wiring layer and are electrically connected to the second re-layout wiring layer.
2. The multi-channel AiP package structure of claim 1, wherein the first redistribution routing layer includes a side sub-antenna structure.
3. The multi-channel AiP package structure of claim 2, wherein the side sub-antenna structure is a yagi antenna structure.
4. The multi-channel AiP package structure of claim 1, further comprising a first molding layer conductive via disposed in the first molding layer, the first molding layer conductive via and a portion of the second molding layer conductive via together forming two arms of a side dipole antenna.
5. The multi-channel AiP package structure of claim 1 or 4, wherein the conductive material of the first and/or second molding layer conductive vias is a copper pillar or silver paste.
6. The multi-channel AiP package structure of claim 1, wherein the first antenna is a patch antenna, the first redistribution routing layer comprising a ground layer for the first antenna.
7. The multi-channel AiP package structure of claim 1, wherein the patch antenna is a single antenna or a series-fed, parallel-fed antenna array.
8. A method of manufacturing a multi-channel AiP package structure, comprising:
carrying out plastic package on the chip to form a first plastic package layer for coating the chip;
forming a first re-layout wiring layer on the lower surface of the first plastic packaging layer and the surface of the chip;
forming a first plastic packaging layer conductive through hole in the first plastic packaging layer;
forming a second re-layout wiring layer on the upper surface of the first plastic packaging layer;
forming a second plastic packaging layer above the second re-layout wiring layer;
forming a top surface antenna on the upper surface of the second plastic packaging layer; and
and forming an external solder ball electrically connected with the first re-layout wiring layer.
9. The method of manufacturing a multi-channel AiP package structure of claim 8, wherein the second redistribution routing layer includes an under-metal layer of the top antenna; the second re-layout routing layer also includes a yagi antenna structure.
10. The method of manufacturing a multi-channel AiP package structure of claim 8, further comprising forming second molding layer conductive vias in the second molding layer, the second molding layer conductive vias forming two arms of a side dipole antenna with portions of the first molding layer conductive vias.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN201911240764.7A CN110943054A (en) | 2019-12-06 | 2019-12-06 | Multichannel AiP packaging structure and preparation method thereof |
| PCT/CN2020/095307 WO2021109528A1 (en) | 2019-12-06 | 2020-06-10 | Multi-channel aip encapsulation structure and manufacturing method therefor |
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| CN201911240764.7A CN110943054A (en) | 2019-12-06 | 2019-12-06 | Multichannel AiP packaging structure and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021109528A1 (en) * | 2019-12-06 | 2021-06-10 | 上海先方半导体有限公司 | Multi-channel aip encapsulation structure and manufacturing method therefor |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107093598A (en) * | 2016-02-17 | 2017-08-25 | 英飞凌科技股份有限公司 | Semiconductor device including antenna |
| CN110277356A (en) * | 2018-03-16 | 2019-09-24 | 中芯长电半导体（江阴）有限公司 | The encapsulating structure and packaging method of antenna feeder |
| CN110429068A (en) * | 2019-08-09 | 2019-11-08 | 芯光科技新加坡有限公司 | A kind of antenna packages structure and preparation method thereof, communication equipment |
| CN110491863A (en) * | 2018-05-14 | 2019-11-22 | 联发科技股份有限公司 | Semiconductor package |
| CN110491843A (en) * | 2018-05-14 | 2019-11-22 | 联发科技股份有限公司 | Semiconductor packages and its manufacturing method with antenna |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10157807B2 (en) * | 2016-05-26 | 2018-12-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Sensor packages and manufacturing mehtods thereof |
| US10312112B2 (en) * | 2017-06-20 | 2019-06-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated fan-out package having multi-band antenna and method of forming the same |
| KR102117463B1 (en) * | 2017-08-18 | 2020-06-02 | 삼성전기주식회사 | Antenna embedded semiconductor package |
| US10748861B2 (en) * | 2018-05-16 | 2020-08-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure and manufacturing method thereof |
| CN110943054A (en) * | 2019-12-06 | 2020-03-31 | 上海先方半导体有限公司 | Multichannel AiP packaging structure and preparation method thereof |
-
2019
- 2019-12-06 CN CN201911240764.7A patent/CN110943054A/en active Pending
-
2020
- 2020-06-10 WO PCT/CN2020/095307 patent/WO2021109528A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107093598A (en) * | 2016-02-17 | 2017-08-25 | 英飞凌科技股份有限公司 | Semiconductor device including antenna |
| CN110277356A (en) * | 2018-03-16 | 2019-09-24 | 中芯长电半导体（江阴）有限公司 | The encapsulating structure and packaging method of antenna feeder |
| CN110491863A (en) * | 2018-05-14 | 2019-11-22 | 联发科技股份有限公司 | Semiconductor package |
| CN110491843A (en) * | 2018-05-14 | 2019-11-22 | 联发科技股份有限公司 | Semiconductor packages and its manufacturing method with antenna |
| CN110429068A (en) * | 2019-08-09 | 2019-11-08 | 芯光科技新加坡有限公司 | A kind of antenna packages structure and preparation method thereof, communication equipment |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021109528A1 (en) * | 2019-12-06 | 2021-06-10 | 上海先方半导体有限公司 | Multi-channel aip encapsulation structure and manufacturing method therefor |
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| WO2021109528A1 (en) | 2021-06-10 |
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