CN111063673A - Substrate-free integrated antenna packaging structure and manufacturing method thereof - Google Patents
Substrate-free integrated antenna packaging structure and manufacturing method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/50—Structural association of antennas with earthing switches, lead-in devices or lightning protectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q19/00—Combinations of primary active antenna elements and units with secondary devices, e.g. with quasi-optical devices, for giving the antenna a desired directional characteristic
- H01Q19/10—Combinations of primary active antenna elements and units with secondary devices, e.g. with quasi-optical devices, for giving the antenna a desired directional characteristic using reflecting surfaces
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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Abstract
The invention provides a substrate-free integrated antenna packaging structure, which comprises: the antenna layer is embedded or attached to the surface of the first plastic package layer; a chip having chip solder balls; one or more first metal posts; the first metal layer is attached to or embedded in the surface of one side, away from the antenna layer, of the first plastic packaging layer and is electrically connected with the chip and the first metal column; the first dielectric layer covers the surface and the gap of the first metal layer; the second plastic packaging layer covers the surface of the first dielectric layer and wraps the chip and the first metal column; the second dielectric layer is covered on the surface of the second plastic package layer; the second metal layer is formed on the surface of the second dielectric layer and is electrically connected with the first metal column; the third dielectric layer covers the surface and the gap of the second metal layer; and an external solder ball electrically connected to the second metal layer.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a substrate-free integrated antenna packaging technology.
Background
Package-in-Package (AiP) technology integrates an Antenna into a Package carrying a chip through packaging materials and processes. AiP technology has been the mainstream antenna technology in wireless communication systems due to its good compromise of antenna performance, cost and volume.
As shown in fig. 11, the conventional integrated antenna package is manufactured by integrating a PCB and a chip, the chip is mounted on the PCB by flip chip or wire bonding, and the antenna is designed on the surface of the PCB. The PCB in such a package structure is typically a multi-layer board with more than 8 layers, as shown in fig. 12. The packaging volume is large, the product thickness is thick, the signal transmission distance is long, the high-frequency attenuation is large, and the packaging method is not suitable for future terminal products. Meanwhile, the PCB material suitable for the antenna is difficult to obtain and has higher cost.
Accordingly, there is a need for a new integrated antenna package structure and method of making the same that at least partially solves the problems of the prior art.
Disclosure of Invention
In order to solve at least some of the problems in the prior art, an aspect of the present invention provides a substrate-less integrated antenna package structure.
A substrate-less integrated antenna package structure, comprising:
an antenna layer;
the antenna layer is embedded into or attached to the surface of the first plastic package layer;
a chip;
one or more first metal posts;
the first metal layer is attached to or embedded into one side surface, away from the antenna layer, of the first plastic packaging layer, and the first metal layer is electrically connected with the chip and the first metal column;
the first dielectric layer covers the surface and the gap of the first metal layer;
the second plastic packaging layer covers the surface of the first medium layer and wraps the chip and the first metal column;
the second dielectric layer covers the surface of the second plastic package layer;
the second metal layer is formed on the surface of the second dielectric layer and is electrically connected with the first metal column;
the third dielectric layer covers the surface and the gap of the second metal layer; and
and the external solder balls are electrically connected to the second metal layer.
Further, the substrate-less integrated antenna package structure may further include one or more second metal posts electrically connected to the antenna layer and the first metal layer.
Furthermore, the chip is attached to the first metal layer through a chip solder ball formed on the chip bonding pad.
Further, the first metal layer realizes a fan-out function of the chip solder balls.
Further, the material of the first metal layer and/or the second metal layer and/or the first metal pillar and/or the second metal pillar is copper, silver, gold, tin.
Further, the material of the first plastic package layer and/or the second plastic package layer is composed of resin and filler.
Further, the material of the first medium layer and/or the second medium layer and/or the third medium layer is a liquid or film photosensitive material.
Another aspect of the present invention provides a method for manufacturing a substrate-less integrated antenna package structure, including:
covering a temporary film on the slide;
forming an antenna layer on the temporary film;
forming a first plastic packaging layer;
forming a first metal layer on the surface of the first plastic package layer;
covering a first dielectric layer on the first metal layer, and removing part of the first dielectric layer through an exposure or development technology to expose at least one external bonding pad of the first metal layer;
manufacturing a first metal column on one or more external bonding pads of the first metal layer;
adding a chip solder ball on the surface of the chip bonding pad, and inversely mounting the chip on the bonding pad of the first metal layer;
forming a second plastic packaging layer;
covering a second dielectric layer on the surface of the second plastic package layer, and removing part of the second dielectric layer through an exposure or development technology to expose the surface of the first metal column;
forming a second metal layer on the surface of the second dielectric layer;
covering a third dielectric layer on the surface of the second metal layer, and removing part of the third dielectric layer through an exposure or development technology to expose at least one external bonding pad of the second metal layer;
manufacturing a solder ball on one or more external bonding pads of the second metal layer; and
and removing the slide glass and the temporary film.
Further, the method further comprises forming a second metal pillar on the surface of the antenna layer.
In another aspect, the present invention provides a method for manufacturing a substrate-less integrated antenna package structure, including:
covering a temporary film on the slide;
forming a third dielectric layer on the surface of the temporary film, and removing part of the third dielectric layer by exposure or development technology;
forming a second metal layer on the third dielectric layer;
covering a second dielectric layer on the surface of the second metal layer, and removing part of the second dielectric layer through an exposure or development technology to expose at least one external bonding pad of the second metal layer;
manufacturing a first metal column on one or more external bonding pads of the second metal layer;
adding a chip solder ball on the surface of the chip bonding pad, and attaching the chip to the second medium layer;
forming a second plastic packaging layer;
covering a first dielectric layer on the surface of the second plastic package layer, and removing part of the first dielectric layer through an exposure or development technology to expose the surface of the first metal column and the solder balls of the chip;
forming a first metal layer on the first dielectric layer;
forming a first plastic packaging layer;
forming an antenna layer on the surface of the plastic packaging layer;
removing the slide glass and the temporary film; and
and manufacturing solder balls on the external connection pads of one or more second metal layers.
Further, the method further includes covering a fourth dielectric layer on the surface of the first metal layer, removing a part of the fourth dielectric layer through an exposure or development technology to expose at least one external bonding pad of the first metal layer, and manufacturing a second metal column on one or more external bonding pads of the first metal layer.
The invention provides a substrate-free integrated antenna packaging structure and a manufacturing method thereof, and three-dimensional integration of chip wiring is realized by adopting a substrate-free fan-out packaging process. The whole thickness of the packaging structure is thinner, and meanwhile, the back surface of the packaging structure can be coated with copper and cloth balls in a large area, so that the heat dissipation performance is good; the millimeter wave chip is externally interconnected with the P/G IO at a low speed through the bottom metal column; the upper layer structure comprises a feed structure and a reflecting surface and can be arranged in an array; the packaging structure can realize multi-chip 3D integration.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the present invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.
Fig. 1 illustrates a cross-sectional schematic view of a substrate-less integrated antenna package structure according to an embodiment of the present invention;
fig. 2 shows a cross-sectional schematic view of a substrate-less integrated antenna package structure according to yet another embodiment of the invention;
fig. 3 illustrates a cross-sectional view of a substrate-less integrated antenna package structure according to yet another embodiment of the present invention;
fig. 4 shows a cross-sectional schematic view of a substrate-less integrated antenna package structure according to yet another embodiment of the invention;
fig. 5A-5O are cross-sectional schematic diagrams illustrating a process of forming a substrate-less integrated antenna package structure according to one embodiment of the invention;
fig. 6A-6O are cross-sectional schematic diagrams illustrating a process of forming a substrate-less integrated antenna package structure according to yet another embodiment of the invention; and
fig. 7 illustrates a flow diagram for forming a substrate-less integrated antenna package structure according to an embodiment of the present invention;
fig. 8 illustrates a flow diagram for forming a substrate-less integrated antenna package structure according to yet another embodiment of the present invention;
fig. 9 illustrates a flow diagram for forming a substrate-less integrated antenna package structure according to yet another embodiment of the present invention;
fig. 10 illustrates a flow diagram for forming a substrate-less integrated antenna package structure according to yet another embodiment of the present invention;
fig. 11 illustrates a structure of an organic substrate integrated antenna package in the related art; and
fig. 12 is a schematic diagram illustrating a structure of an organic substrate of an integrated antenna package in the prior art.
Detailed Description
In the following description, the present invention is described with reference to examples. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention is not limited to these specific details. Further, it should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
In the present invention, "disposed on …", "disposed over …" and "disposed over …" do not exclude the presence of an intermediate therebetween, unless otherwise specified. Further, "disposed on or above …" merely indicates the relative positional relationship between two components, and may also be converted to "disposed below or below …" and vice versa in certain cases, such as after reversing the product direction.
Reference in the specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
It should be noted that the embodiment of the present invention describes the process steps in a specific order, however, this is only for the purpose of illustrating the specific embodiment, and does not limit the sequence of the steps. Rather, in various embodiments of the present invention, the order of the steps may be adjusted according to process adjustments.
A substrate-less integrated antenna package structure according to an embodiment of the invention is described in detail below with reference to fig. 1. Fig. 1 illustrates a cross-sectional schematic view of a substrate-less integrated antenna package structure 100 according to an embodiment of the invention. As shown in fig. 1, the substrate-less integrated antenna package structure 100 includes an antenna layer 101, a chip 102, a first molding compound layer 111, a second molding compound layer 112, a first metal layer 121, a second metal layer 122, a first metal pillar 131, a first dielectric layer 141, a second dielectric layer 142, a third dielectric layer 143, and an external solder ball 150.
The first molding compound layer 111 wraps the antenna layer 101, but the surface of the antenna layer 101 is exposed, the material of the antenna layer 101 may be copper, silver or gold, and the material of the first molding compound layer 111 is composed of resin and filler.
The first metal layer 121 is formed on a surface of the first molding compound layer 111 away from the antenna layer to electrically connect the chip 102 and the first metal pillar 131, and the material of the first metal layer 121 and/or the first metal pillar 131 may be copper, silver, tin, or gold.
The first dielectric layer 141 covers the surface of the first metal layer 121, the gaps between the metal wires and the gaps between the copper pillars and the chip solder balls, and plays an insulating role. The material of the first dielectric layer 141 is a photosensitive material, and may be a liquid or film material.
The second molding compound layer 112 is disposed to cover the chip 102 and the first metal pillar 131, but exposes an end surface of the first metal pillar 131, and the material of the second molding compound layer 112 is composed of resin and filler.
The second dielectric layer 142 covers the surface of the second molding compound layer 112, but exposes the end surface of the first metal pillar 131. The material of the second medium layer 142 is a photosensitive material, and may be a liquid or film material.
The second metal layer 122 is formed on the surface of the second dielectric layer 142 to electrically connect to the first metal pillar 131, and the material of the second metal layer 121 may be copper, silver, gold, or the like.
The third dielectric layer 143 covers the surface of the second metal layer 122 and the gaps between the metal wires, thereby performing an insulation protection function. The material of the third dielectric layer 143 is a photosensitive material, and may be a liquid or film material.
Fig. 2 illustrates a cross-sectional view of a substrate-less integrated antenna package structure 200 according to yet another embodiment of the invention. As shown in fig. 2, the difference between the substrate-less integrated antenna package structure 200 and the substrate-less integrated antenna package structure 100 is that the substrate-less integrated antenna package structure 200 further includes a second metal pillar 232, the second metal pillar 232 is wrapped in the first molding compound layer 211 to achieve electrical connection with the antenna layer 201 and the first metal layer 221, and the second metal pillar 232 may be made of copper, silver, gold, or the like.
Fig. 3 illustrates a cross-sectional view of a substrate-less integrated antenna package structure 300 according to yet another embodiment of the invention. As shown in fig. 3, the difference between the substrate-less integrated antenna package structure 300 and the substrate-less integrated antenna package structure 100 is that the antenna layer 301 is formed on the surface of the first plastic package layer 311, the first metal layer 321 is embedded in the other side surface of the first plastic package layer 311, and the first dielectric layer 341 covers the surface of the first plastic package layer 311 having the first metal layer 321, and exposes a portion of the external bonding pads of the first metal layer 321.
Fig. 4 illustrates a cross-sectional view of a substrate-less integrated antenna package structure 400 according to yet another embodiment of the invention. As shown in fig. 4, the difference between the substrate-less integrated antenna package structure 400 and the substrate-less integrated antenna package structure 300 is that the substrate-less integrated antenna package structure 400 further includes a fourth dielectric layer 444 and a second metal pillar 432, the second metal pillar 432 is wrapped in the first plastic package layer 411 to achieve electrical connection with the antenna layer 401 and the first metal layer 421, and the fourth dielectric layer 444 covers the surface of the first metal layer 421 and the gap between the metal wires to achieve the insulation protection effect. The material of the fourth dielectric layer 444 is a photosensitive material, and may be a liquid or film material, and the material of the second metal pillar 432 may be copper, silver, gold, or the like.
The process of forming the substrate-less integrated antenna package structure 100 is described in detail below with reference to fig. 5A to 5N and fig. 7. Fig. 5A-5N are schematic cross-sectional views illustrating a process of forming the integrated antenna package without a substrate according to an embodiment of the invention; fig. 7 illustrates a flow diagram 700 for forming such a substrate-less integrated antenna package structure according to an embodiment of the present invention.
First, at step 701, as shown in fig. 5A, a slide 002 is covered with a temporary film 003. Wherein the slide 002 can be wafer, glass, metal, ceramic, silicon, etc; the temporary film 003 is a detachable adhesive material such as heat or light.
Next, in step 702, as shown in fig. 5B, the antenna layer 101 is formed on the surface of the temporary film 003. The specific forming method may form a seed layer on the surface of the temporary film 003 by processes such as electroless plating and PVD, coat a photoresist by means of lamination, pasting, printing, spin coating, and the like, and then perform steps such as exposure, development, electroplating, photoresist removal, and excess seed layer removal to form the antenna layer 101.
Next, in step 703, as shown in fig. 5C, a first molding layer 111 is formed. The first molding layer 111 covers the antenna layer 101.
Next, in step 704, as shown in fig. 5D, a first metal layer 121 is formed on the surface of the first molding layer 111. The specific forming method may form a seed layer on the surface of the first plastic package layer 111 through processes such as chemical plating and PVD, coat a photoresist through methods such as lamination, patch, printing, spin coating, and the like, and then perform steps such as exposure, development, electroplating, photoresist removal, and removal of an excess seed layer, to form the first metal layer 121.
Next, in step 705, as shown in fig. 5E, a first dielectric layer 141 is formed on the first metal layer 121, and a portion of the first dielectric layer 141 is removed by exposure or development, so as to expose at least one external pad of the first metal layer 121.
Next, in step 706, as shown in fig. 5F, a first metal pillar 131 is formed on at least one external pad of the first metal layer 121 by electroplating, printing, ball-planting, and the like.
Next, in step 707, as shown in fig. 5G, a chip solder ball 001 is added on the pad surface of the chip 102, and the material of the chip solder ball 001 is copper, nickel, tin, silver, gold, palladium or an alloy thereof.
Next, at step 708, as shown in fig. 5H, the chip 102 is flip-chip mounted on the chip pad between the first metal posts 131, where the first metal layer 121 is preset.
Next, in step 709, as shown in fig. 5I, a second molding layer 112 is formed. The second molding compound layer 112 covers the chip 102 and the first metal pillar 131, and exposes a head of the first metal pillar 131. In an embodiment of the present invention, after the second molding layer 112 is formed, the second molding layer 112 is thinned, milled, and ground to expose the first metal pillar 131.
Next, in step 710, as shown in fig. 5J, the second dielectric layer 142 is covered on the surface of the second molding compound layer 112, and a portion of the second dielectric layer 142 is removed by exposure or development, so as to expose the end surface of the first metal pillar 131.
Next, in step 711, as shown in fig. 5K, a second metal layer 122 is formed on the surface of the second dielectric layer 142. In a specific forming method, a seed layer may be formed on the surface of the second dielectric layer 142 by processes such as chemical plating and PVD, a photoresist may be coated by laminating, pasting, printing, spin coating, and the like, and then the second metal layer 122 may be formed by performing steps such as exposure, development, electroplating, photoresist removal, and excess seed layer removal.
Next, in step 712, as shown in fig. 5L, a third dielectric layer 143 is formed on the second metal layer 122, and a portion of the third dielectric layer 143 is removed by exposure or development, etc. to expose at least one external pad of the second metal layer 122.
Next, in step 713, as shown in fig. 5M, external solder balls 150 are formed on the second metal layer 122. In an embodiment of the present invention, the external solder balls 150 may be formed on at least one external pad of the second metal layer 122 by electroplating, ball-planting, printing, or the like.
Finally, at step 714, the slide 002 and temporary film 003 are removed, as shown in fig. 5N. In an embodiment of the present invention, the temporary bonding layer 002 may be removed by mechanical grinding, chemical etching, dry etching, laser, or heating, depending on the characteristics of the temporary bonding layer 002.
Fig. 8 illustrates a flow chart 800 for forming the substrate-less integrated antenna package structure 200 according to one embodiment of the invention. The difference from the process 700 is that the process 800 adds the step 801 of forming the second metal pillar 232 and the exposing operation of the second metal pillar 232 after forming the antenna layer.
In step 801, as shown in fig. 5O, a second metal pillar 232 is fabricated on the surface of the antenna layer 221 by electroplating, printing, ball-planting, and other processes.
Next, after the first plastic package layer is formed, the first plastic package layer is thinned, milled, and ground to expose the second metal pillar 232. The first molding compound layer covers the antenna layer and the second metal pillar 232.
The remaining steps of the process 800 correspond to the process 700.
The process of forming the substrate-less integrated antenna package structure 300 is described in detail below with reference to fig. 6A to 6N and fig. 9. Fig. 6A-6N are schematic cross-sectional views illustrating a process of forming the integrated antenna package without a substrate according to an embodiment of the invention; fig. 9 illustrates a flow chart 900 for forming such a substrate-less integrated antenna package structure according to an embodiment of the present invention.
First, at step 901, as shown in fig. 6A, a slide 002 is covered with a temporary film 003. Wherein the slide 002 can be wafer, glass, metal, ceramic, silicon, etc; the temporary film 003 is a detachable adhesive material such as heat or light.
Next, in step 902, as shown in fig. 6B, a third dielectric layer 343 is formed on the surface of the temporary film 003, and a portion of the third dielectric layer 343 is removed by exposure or development.
Next, in step 903, as shown in fig. 6C, a second metal layer 322 is formed on the surface of the third dielectric layer 343. The specific forming method may form a seed layer on the surface of the third dielectric layer 343 by processes such as chemical plating, PVD, etc., coat a photoresist by means of lamination, pasting, printing, spin coating, etc., and then perform steps such as exposure, development, electroplating, photoresist removal, removal of excess seed layer, etc., to form the second metal layer 322.
Next, in step 904, as shown in fig. 6D, a second dielectric layer 342 is formed on the second metal layer 322, and a portion of the second dielectric layer 342 is removed by exposure or development, etc. to expose at least one external pad of the second metal layer 322.
Next, in step 905, as shown in fig. 6E, a first metal pillar 331 is formed on at least one external pad of the second metal layer 322 by electroplating, printing, ball-planting, and other processes.
Next, in step 906, as shown in fig. 6F, a chip solder ball 001 is added on the surface of the pad of the chip 302, and the material of the chip solder ball 001 is copper, nickel, tin, silver, gold, palladium or an alloy thereof.
Next, at step 907, as shown in fig. 6G, the chip 302 is mounted on the second metal layer 322 between the first metal posts 331 using an adhesive.
Next, at step 908, as shown in fig. 6H, a second molding layer 312 is formed. The second molding compound layer 312 covers the chip 302 and the first metal pillar 331, and simultaneously exposes the head of the first metal pillar 331 and the chip solder ball 001 of the chip 302. In an embodiment of the invention, after the second molding layer 312 is formed, the first metal pillar 131 and the solder ball 001 of the chip are exposed by thinning, milling and grinding the second molding layer 312.
Next, in step 909, as shown in fig. 6I, the first dielectric layer 341 is covered on the surface of the second molding layer 312, and a portion of the first dielectric layer 341 is removed by exposure or development, so as to expose the end surface of the first metal pillar 331 and the chip solder ball 001.
Next, in step 910, as shown in fig. 6J, a first metal layer 321 is formed on the surface of the first dielectric layer 341. The specific forming method may form a seed layer on the surface of the first dielectric layer 341 through processes such as chemical plating and PVD, coat a photoresist through methods such as lamination, pasting, printing, spin coating, and the like, and then perform steps such as exposure, development, electroplating, photoresist removal, and removal of an excess seed layer, to form the first metal layer 321.
Next, in step 911, as shown in fig. 6K, a first molding layer 311 is formed. The first molding compound layer 311 covers the first metal layer 321.
Next, in step 912, as shown in fig. 6L, the antenna layer 301 is formed on the surface of the first molding layer 311. The specific forming method can be formed by different processes such as electroplating, physical vapor deposition or pasting.
Next, at step 913, as shown in fig. 6M, the slide 002 and the temporary film 003 are removed. In an embodiment of the invention, the carrier 002 and the temporary film 003 can be removed by mechanical polishing, chemical etching, dry etching, laser, or heating according to the characteristics of the temporary bonding layer 002 to expose the third dielectric layer 343 and at least one external pad of the second metal layer 322.
Finally, in step 914, as shown in fig. 6N, external solder balls 350 are formed on the second metal layer 322. In an embodiment of the present invention, the external solder balls 350 may be formed on at least one external pad of the second metal layer 322 by electroplating, ball-planting, printing, or the like.
Fig. 10 illustrates a flow diagram 1000 for forming a substrate-less integrated antenna package structure 400 according to one embodiment of the invention. The difference from the process 900 is that the process 1000 adds the step 1001, the second metal pillar 432 and the end-exposing operation of the second metal pillar 432 after the first metal layer is formed.
Next, a first molding layer 411 is formed. The first molding compound 411 covers the first metal layer 421 and the second metal pillar 432, but exposes an end surface of the second metal pillar 432. The specific implementation method may be that after the first plastic package layer 411 is formed, the first plastic package layer 411 is thinned, milled, and ground to expose the second metal pillar 432.
The remaining steps of the process 1000 are consistent with the process 900.
Based on the substrate-free integrated antenna packaging structure and the manufacturing method thereof provided by the invention, the three-dimensional integration of chip wiring is realized by adopting a substrate-free fan-out packaging process. The whole thickness of the packaging structure is thinner, and meanwhile, the back surface of the packaging structure can be coated with copper and cloth balls in a large area, so that the heat dissipation performance is good; the millimeter wave chip is externally interconnected with the P/G IO at a low speed through the bottom metal column; the upper layer structure comprises a feed structure and a reflecting surface and can be arranged in an array; the packaging structure can realize multi-chip 3D integration.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various combinations, modifications, and changes can be made thereto without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims (10)
1. A substrate-less integrated antenna package structure, comprising:
an antenna layer;
the antenna layer is embedded into or attached to the surface of the first plastic package layer;
a chip including chip solder balls;
one or more first metal posts;
the first metal layer is attached to or embedded in the surface of one side, away from the antenna layer, of the first plastic packaging layer, and the first metal layer is electrically connected with the chip and the first metal column;
the first dielectric layer covers the surface and the gap of the first metal layer;
the second plastic packaging layer covers the surface of the first medium layer and wraps the chip and the first metal column;
the second dielectric layer covers the surface of the second plastic package layer;
the second metal layer is formed on the surface of the second dielectric layer and is electrically connected with the first metal column;
the third dielectric layer covers the surface and the gap of the second metal layer; and
and the external solder balls are electrically connected to the second metal layer.
2. The substrate-less integrated antenna package structure of claim 1, wherein the first metal layer implements a fan-out function for the chip solder balls.
3. The substrate-less integrated antenna package structure of claim 1, wherein a material of the first dielectric layer and/or the second dielectric layer and/or the third dielectric layer is a liquid or film photosensitive material.
4. The substrate-less integrated antenna package structure of claim 1, wherein the material of the first molding compound layer and/or the second molding compound layer is composed of resin and filler.
5. The substrate-less integrated antenna package structure of claim 1, further comprising one or more second metal posts electrically connected to the antenna layer and the first metal layer.
6. The substrate-less integrated antenna package structure of claim 5, wherein a material of the first metal layer and/or the second metal layer and/or the first metal pillar and/or the second metal pillar is copper, silver, gold, tin, or an alloy thereof.
7. A method for manufacturing a substrate-free integrated antenna package structure comprises the following steps:
covering a temporary film on the slide;
forming an antenna layer on the temporary film;
forming a first plastic packaging layer;
forming a first metal layer on the surface of the first plastic package layer;
covering a first dielectric layer on the first metal layer;
removing part of the first dielectric layer to expose at least one external bonding pad of the first metal layer;
manufacturing a first metal column on one or more external bonding pads of the first metal layer;
adding a chip solder ball on the surface of the chip bonding pad, and inversely mounting the chip on the bonding pad of the first metal layer;
forming a second plastic packaging layer;
covering a second dielectric layer on the surface of the second plastic package layer;
removing part of the second dielectric layer to expose the surface of the first metal column;
forming a second metal layer on the surface of the second dielectric layer;
covering a third dielectric layer on the surface of the second metal layer;
removing part of the third dielectric layer to expose at least one external bonding pad of the second metal layer;
manufacturing a solder ball on one or more external bonding pads of the second metal layer; and
and removing the slide glass and the temporary film.
8. The method of manufacturing the substrate-less integrated antenna package structure of claim 7, further comprising forming a second metal pillar on a surface of the antenna layer.
9. A method for manufacturing a substrate-free integrated antenna package structure comprises the following steps:
covering a temporary film on the slide;
forming a third dielectric layer on the surface of the temporary film;
removing part of the third medium layer;
forming a second metal layer on the third dielectric layer;
covering a second dielectric layer on the surface of the second metal layer;
removing part of the second dielectric layer to expose at least one external bonding pad of the second metal layer;
manufacturing a first metal column on one or more external bonding pads of the second metal layer;
adding a chip solder ball on the surface of the chip bonding pad, and attaching the chip to the second medium layer;
forming a second plastic packaging layer;
covering a first dielectric layer on the surface of the second plastic package layer;
removing part of the first dielectric layer to expose the surface of the first metal column and the solder balls of the chip;
forming a first metal layer on the first dielectric layer;
forming a first plastic packaging layer;
forming an antenna layer on the surface of the plastic packaging layer;
removing the slide glass and the temporary film; and
and manufacturing solder balls on the external connection pads of one or more second metal layers.
10. The method of claim 9, further comprising covering a fourth dielectric layer on the surface of the first metal layer, removing a portion of the fourth dielectric layer to expose at least one external pad of the first metal layer, and forming a second metal pillar on one or more external pads of the first metal layer.
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| CN201911224624.0A CN111063673A (en) | 2019-12-04 | 2019-12-04 | Substrate-free integrated antenna packaging structure and manufacturing method thereof |
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| CN201911224624.0A CN111063673A (en) | 2019-12-04 | 2019-12-04 | Substrate-free integrated antenna packaging structure and manufacturing method thereof |
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| CN103872012A (en) * | 2012-12-13 | 2014-06-18 | 台湾积体电路制造股份有限公司 | Antenna Apparatus and Method |
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| CN108615721A (en) * | 2016-12-13 | 2018-10-02 | 台湾积体电路制造股份有限公司 | Chip package |
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| US20190115271A1 (en) * | 2016-05-26 | 2019-04-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor packages and manufacturing mehtods thereof |
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| CN103872012A (en) * | 2012-12-13 | 2014-06-18 | 台湾积体电路制造股份有限公司 | Antenna Apparatus and Method |
| CN107093598A (en) * | 2016-02-17 | 2017-08-25 | 英飞凌科技股份有限公司 | Semiconductor device including antenna |
| US20190115271A1 (en) * | 2016-05-26 | 2019-04-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor packages and manufacturing mehtods thereof |
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