US20220117093A1 - Method of fabricating circuit board - Google Patents
Method of fabricating circuit board Download PDFInfo
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- US20220117093A1 US20220117093A1 US17/068,905 US202017068905A US2022117093A1 US 20220117093 A1 US20220117093 A1 US 20220117093A1 US 202017068905 A US202017068905 A US 202017068905A US 2022117093 A1 US2022117093 A1 US 2022117093A1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
- H05K3/384—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal by plating
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
- H05K3/242—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/188—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by direct electroplating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09745—Recess in conductor, e.g. in pad or in metallic substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/17—Post-manufacturing processes
- H05K2203/175—Configurations of connections suitable for easy deletion, e.g. modifiable circuits or temporary conductors for electroplating; Processes for deleting connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
Definitions
- the present invention relates to a circuit board and a method of fabricating the same.
- Electroplating techniques are used in a variety of industrial applications. Take circuit board fabrication as an example, including printed circuit boards, IC carrier, or the like, a circuit board has a substrate such as a core layer or a multilayer wiring board and contact pads on the substrate. Take the core layer as an example, the core layer may include dielectric material such as FR4 resin. Patterned conductive regions are formed on the substrate, and the contact pads can be formed on the conductive regions by an electroplating method. Because the contact pads may serve as interfaces for transmitting signals and currents, if the contact pads have uneven plating thickness on the substrate, that would cause unwanted defects such as assembly abnormity or uneven loading. Therefore, the uniformity of the thickness of the plating metal layer is crucial to the product quality.
- a method of fabricating a circuit board includes forming a conductive layer on a surface of a substrate, and patterning the conductive layer to define a plurality of plating regions and a plurality of plating lines.
- the plating regions have at least two different sizes, a first group of the plating regions are interconnected by a first plating line of the plating lines, and a second group of the plating regions are interconnected by a second plating line of the plating lines, in which a ratio of a total area of the first group of the plating regions to a total area of the second group of the plating regions is from about 1 to about 5.
- a solder mask is formed on the surface of the substrate, in which the solder mask covers the plating lines and partially exposes the plating regions. At least one metal layer is electroplated on the exposed plating regions, in which a topmost surface of the metal layer is below a top surface of the solder mask.
- a ratio of a total area of the first group of the plating regions to a largest one area of the plating regions is from about 1 to about 5.
- a ratio of a largest one area of the plating regions to a total area of the first group of the plating regions is from about 1 to about 5.
- the first group of the plating regions are interconnected by the first plating line in a serial connection manner.
- the method further includes disconnecting the first plating line between adjacent two plating regions of the first group of the plating regions after electroplating the metal layer on the exposed plating regions.
- the method further includes disconnecting the second plating line between adjacent two plating regions of the second group of the plating regions after electroplating the metal layer on the exposed plating regions.
- the method further includes recessing at least one of the plating regions before electroplating the metal layer on the exposed plating regions.
- patterning the conductive layer comprises defining a plating frame, and the first plating line and the second plating line are connected to the plating frame.
- a method of fabricating a circuit board includes forming a conductive layer on a surface of a substrate; patterning the conductive layer to define a plurality of plating regions and a plating line, wherein all of the plating regions are interconnected by the plating line; forming a solder mask on the surface of the substrate, wherein the solder mask covers the plating line and partially exposes the plating regions; and electroplating at least one metal layer on the exposed plating regions, wherein a topmost surface of the metal layer is below a top surface of the solder mask.
- all of the plating regions are interconnected by the plating line in a serial connection manner.
- the method further includes disconnecting the plating line between adjacent two plating regions after electroplating the metal layer on the exposed plating regions.
- the method further includes recessing at least one of the plating regions before electroplating the metal layer on the exposed plating regions.
- patterning the conductive layer comprises defining a plating frame, and the plating line is connected to the plating frame.
- a circuit board includes a substrate, a plurality of contacts disposed on a surface of the substrate, and a solder mask.
- the contacts have a plurality of plating regions and a metal layer on the plating regions, and the plating regions have at least two different sizes.
- the solder mask covers the surface of the substrate and covers edges of the plating regions, in which topmost surfaces of the contacts are below a top surface of the solder mask, and a gap between the topmost surfaces of the contacts and the top surface of the solder mask is larger than 0 ⁇ m and is smaller than 5 ⁇ m.
- the circuit board further includes a plating line extending from a first plating region of the plating regions and terminated at an edge of the substrate.
- the circuit board further includes a plating line tail extending from a second plating region of the plating regions and pointing to a third plating region of the plating regions.
- the plating line tail is connected to the second plating region and is not connected to the third plating region.
- the circuit board further includes two plating line tail extending from adjacent two of the plating regions and pointing to each other.
- each of the contacts includes a nickel layer in contact with the corresponding plating region, and a gold alloy layer on the nickel layer.
- the metal layer is embedded in at least one of the plating regions.
- the current density during the electroplating can be more uniform, such that the plating thickness can be more uniform.
- contacts of the circuit board fabricated by the method can have a uniform thickness.
- FIG. 1A to FIG. 7B show various stages of fabricating a circuit board according to some embodiments of the disclosure.
- FIG. 8 and FIG. 11 are top views of some other embodiments of fabricating the circuit board of the disclosure.
- FIG. 12 and FIG. 13 are cross-sectional views of some stages of other embodiments of fabricating the circuit board of the disclosure.
- the present disclosure provides a method of fabricating a circuit board, in which the current density during the electroplating can be more uniform by properly arranging the layout of the plating regions, such that the plating thickness can be more uniform.
- contacts of the circuit board fabricated by the method can have a uniform thickness.
- FIG. 1A to FIG. 7B show various stages of fabricating a circuit board according to some embodiments of the disclosure, in which FIGS. 1A, 2A, 3A, 4A, 5A, 6A, and 7A are top views, and FIGS. 1B, 2B, 3B, 4B, 5B, 6B, and 7B are cross-sectional views taken along line A-A of FIGS. 1A-7A .
- a substrate 100 is provided.
- the substrate 100 includes a core layer 102 , which may include a plurality through vias therein to connect wiring layer of opposite surfaces of the core layer 102 .
- the core layer 102 may include a resin material such as epoxy resin, polyimide resin, BT (bismaleimide triazine) resin, FR4 resin, or FR5 resin.
- a metal foil 104 such as a film of copper or copper alloy is coated on a surface of the core layer 102 .
- a pre-cleaning process is performed to clean the substrate 100 .
- the pre-cleaning step is carried out to clean the residues from the surface of the substrate 100 , especially to clean the surface of the metal foil 104 , which would otherwise increase the contact resistance.
- the pre-cleaning process is performed to remove the native oxide on the metal foil 104 .
- the pre-cleaning step includes a wet etch or a dry etching process. After the pre-cleaning process is performed, a conductive layer 110 is blanket deposited on the surface of the substrate 100 .
- the conductive layer 110 is formed on the metal foil 104 of the substrate 100 , thus the metal foil 104 can be regarded as a seed layer, such that the conductive layer 110 can be formed uniformly on the surface of the substrate 100 . That is, the conductive layer 110 may have a uniform thickness and is conformally formed on the metal foil 104 of the substrate 100 . In some embodiments, the metal foil 104 entirely covers the core layer 102 , and the conductive layer 110 entirely covers the metal foil 104 .
- a patterning process is performed to the conductive layer 110 and the underlying metal foil 104 to define a plurality of plating regions 120 and a plurality of plating lines 130 .
- the conductive layer 110 and the underlying metal foil 104 are defined with at least one plating frame 190 and at least one clip electrode 140 , in which the plating lines 130 are connected to the plating frame 190 , and the plating frame 190 is connected to the clip electrode 140 by a connecting line 192 .
- the plating regions 120 , the plating lines 130 , the clip electrode 140 , the plating frame 190 , and the connecting line 192 are formed by the same material lamination and are defined by the same etching process.
- the current provided by the clip electrode 140 is sent to the plating frame 190 via the connecting line 192 and then sent to each plating line 130 that is connected to the plating frame 190 , such that the current passes through each plating regions 120 .
- the circuit board may include a plurality of contacts that have different functions, the shapes and/or areas of the contacts may be different to fit application requirements. Therefore, the plating regions 120 that correspond to the contacts may also have different shapes and/or areas.
- the plating regions 120 may include at least one first plating region 120 A that has a larger area and at least one second plating region 120 B that has a smaller area.
- the number of the at least one first plating region 120 A is plural, and the first plating regions 120 A are disposed at the center zone of the substrate 100 .
- the number of the at least one second plating region 120 B is plural, and the second plating regions 120 B are disposed at the peripheral zone of the substrate 100 and surround the first plating regions 120 A.
- the first plating regions 120 A having a larger area may serve as terminals (e.g. fingers) for being in contact with corresponding terminals in a socket or solder pads
- the second plating regions 120 B having a smaller area may serve as test pads, terminals, or solder pads.
- the ratio of the area of each of the first plating regions 120 A to the area of each of the second plating regions 120 B is determined according to the application requirement and can be varied within a huge range.
- the ratio of the area of each of the first plating regions 120 A to the area of each of the second plating regions 120 B can be greater than 5.
- the ratio of the area of each of the first plating regions 120 A to the area of each of the second plating regions 120 B can be greater than 20.
- the ratio of the area of each of the first plating regions 120 A to the area of each of the second plating regions 120 B can be huge, the current that passes through each of the first plating regions 120 A and each of the second plating regions 120 B can be uneven thereby leading to uneven electroplating thickness of the following electroplating process, if each of the first plating regions 120 A and each of the second plating regions 120 B were connected to the plating frame 190 , respectively.
- the plating lines 130 of the present disclosure interconnects all of the second plating regions 120 B, such that the total area of the interconnected second plating regions 120 B would be similar to the first plating region 120 A.
- the first plating region 120 A has the largest area of the plating regions 120 , and each of the first plating regions 120 A is connected to the plating frame 190 by the first plating lines 130 A, respectively.
- the second plating regions 120 B are grouped (one group in the drawing) and interconnected by the second plating line 130 B.
- the grouped second plating regions 120 B are connected to the plating frame 190 by the second plating lines 130 B in a serial connection manner.
- the ratio of each of the first plating regions 120 A to the total area of the grouped plating regions 120 B is from about 1 to about 5. In some other embodiments, the ratio of each of the first plating regions 120 A to the total area of the grouped second plating regions 120 B is from about 5 to about 1.
- the total area of the interconnected second plating regions 120 B would be similar to the area of the first plating region 120 A. Therefore, the plating area that each of the plating lines 130 passes through can be more uniform, and thus the voltage drop and the current of the plating lines 130 can be more uniform accordingly.
- a solder mask 150 is formed on the substrate 100 to control the areas on which electroplating metal is deposited.
- the solder mask 150 formed by one or more photolithography processes.
- the solder mask 150 may include insulating material and may have sufficient thickness to define a plurality of openings 152 over the first plating regions 120 A and the second plating regions 120 B, in which the thickness of the solder mask 150 is thicker than the thickness of the plating regions 120 .
- the solder mask 150 only covers edges of the first plating regions 120 A and the second plating regions 120 B, and most of the areas of the first plating regions 120 A and the second plating regions 120 B are exposed by the solder mask 150 .
- the exposed surfaces of the first plating regions 120 A and the second plating regions 120 B are the area where the electroplating metal is deposited on.
- the solder mask 150 only covers edges of the clip electrode 140 , such that most of the area of the clip electrode 140 is also exposed by the solder mask 150 .
- the solder mask 150 covers the portions of the core layer 102 that are not covered by the first plating regions 120 A, the second plating regions 120 B, and the clip electrode 140 .
- the plating lines 130 , the plating frame 190 , and the connecting lines 192 are buried under the solder mask 150 .
- One or more electroplating processes are performed to form one or more metal layers 160 on the exposed surface of the first plating regions 120 A and the second plating regions 120 B.
- the clip electrode 140 is connected to a power supply through a clip, such that the voltage is applied to the clip electrode 140 , and thus the clip electrode 140 can be regarded as a voltage source of the substrate 100 during the electroplating process.
- the first plating regions 120 A and the grouped second plating regions 120 B are connected to the plating frame 190 by the corresponding plating lines 130 , in which the first plating regions 120 A are connected to the plating frame 190 through the first plating lines 130 A, respectively, and the grouped second plating regions 120 B are connected to the plating frame 190 through the second plating line 130 B.
- the plating frame 190 is connected to the clip electrode 140 through the connecting line 192 , such that the plating frame 190 may have the substantially the same voltage level as that of the clip electrode 140 .
- the second plating regions 120 B that respectively have a smaller area are interconnected by the second plating line 130 B, thus the total area of the interconnected second plating regions 120 B is similar to the first plating region 120 A.
- the voltage drop and the current of each of the plating lines 130 can be more uniform. Therefore, the one or more metal layers 160 formed on the first plating regions 120 A and the second plating regions 120 B may have a uniform thickness.
- the metal layers 160 includes a bottom metal layer 162 and a top metal layer 164 , in which the bottom metal layer 162 is between the top metal layer 164 and the first plating regions 120 A and the second plating regions 120 B.
- the bottom metal layer 162 may include a material that has good bonding ability such as Ni.
- the bottom metal layer 162 also serves as a barrier layer to prevent the top metal layer 164 from diffusing into the core layer 102 .
- the top metal layer 164 may include a material that has higher hardness and is able to prevent the bottom metal layer 162 from oxidation.
- the top metal layer 164 can be such as Au alloy.
- a disconnecting process is performed to disconnect at least one of the plating lines 130 after electroplating the metal layer 160 on the first plating regions 120 A and the second plating regions 120 B.
- the second plating lines 130 B which is utilized to interconnect the second plating regions 120 B, is disconnected after the metal layer 160 is deposited on the first plating regions 120 A and the second plating regions 120 B. More particularly, the second plating line 130 B is disconnected between adjacent two of the second plating regions 120 B, such that the second plating regions 120 B are not directly connected to each other.
- the first plating lines 130 A that individually connect the corresponding first plating regions 120 A to the plating frame 190 are not disconnected.
- the disconnecting process to disconnect the second plating line 130 B can be a laser drilling process, and the laser penetrates the solder mask 150 to disconnect the second plating line 130 B. Therefore, a plurality of the through holes 154 are formed within the solder mask 150 , and portions of the core layer 102 of the substrate 100 are exposed from the through holes 154 .
- a cutting process is performed to cut the substrate 100 and to remove the portion of the substrate 100 having the clip electrode 140 and the plating frame 190 (see FIG. 6A ) thereon, such that a circuit board 200 is obtained.
- the circuit board 200 can be served as an IC carrier or a connecting circuit board.
- the first plating lines 130 A are extended from the corresponding first plating regions 120 A and are terminated at an edge of the circuit board 200 .
- An end of the second plating line 130 B is also terminated at the edge of the circuit board 200 .
- the second plating line 130 B is disconnected after electroplating the metal layer 160 , thus a plurality of plating line tails 132 are present on the circuit board 200 .
- Each of the plating line tails 132 extends from one of the second plating regions 120 B and points to adjacent one of the second plating regions 120 B.
- the plating line tails 132 extended from adjacent pair of the second plating regions 120 B may align with each other.
- Each of the plating line tails 132 is not connected to the adjacent one of the plating line tails 132 or the adjacent one of second plating regions 120 B.
- the circuit board 200 includes the core layer 102 , the plating regions 120 on the core layer 102 , the metal layer 160 on the plating regions 120 , and the solder mask 150 between the plating regions 120 .
- the stacks of the metal foil 104 , the conductive layer 110 , and the metal layer 160 are collectively referred as contacts 180 on the core layer 102 .
- Each of the contacts 180 has a bottom section 182 and a top section 184 , in which the bottom section 182 includes the metal foil 104 and the conductive layer 110 and is covered by the top section 184 and the solder mask 150 , and the top section 184 includes the metal layer 160 and is exposed from the solder mask 150 .
- the width W 1 of the bottom section 182 of the contact 180 is wider than the width W 2 of the top section 184 of the contact 180 .
- the solder mask 150 has a thickness T 1 ranging from the top surface of the core layer 102 to the top surface S 2 of the solder mask 150 .
- the plating region 120 has a thickness T 2 ranging from the top surface of the core layer 102 to the top surface S 3 of the bottom section 182 of the contact 180 .
- the contact 180 has a thickness T 3 ranging from the top surface of the core layer 102 to the topmost surface S 1 of the contact 180 .
- the metal layer 160 has a thickness T 4 ranging from the top surface S 3 of the bottom section 182 of the contact 180 to the topmost surface S 1 of the contact 180 .
- the topmost surface S 1 of each of the contacts 180 is below the top surface S 2 of the solder mask 150 .
- the thickness T 1 of the solder mask 150 is greater than the thickness T 3 of the contact 180 .
- the thickness T 1 of the solder mask 150 is greater than a sum of the thickness T 2 of the plating region 120 and the thickness T 4 of the metal layer 160 , and a gap G is present between the topmost surface S 1 of the contacts 180 and the top surface S 2 of the solder mask 150 .
- the gap G between the topmost surface S 1 of the contact 180 and the top surface S 2 of the solder mask 150 is larger than 0 ⁇ m and is smaller than 5 ⁇ m.
- the gap G between the topmost surface S 1 of the contact 180 and the top surface S 2 of the solder mask 150 is larger than 0 ⁇ m and is smaller than 2 ⁇ m.
- the metal layer 160 of each of the contacts 180 includes the bottom layer 162 such as a nickel layer in contact with the corresponding plating region 120 .
- the metal layer 160 of each of the contacts 180 includes the top metal layer 164 such as a gold alloy layer on the bottom layer 162 .
- the top metal layer 164 provides sufficient hardness to protect the contact 180 from being deformed.
- the substrate 100 having the core layer 102 and the metal foil 104 , and the conductive layer 110 is formed on the surface of the core layer 102
- the substrate can include multilayer wiring board, and the metal foil and the conductive layer, or the plating regions formed by patterning thereof are formed on the surface of the multilayer wiring board. These embodiments are not utilized to limit the invention.
- FIG. 8 and FIG. 9 are top views of some other embodiments of fabricating the circuit board of the disclosure, in which the stage of FIG. 8 and FIG. 9 are same as that of FIG. 3A and FIG. 3B , which follows after stages of FIGS. 1A-2B and are followed by stages of FIGS. 4A-7B .
- plating regions 320 , plating lines 330 , at least one plating frame 390 , at least one clip electrode 340 , and at least one connecting line 392 are formed on the substrate 300 , e.g. the core layer or the multilayer wiring board.
- the plating lines 330 respectively connect to the plating frame 390 , and the plating frame 390 is connected to the clip electrode 340 through the connecting line 392 .
- the plating regions 320 have many sizes and shapes, such as circles and rectangles with different lengths. Based on previously discussion, the plating regions 320 can be grouped, such that the areas of the grouped plating regions 320 become similar.
- some plating regions 320 such as plating regions 320 A are interconnected by the plating line 330 A in a serial connection manner, and shape and size of each plating region of the plating regions 320 A can be not the same.
- some plating regions 320 such as plating regions 320 B are interconnected by the plating line 330 B in a serial connection manner
- some plating regions 320 such as plating regions 320 C are interconnected by the plating line 330 C in a serial connection manner
- some plating regions 320 such as plating regions 320 D are interconnected by the plating line 330 D in a serial connection manner
- the rest plating regions 320 such as plating regions 320 E are interconnected by the plating line 330 E in a serial connection manner.
- the grouped plating regions 320 A, plating regions 320 B, plating regions 320 C, plating regions 320 D, and plating regions 320 E may have similar total area, respectively.
- the area ratio of the group of the plating regions 320 that has the largest total area to the group of the plating regions 320 that has the smallest total area is not greater than 5, to improve electroplating uniform.
- plating regions 420 , plating lines 430 , at least one plating frame 490 , at least one clip electrode 440 , and at least one connecting line 492 are formed on the substrate 400 , e.g. the core layer or the multilayer wiring board.
- the layout of the plating regions 420 is substantially the same as that of FIG. 8 , but the paths of the plating lines 430 are different.
- the number of the plating lines 430 is four in this embodiment, and the plating lines 430 A, 430 B, 430 C, and 430 D respectively interconnect the corresponding plating regions 420 A, plating regions 420 B, plating regions 420 C, and plating regions 420 D in a serial and parallel manner, such that the area ratio among the total areas of each grouped plating regions 420 is not greater than 5.
- the paths and the number of the plating lines can be varied according to different layout requirements, and the connection of the plating regions can be in a serial manner or in a serial and parallel manner, such that the flexibility of process design can be improved accordingly.
- FIG. 10 and FIG. 11 are top views of some other embodiments of fabricating the circuit board of the disclosure, in which the stage of FIG. 10 and FIG. 11 are same as that of FIG. 3A and FIG. 3B , which follows after stages of FIGS. 1A-2B and are followed by stages of FIGS. 4A-7B .
- plating regions 520 , plating lines 530 , at least one plating frame 590 , at least one clip electrode 540 , and at least one connecting line 592 are formed on the substrate 500 , e.g. the core layer or the multilayer wiring board.
- the plating regions 520 are grouped and are interconnected by the corresponding plating lines 530 .
- the plating line 530 A interconnects the plating regions 520 A, and the plating regions 520 A may have at least two sizes and shapes.
- the plating line 530 B interconnects the plating regions 520 B, and the plating regions 520 B may have at least two sizes and shapes.
- the plating line 530 C interconnects the plating regions 520 C, and the plating regions 520 C may have at least two sizes and shapes.
- the plating lines 530 A, 530 B, and 530 C are connected to the plating frame 590 , and the plating frame 590 is connected to the clip electrode 540 through the connecting line 592 .
- the total area of each of the grouped plating regions 520 A, 520 B, and 520 C may be similar.
- the group of plating regions 520 B may have the largest total area of the three groups of plating regions 520 A, 520 B, 520 C, and the group of plating regions 520 A/ 520 C may have the smaller total area of the three groups of plating regions 520 A, 520 B, 520 C.
- a ratio of the total area of the group of plating regions 520 B to the total area of the group of plating regions 520 A/ 520 C is not greater than 5.
- plating regions 620 , plating line 630 , at least one plating frame 690 , at least one clip electrode 640 , and at least one connecting line 692 are formed on the substrate 600 , e.g. the core layer or the multilayer wiring board.
- all of the plating regions 620 are interconnected by a single plating line 630 , in which the plating regions 620 may have at least two sizes and shapes.
- the shapes of the plating regions 620 are not limited to circular or rectangular, the plating regions 620 can be triangle, polygons, or combinations thereof.
- FIG. 12 and FIG. 13 are cross-sectional views of some stages of other embodiment of fabricating the circuit board of the disclosure, in which the stages of FIG. 12 and FIG. 13 follow after stages of FIGS. 1A-4B and are followed by stages of FIGS. 6A-7B .
- the area of the plating regions 720 B on the core layer 702 of the substrate 700 is smaller than the area of the plating regions 720 A.
- the method further includes forming a patterned mask 770 on the substrate 700 to expose the plating regions 720 B that have a smaller area while the plating regions 720 A that has a larger area is covered by the patterned mask 770 .
- the plating regions 720 A, 720 B can be further connected to the plating frame 790 by the plating line 730 .
- each of the recessed plating regions 720 B has a center section 722 exposed by the solder mask 750 and the patterned mask 770 and a peripheral section 724 covered by the solder mask 750 and the patterned mask 770 , in which the thickness of the peripheral section 724 is thicker than the thickness of the center section 722 .
- Each of the plating regions 720 has the metal foil layer 702 and the conductive layer 704 , in which the conductive layer 704 is recessed, and the metal foil layer 702 is covered by the conductive layer 704 .
- the patterned mask 770 is removed, and an electroplating process is performed to deposit the metal layer 760 on the exposed surface of the plating regions 720 .
- the thickness of the metal layer 760 on the plating regions 720 B that have the smaller area has a thickness H 2
- the metal layer 760 on the plating region 720 A that has the larger area has a thickness H 1
- the thickness H 2 is thicker than the thickness H 1 .
- the metal layer 760 is embedded in the plating regions 720 B, and an interface between the metal layer 760 and the plating region 720 B is below an interface between the solder mask 750 and the plating region 720 B.
- the present disclosure provides a method of fabricating a circuit board, in which the current density during the electroplating can be more uniform by properly arranging the layout of the plating regions, such that the plating thickness can be more uniform.
- contacts of the circuit board fabricated by the method can have a uniform thickness.
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Abstract
A method of fabricating a circuit board includes forming a conductive layer on a surface of a substrate, and patterning the conductive layer to define a plurality of plating regions and a plurality of plating lines. The plating regions have at least two different sizes, a first group of the plating regions are interconnected by a first plating line of the plating lines, and a second group of the plating regions are interconnected by a second plating line of the plating lines. A ratio of a total area of the first group of the plating regions to a total area of the second group of the plating regions is from about 1 to about 5. A solder mask is formed on the surface of the substrate to cover the plating lines and partially expose the plating regions. At least one metal layer is electroplated on the exposed plating regions.
Description
- The present invention relates to a circuit board and a method of fabricating the same.
- Electroplating techniques are used in a variety of industrial applications. Take circuit board fabrication as an example, including printed circuit boards, IC carrier, or the like, a circuit board has a substrate such as a core layer or a multilayer wiring board and contact pads on the substrate. Take the core layer as an example, the core layer may include dielectric material such as FR4 resin. Patterned conductive regions are formed on the substrate, and the contact pads can be formed on the conductive regions by an electroplating method. Because the contact pads may serve as interfaces for transmitting signals and currents, if the contact pads have uneven plating thickness on the substrate, that would cause unwanted defects such as assembly abnormity or uneven loading. Therefore, the uniformity of the thickness of the plating metal layer is crucial to the product quality.
- According to some embodiments of the disclosure, a method of fabricating a circuit board includes forming a conductive layer on a surface of a substrate, and patterning the conductive layer to define a plurality of plating regions and a plurality of plating lines. The plating regions have at least two different sizes, a first group of the plating regions are interconnected by a first plating line of the plating lines, and a second group of the plating regions are interconnected by a second plating line of the plating lines, in which a ratio of a total area of the first group of the plating regions to a total area of the second group of the plating regions is from about 1 to about 5. A solder mask is formed on the surface of the substrate, in which the solder mask covers the plating lines and partially exposes the plating regions. At least one metal layer is electroplated on the exposed plating regions, in which a topmost surface of the metal layer is below a top surface of the solder mask.
- In some embodiments, a ratio of a total area of the first group of the plating regions to a largest one area of the plating regions is from about 1 to about 5.
- In some embodiments, a ratio of a largest one area of the plating regions to a total area of the first group of the plating regions is from about 1 to about 5.
- In some embodiments, the first group of the plating regions are interconnected by the first plating line in a serial connection manner.
- In some embodiments, the method further includes disconnecting the first plating line between adjacent two plating regions of the first group of the plating regions after electroplating the metal layer on the exposed plating regions.
- In some embodiments, the method further includes disconnecting the second plating line between adjacent two plating regions of the second group of the plating regions after electroplating the metal layer on the exposed plating regions.
- In some embodiments, the method further includes recessing at least one of the plating regions before electroplating the metal layer on the exposed plating regions.
- In some embodiments, patterning the conductive layer comprises defining a plating frame, and the first plating line and the second plating line are connected to the plating frame.
- According to some embodiments of the disclosure, a method of fabricating a circuit board includes forming a conductive layer on a surface of a substrate; patterning the conductive layer to define a plurality of plating regions and a plating line, wherein all of the plating regions are interconnected by the plating line; forming a solder mask on the surface of the substrate, wherein the solder mask covers the plating line and partially exposes the plating regions; and electroplating at least one metal layer on the exposed plating regions, wherein a topmost surface of the metal layer is below a top surface of the solder mask.
- In some embodiments, all of the plating regions are interconnected by the plating line in a serial connection manner.
- In some embodiments, the method further includes disconnecting the plating line between adjacent two plating regions after electroplating the metal layer on the exposed plating regions.
- In some embodiments, the method further includes recessing at least one of the plating regions before electroplating the metal layer on the exposed plating regions.
- In some embodiments, patterning the conductive layer comprises defining a plating frame, and the plating line is connected to the plating frame.
- According to some embodiments of the disclosure, a circuit board includes a substrate, a plurality of contacts disposed on a surface of the substrate, and a solder mask. The contacts have a plurality of plating regions and a metal layer on the plating regions, and the plating regions have at least two different sizes. The solder mask covers the surface of the substrate and covers edges of the plating regions, in which topmost surfaces of the contacts are below a top surface of the solder mask, and a gap between the topmost surfaces of the contacts and the top surface of the solder mask is larger than 0 μm and is smaller than 5 μm.
- In some embodiments, the circuit board further includes a plating line extending from a first plating region of the plating regions and terminated at an edge of the substrate.
- In some embodiments, the circuit board further includes a plating line tail extending from a second plating region of the plating regions and pointing to a third plating region of the plating regions.
- In some embodiments, the plating line tail is connected to the second plating region and is not connected to the third plating region.
- In some embodiments, the circuit board further includes two plating line tail extending from adjacent two of the plating regions and pointing to each other.
- In some embodiments, each of the contacts includes a nickel layer in contact with the corresponding plating region, and a gold alloy layer on the nickel layer.
- In some embodiments, the metal layer is embedded in at least one of the plating regions.
- By properly arranging the layout of the plating regions, the current density during the electroplating can be more uniform, such that the plating thickness can be more uniform. As a result, contacts of the circuit board fabricated by the method can have a uniform thickness.
- It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the invention as claimed.
- The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
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FIG. 1A toFIG. 7B show various stages of fabricating a circuit board according to some embodiments of the disclosure. -
FIG. 8 andFIG. 11 are top views of some other embodiments of fabricating the circuit board of the disclosure. -
FIG. 12 andFIG. 13 are cross-sectional views of some stages of other embodiments of fabricating the circuit board of the disclosure. - Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
- The present disclosure provides a method of fabricating a circuit board, in which the current density during the electroplating can be more uniform by properly arranging the layout of the plating regions, such that the plating thickness can be more uniform. As a result, contacts of the circuit board fabricated by the method can have a uniform thickness.
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FIG. 1A toFIG. 7B show various stages of fabricating a circuit board according to some embodiments of the disclosure, in whichFIGS. 1A, 2A, 3A, 4A, 5A, 6A, and 7A are top views, andFIGS. 1B, 2B, 3B, 4B, 5B, 6B, and 7B are cross-sectional views taken along line A-A ofFIGS. 1A-7A . Referring toFIG. 1A andFIG. 1B , asubstrate 100 is provided. Thesubstrate 100 includes acore layer 102, which may include a plurality through vias therein to connect wiring layer of opposite surfaces of thecore layer 102. Thecore layer 102 may include a resin material such as epoxy resin, polyimide resin, BT (bismaleimide triazine) resin, FR4 resin, or FR5 resin. In some embodiments, ametal foil 104 such as a film of copper or copper alloy is coated on a surface of thecore layer 102. - Referring to
FIG. 2A andFIG. 2B , a pre-cleaning process is performed to clean thesubstrate 100. For example, the pre-cleaning step is carried out to clean the residues from the surface of thesubstrate 100, especially to clean the surface of themetal foil 104, which would otherwise increase the contact resistance. In some embodiments, the pre-cleaning process is performed to remove the native oxide on themetal foil 104. In some embodiments, the pre-cleaning step includes a wet etch or a dry etching process. After the pre-cleaning process is performed, aconductive layer 110 is blanket deposited on the surface of thesubstrate 100. For example, theconductive layer 110 is formed on themetal foil 104 of thesubstrate 100, thus themetal foil 104 can be regarded as a seed layer, such that theconductive layer 110 can be formed uniformly on the surface of thesubstrate 100. That is, theconductive layer 110 may have a uniform thickness and is conformally formed on themetal foil 104 of thesubstrate 100. In some embodiments, themetal foil 104 entirely covers thecore layer 102, and theconductive layer 110 entirely covers themetal foil 104. - Referring to
FIG. 3A andFIG. 3B , a patterning process is performed to theconductive layer 110 and theunderlying metal foil 104 to define a plurality of platingregions 120 and a plurality of platinglines 130. In some embodiments, theconductive layer 110 and theunderlying metal foil 104 are defined with at least oneplating frame 190 and at least oneclip electrode 140, in which theplating lines 130 are connected to theplating frame 190, and theplating frame 190 is connected to theclip electrode 140 by a connectingline 192. In some embodiments, the platingregions 120, theplating lines 130, theclip electrode 140, theplating frame 190, and the connectingline 192 are formed by the same material lamination and are defined by the same etching process. When an electroplating process is performed, the current provided by theclip electrode 140 is sent to theplating frame 190 via the connectingline 192 and then sent to eachplating line 130 that is connected to theplating frame 190, such that the current passes through each platingregions 120. - Because the circuit board may include a plurality of contacts that have different functions, the shapes and/or areas of the contacts may be different to fit application requirements. Therefore, the plating
regions 120 that correspond to the contacts may also have different shapes and/or areas. - For example, the plating
regions 120 may include at least onefirst plating region 120A that has a larger area and at least onesecond plating region 120B that has a smaller area. In some embodiments, the number of the at least onefirst plating region 120A is plural, and thefirst plating regions 120A are disposed at the center zone of thesubstrate 100. In some embodiments, the number of the at least onesecond plating region 120B is plural, and thesecond plating regions 120B are disposed at the peripheral zone of thesubstrate 100 and surround thefirst plating regions 120A. In some embodiments, thefirst plating regions 120A having a larger area may serve as terminals (e.g. fingers) for being in contact with corresponding terminals in a socket or solder pads, and thesecond plating regions 120B having a smaller area may serve as test pads, terminals, or solder pads. - The ratio of the area of each of the
first plating regions 120A to the area of each of thesecond plating regions 120B is determined according to the application requirement and can be varied within a huge range. For example, the ratio of the area of each of thefirst plating regions 120A to the area of each of thesecond plating regions 120B can be greater than 5. In some embodiments, the ratio of the area of each of thefirst plating regions 120A to the area of each of thesecond plating regions 120B can be greater than 20. - Because the ratio of the area of each of the
first plating regions 120A to the area of each of thesecond plating regions 120B can be huge, the current that passes through each of thefirst plating regions 120A and each of thesecond plating regions 120B can be uneven thereby leading to uneven electroplating thickness of the following electroplating process, if each of thefirst plating regions 120A and each of thesecond plating regions 120B were connected to theplating frame 190, respectively. - To prevent such situation, the
plating lines 130 of the present disclosure interconnects all of thesecond plating regions 120B, such that the total area of the interconnectedsecond plating regions 120B would be similar to thefirst plating region 120A. - For example, the
first plating region 120A has the largest area of theplating regions 120, and each of thefirst plating regions 120A is connected to theplating frame 190 by thefirst plating lines 130A, respectively. Thesecond plating regions 120B are grouped (one group in the drawing) and interconnected by thesecond plating line 130B. The grouped second platingregions 120B are connected to theplating frame 190 by the second plating lines 130B in a serial connection manner. In some embodiments, the ratio of each of thefirst plating regions 120A to the total area of the grouped platingregions 120B is from about 1 to about 5. In some other embodiments, the ratio of each of thefirst plating regions 120A to the total area of the grouped second platingregions 120B is from about 5 to about 1. - By grouping and interconnecting the
second plating regions 120B having smaller area in a serial connection manner, the total area of the interconnectedsecond plating regions 120B would be similar to the area of thefirst plating region 120A. Therefore, the plating area that each of theplating lines 130 passes through can be more uniform, and thus the voltage drop and the current of theplating lines 130 can be more uniform accordingly. - Reference is made to
FIG. 4A andFIG. 4B . Asolder mask 150 is formed on thesubstrate 100 to control the areas on which electroplating metal is deposited. Thesolder mask 150 formed by one or more photolithography processes. Thesolder mask 150 may include insulating material and may have sufficient thickness to define a plurality ofopenings 152 over thefirst plating regions 120A and thesecond plating regions 120B, in which the thickness of thesolder mask 150 is thicker than the thickness of theplating regions 120. - In some embodiments, the
solder mask 150 only covers edges of thefirst plating regions 120A and thesecond plating regions 120B, and most of the areas of thefirst plating regions 120A and thesecond plating regions 120B are exposed by thesolder mask 150. The exposed surfaces of thefirst plating regions 120A and thesecond plating regions 120B are the area where the electroplating metal is deposited on. Similarly, thesolder mask 150 only covers edges of theclip electrode 140, such that most of the area of theclip electrode 140 is also exposed by thesolder mask 150. - In some embodiments, the
solder mask 150 covers the portions of thecore layer 102 that are not covered by thefirst plating regions 120A, thesecond plating regions 120B, and theclip electrode 140. The plating lines 130, theplating frame 190, and the connectinglines 192 are buried under thesolder mask 150. - Reference is made to
FIG. 5A andFIG. 5B . One or more electroplating processes are performed to form one ormore metal layers 160 on the exposed surface of thefirst plating regions 120A and thesecond plating regions 120B. For example, theclip electrode 140 is connected to a power supply through a clip, such that the voltage is applied to theclip electrode 140, and thus theclip electrode 140 can be regarded as a voltage source of thesubstrate 100 during the electroplating process. - The
first plating regions 120A and the grouped second platingregions 120B are connected to theplating frame 190 by the corresponding platinglines 130, in which thefirst plating regions 120A are connected to theplating frame 190 through thefirst plating lines 130A, respectively, and the grouped second platingregions 120B are connected to theplating frame 190 through thesecond plating line 130B. Theplating frame 190 is connected to theclip electrode 140 through the connectingline 192, such that theplating frame 190 may have the substantially the same voltage level as that of theclip electrode 140. - As discussed above, the
second plating regions 120B that respectively have a smaller area are interconnected by thesecond plating line 130B, thus the total area of the interconnectedsecond plating regions 120B is similar to thefirst plating region 120A. The voltage drop and the current of each of theplating lines 130 can be more uniform. Therefore, the one ormore metal layers 160 formed on thefirst plating regions 120A and thesecond plating regions 120B may have a uniform thickness. - In some embodiments, the metal layers 160 includes a
bottom metal layer 162 and atop metal layer 164, in which thebottom metal layer 162 is between thetop metal layer 164 and thefirst plating regions 120A and thesecond plating regions 120B. Thebottom metal layer 162 may include a material that has good bonding ability such as Ni. Thebottom metal layer 162 also serves as a barrier layer to prevent thetop metal layer 164 from diffusing into thecore layer 102. Thetop metal layer 164 may include a material that has higher hardness and is able to prevent thebottom metal layer 162 from oxidation. Thetop metal layer 164 can be such as Au alloy. - Reference is made to
FIG. 6A andFIG. 6B . A disconnecting process is performed to disconnect at least one of theplating lines 130 after electroplating themetal layer 160 on thefirst plating regions 120A and thesecond plating regions 120B. For example, the second plating lines 130B, which is utilized to interconnect thesecond plating regions 120B, is disconnected after themetal layer 160 is deposited on thefirst plating regions 120A and thesecond plating regions 120B. More particularly, thesecond plating line 130B is disconnected between adjacent two of thesecond plating regions 120B, such that thesecond plating regions 120B are not directly connected to each other. In some embodiments, thefirst plating lines 130A that individually connect the correspondingfirst plating regions 120A to theplating frame 190 are not disconnected. - In some embodiments, the disconnecting process to disconnect the
second plating line 130B can be a laser drilling process, and the laser penetrates thesolder mask 150 to disconnect thesecond plating line 130B. Therefore, a plurality of the throughholes 154 are formed within thesolder mask 150, and portions of thecore layer 102 of thesubstrate 100 are exposed from the throughholes 154. - Reference is made to
FIG. 7A andFIG. 7B . A cutting process is performed to cut thesubstrate 100 and to remove the portion of thesubstrate 100 having theclip electrode 140 and the plating frame 190 (seeFIG. 6A ) thereon, such that acircuit board 200 is obtained. Thecircuit board 200 can be served as an IC carrier or a connecting circuit board. - As shown in
FIG. 7A , thefirst plating lines 130A are extended from the correspondingfirst plating regions 120A and are terminated at an edge of thecircuit board 200. An end of thesecond plating line 130B is also terminated at the edge of thecircuit board 200. However, thesecond plating line 130B is disconnected after electroplating themetal layer 160, thus a plurality of platingline tails 132 are present on thecircuit board 200. Each of theplating line tails 132 extends from one of thesecond plating regions 120B and points to adjacent one of thesecond plating regions 120B. Theplating line tails 132 extended from adjacent pair of thesecond plating regions 120B may align with each other. Each of theplating line tails 132 is not connected to the adjacent one of theplating line tails 132 or the adjacent one ofsecond plating regions 120B. - As shown in
FIG. 7B , thecircuit board 200 includes thecore layer 102, the platingregions 120 on thecore layer 102, themetal layer 160 on theplating regions 120, and thesolder mask 150 between the platingregions 120. The stacks of themetal foil 104, theconductive layer 110, and themetal layer 160 are collectively referred ascontacts 180 on thecore layer 102. Each of thecontacts 180 has abottom section 182 and atop section 184, in which thebottom section 182 includes themetal foil 104 and theconductive layer 110 and is covered by thetop section 184 and thesolder mask 150, and thetop section 184 includes themetal layer 160 and is exposed from thesolder mask 150. The width W1 of thebottom section 182 of thecontact 180 is wider than the width W2 of thetop section 184 of thecontact 180. - The
solder mask 150 has a thickness T1 ranging from the top surface of thecore layer 102 to the top surface S2 of thesolder mask 150. Theplating region 120 has a thickness T2 ranging from the top surface of thecore layer 102 to the top surface S3 of thebottom section 182 of thecontact 180. Thecontact 180 has a thickness T3 ranging from the top surface of thecore layer 102 to the topmost surface S1 of thecontact 180. Themetal layer 160 has a thickness T4 ranging from the top surface S3 of thebottom section 182 of thecontact 180 to the topmost surface S1 of thecontact 180. - In some embodiments, the topmost surface S1 of each of the
contacts 180 is below the top surface S2 of thesolder mask 150. The thickness T1 of thesolder mask 150 is greater than the thickness T3 of thecontact 180. The thickness T1 of thesolder mask 150 is greater than a sum of the thickness T2 of theplating region 120 and the thickness T4 of themetal layer 160, and a gap G is present between the topmost surface S1 of thecontacts 180 and the top surface S2 of thesolder mask 150. In some embodiments, the gap G between the topmost surface S1 of thecontact 180 and the top surface S2 of thesolder mask 150 is larger than 0 μm and is smaller than 5 μm. Preferably, the gap G between the topmost surface S1 of thecontact 180 and the top surface S2 of thesolder mask 150 is larger than 0 μm and is smaller than 2 μm. - In some embodiments, the
metal layer 160 of each of thecontacts 180 includes thebottom layer 162 such as a nickel layer in contact with thecorresponding plating region 120. Themetal layer 160 of each of thecontacts 180 includes thetop metal layer 164 such as a gold alloy layer on thebottom layer 162. Thetop metal layer 164 provides sufficient hardness to protect thecontact 180 from being deformed. - Although the embodiment discussed from
FIG. 1A toFIG. 7A relates to thesubstrate 100 having thecore layer 102 and themetal foil 104, and theconductive layer 110 is formed on the surface of thecore layer 102, in some other embodiments, the substrate can include multilayer wiring board, and the metal foil and the conductive layer, or the plating regions formed by patterning thereof are formed on the surface of the multilayer wiring board. These embodiments are not utilized to limit the invention. - Referring to
FIG. 8 andFIG. 9 , which are top views of some other embodiments of fabricating the circuit board of the disclosure, in which the stage ofFIG. 8 andFIG. 9 are same as that ofFIG. 3A andFIG. 3B , which follows after stages ofFIGS. 1A-2B and are followed by stages ofFIGS. 4A-7B . - As shown in
FIG. 8 , platingregions 320, plating lines 330, at least oneplating frame 390, at least oneclip electrode 340, and at least one connectingline 392 are formed on thesubstrate 300, e.g. the core layer or the multilayer wiring board. The plating lines 330 respectively connect to theplating frame 390, and theplating frame 390 is connected to theclip electrode 340 through the connectingline 392. In this embodiment, the platingregions 320 have many sizes and shapes, such as circles and rectangles with different lengths. Based on previously discussion, the platingregions 320 can be grouped, such that the areas of the grouped platingregions 320 become similar. For example, someplating regions 320 such asplating regions 320A are interconnected by theplating line 330A in a serial connection manner, and shape and size of each plating region of theplating regions 320A can be not the same. Similarly, someplating regions 320 such as platingregions 320B are interconnected by theplating line 330B in a serial connection manner, someplating regions 320 such as platingregions 320C are interconnected by theplating line 330C in a serial connection manner, someplating regions 320 such asplating regions 320D are interconnected by theplating line 330D in a serial connection manner, and therest plating regions 320 such asplating regions 320E are interconnected by theplating line 330E in a serial connection manner. - The grouped
plating regions 320A, platingregions 320B, platingregions 320C, platingregions 320D, andplating regions 320E may have similar total area, respectively. For example, the area ratio of the group of theplating regions 320 that has the largest total area to the group of theplating regions 320 that has the smallest total area is not greater than 5, to improve electroplating uniform. - As shown in
FIG. 9 , platingregions 420, plating lines 430, at least oneplating frame 490, at least oneclip electrode 440, and at least one connectingline 492 are formed on thesubstrate 400, e.g. the core layer or the multilayer wiring board. In this embodiment, the layout of theplating regions 420 is substantially the same as that ofFIG. 8 , but the paths of the plating lines 430 are different. For example, the number of the plating lines 430 is four in this embodiment, and theplating lines plating regions 420A, platingregions 420B, platingregions 420C, andplating regions 420D in a serial and parallel manner, such that the area ratio among the total areas of each grouped platingregions 420 is not greater than 5. - Reference is made to both
FIG. 8 andFIG. 9 , the paths and the number of the plating lines can be varied according to different layout requirements, and the connection of the plating regions can be in a serial manner or in a serial and parallel manner, such that the flexibility of process design can be improved accordingly. - Referring to
FIG. 10 andFIG. 11 , which are top views of some other embodiments of fabricating the circuit board of the disclosure, in which the stage ofFIG. 10 andFIG. 11 are same as that ofFIG. 3A andFIG. 3B , which follows after stages ofFIGS. 1A-2B and are followed by stages ofFIGS. 4A-7B . - As shown in
FIG. 10 , platingregions 520, plating lines 530, at least oneplating frame 590, at least oneclip electrode 540, and at least one connectingline 592 are formed on thesubstrate 500, e.g. the core layer or the multilayer wiring board. Theplating regions 520 are grouped and are interconnected by the corresponding plating lines 530. For example, theplating line 530A interconnects theplating regions 520A, and theplating regions 520A may have at least two sizes and shapes. Theplating line 530B interconnects theplating regions 520B, and theplating regions 520B may have at least two sizes and shapes. Theplating line 530C interconnects theplating regions 520C, and theplating regions 520C may have at least two sizes and shapes. The plating lines 530A, 530B, and 530C are connected to theplating frame 590, and theplating frame 590 is connected to theclip electrode 540 through the connectingline 592. The total area of each of the groupedplating regions - For example, the group of plating
regions 520B may have the largest total area of the three groups of platingregions regions 520A/520C may have the smaller total area of the three groups of platingregions regions 520B to the total area of the group of platingregions 520A/520C is not greater than 5. - As shown in
FIG. 11 , platingregions 620, platingline 630, at least oneplating frame 690, at least oneclip electrode 640, and at least one connectingline 692 are formed on thesubstrate 600, e.g. the core layer or the multilayer wiring board. In some embodiments, all of theplating regions 620 are interconnected by asingle plating line 630, in which theplating regions 620 may have at least two sizes and shapes. The shapes of theplating regions 620 are not limited to circular or rectangular, the platingregions 620 can be triangle, polygons, or combinations thereof. - Reference is made to
FIG. 12 andFIG. 13 , which are cross-sectional views of some stages of other embodiment of fabricating the circuit board of the disclosure, in which the stages ofFIG. 12 andFIG. 13 follow after stages ofFIGS. 1A-4B and are followed by stages ofFIGS. 6A-7B . - As shown in
FIG. 12 , in some embodiments, the area of theplating regions 720B on thecore layer 702 of thesubstrate 700 is smaller than the area of theplating regions 720A. The method further includes forming apatterned mask 770 on thesubstrate 700 to expose theplating regions 720B that have a smaller area while theplating regions 720A that has a larger area is covered by the patternedmask 770. In some embodiments, theplating regions plating frame 790 by theplating line 730. - Then, an etching process is performed to recess the
plating regions 720B. The recessedplating regions 720B still cover theunderlying core layer 702. That is, each of the recessedplating regions 720B has acenter section 722 exposed by thesolder mask 750 and the patternedmask 770 and aperipheral section 724 covered by thesolder mask 750 and the patternedmask 770, in which the thickness of theperipheral section 724 is thicker than the thickness of thecenter section 722. Each of theplating regions 720 has themetal foil layer 702 and theconductive layer 704, in which theconductive layer 704 is recessed, and themetal foil layer 702 is covered by theconductive layer 704. - As shown in
FIG. 13 , the patternedmask 770 is removed, and an electroplating process is performed to deposit themetal layer 760 on the exposed surface of theplating regions 720. The thickness of themetal layer 760 on theplating regions 720B that have the smaller area has a thickness H2, themetal layer 760 on theplating region 720A that has the larger area has a thickness H1, and the thickness H2 is thicker than the thickness H1. In some embodiments, themetal layer 760 is embedded in theplating regions 720B, and an interface between themetal layer 760 and theplating region 720B is below an interface between thesolder mask 750 and theplating region 720B. - The present disclosure provides a method of fabricating a circuit board, in which the current density during the electroplating can be more uniform by properly arranging the layout of the plating regions, such that the plating thickness can be more uniform. As a result, contacts of the circuit board fabricated by the method can have a uniform thickness.
- Although the present invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
- It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Claims (14)
1. A method of fabricating a circuit board, comprising:
forming a conductive layer on a surface of a substrate;
etching the conductive layer to define a plurality of plating regions and a plurality of plating lines, wherein the plating regions have at least two different sizes, a first group of the plating regions are interconnected by a first plating line of the plating lines, and a second group of the plating regions are interconnected by a second plating line of the plating lines, wherein a ratio of a total area of the first group of the plating regions to a total area of the second group of the plating regions is from about 1 to about 5;
forming a solder mask on the surface of the substrate, wherein the solder mask covers the plating lines and partially exposes the plating regions; and
electroplating at least one metal layer on the exposed plating regions thereby fabricating the circuit board, wherein a topmost surface of the metal layer is below a top surface of the solder mask.
2. The method of claim 1 , wherein each of the plating regions of the first group of the plating regions has an area, and a sum of the areas of the first group of the plating regions is A1, a first plating region of the first group of the plating regions has a largest area A2 among the first group of the plating regions, and a ratio of A1 to A2 is from about 1 to about 5.
3. The method of claim 1 , wherein each of the plating regions of the first group of the plating regions has an area, and a sum of the areas of the first group of the plating regions is A1, a first plating region of the first group of the plating regions has a largest area A2 among the first group of the plating regions, and a ratio of A2 to A1 is from about 1 to about 5.
4. The method of claim 1 , wherein the first group of the plating regions are interconnected by the first plating line in a serial connection manner.
5. The method of claim 1 , further comprising disconnecting the first plating line between adjacent two plating regions of the first group of the plating regions after electroplating the metal layer on the exposed plating regions.
6. The method of claim 1 , further comprising disconnecting the second plating line between adjacent two plating regions of the second group of the plating regions after electroplating the metal layer on the exposed plating regions.
7. The method of claim 1 , further comprising recessing at least one of the plating regions before electroplating the metal layer on the exposed plating regions.
8. The method of claim 1 , wherein etching the conductive layer comprises defining a plating frame, and the first plating line and the second plating line are connected to the plating frame.
9. A method of fabricating a circuit board, comprising:
forming a conductive layer on a surface of a substrate;
etching the conductive layer to define a plurality of plating regions and a plating line, wherein all of the plating regions are interconnected by the plating line;
forming a solder mask on the surface of the substrate, wherein the solder mask covers the plating line and partially exposes the plating regions; and
electroplating at least one metal layer on the exposed plating regions thereby fabricating the circuit board, wherein a topmost surface of the metal layer is below a top surface of the solder mask.
10. The method of claim 9 , wherein all of the plating regions are interconnected by the plating line in a serial connection manner.
11. The method of claim 9 , further comprising disconnecting the plating line between adjacent two plating regions after electroplating the metal layer on the exposed plating regions.
12. The method of claim 9 , further comprising recessing at least one of the plating regions before electroplating the metal layer on the exposed plating regions.
13. The method of claim 9 , wherein etching the conductive layer comprises defining a plating frame, and the plating line is connected to the plating frame.
14-20. (canceled)
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US17/068,905 US11304310B1 (en) | 2020-10-13 | 2020-10-13 | Method of fabricating circuit board |
CN202011115537.4A CN114364146A (en) | 2020-10-13 | 2020-10-19 | Circuit board and method for manufacturing the same |
US17/680,404 US11678439B2 (en) | 2020-10-13 | 2022-02-25 | Circuit board |
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US17/068,905 US11304310B1 (en) | 2020-10-13 | 2020-10-13 | Method of fabricating circuit board |
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US11304310B1 (en) | 2022-04-12 |
US11678439B2 (en) | 2023-06-13 |
CN114364146A (en) | 2022-04-15 |
US20220183162A1 (en) | 2022-06-09 |
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