US20220059156A1 - Method of generating a multi-level signal using selective equalization, method of transmitting data using the same, and transmitter and memory system performing the same - Google Patents

Method of generating a multi-level signal using selective equalization, method of transmitting data using the same, and transmitter and memory system performing the same Download PDF

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Publication number
US20220059156A1
US20220059156A1 US17/321,678 US202117321678A US2022059156A1 US 20220059156 A1 US20220059156 A1 US 20220059156A1 US 202117321678 A US202117321678 A US 202117321678A US 2022059156 A1 US2022059156 A1 US 2022059156A1
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Prior art keywords
voltage level
output data
data signal
signal
transition time
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US17/321,678
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English (en)
Inventor
Junyoung Park
YoungHoon SON
Hyunyoon Cho
Youngdon CHOI
Junghwan Choi
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SON, YOUNGHOON, CHOI, JUNGHWAN, CHOI, YOUNGDON, CHO, HYUNYOON, PARK, JUNYOUNG
Publication of US20220059156A1 publication Critical patent/US20220059156A1/en
Priority to US18/449,066 priority Critical patent/US20230395133A1/en
Abandoned legal-status Critical Current

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    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
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    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
    • H03K5/1534—Transition or edge detectors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/028—Arrangements specific to the transmitter end
    • H04L25/0286—Provision of wave shaping within the driver
    • H04L25/0288—Provision of wave shaping within the driver the shape being matched to the transmission line
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/069—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection by detecting edges or zero crossings
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L2025/0335—Arrangements for removing intersymbol interference characterised by the type of transmission
    • H04L2025/03356—Baseband transmission
    • H04L2025/03363—Multilevel

Definitions

  • Exemplary embodiments of the inventive concept relate generally to semiconductor integrated circuits, and more particularly to methods of generating multi-level signals, methods of transmitting data using the methods of generating multi-level signals, and transmitters and memory systems that perform the methods of transmitting data and the methods of generating multi-level signals, respectively.
  • Semiconductor memory devices can generally be divided into two categories depending upon whether or not they retain stored data when disconnected from a power supply. These categories include volatile memory devices, which lose stored data when disconnected from power, and nonvolatile memory devices, which retain stored data when disconnected from power. Volatile memory devices may perform read and write operations at a high speed, while contents stored therein may be lost at power-off. Nonvolatile memory devices may retain contents stored therein even at power-off, which means they may be used to store data that must be retained regardless of whether they are powered.
  • a method of generating a multi-level signal having one of three or more voltage levels that are different from one another input data including two or more bits is received.
  • a drive strength of at least one of two or more driving paths is changed based on the two or more bits such that a first transition time, during which an output data signal is transitioned from a first voltage level to a second voltage level, is changed.
  • the output data signal that is the multi-level signal is generated such that the first transition time of the output data signal is changed and a second transition time, during which the output data signal is transitioned from the first voltage level to a third voltage level different from the second voltage level, is maintained.
  • a first output data signal that is the multi-level signal is generated based on first input data.
  • a second output data signal that is the multi-level signal is generated based on second input data.
  • the first output data signal and the second output data signal are transmitted through a first channel and a second channel, respectively, that are different from each other.
  • a drive strength of at least one of two or more driving paths is changed based on the two or more bits included in the first input data such that a first transition time, during which the first output data signal is transitioned from a first voltage level to a second voltage level, is changed.
  • the first output data signal is generated such that the first transition time of the first output data signal is changed and a second transition time, during which the first output data signal is transitioned from the first voltage level to a third voltage level different from the second voltage level, is maintained.
  • a method of generating a multi-level signal having one of a first voltage level, a second voltage level, a third voltage level, and a fourth voltage level that are different from one another input data including a first bit and a second bit that are different from each other is received.
  • the input data is divided into the first and second bits. It is determined, based on the first and second bits, whether a first edge in which an output data signal is transitioned from the first voltage level to the second voltage level is detected. When the first edge is detected, at least one of a first pre-emphasis control signal and a second pre-emphasis control signal is activated.
  • the first pre-emphasis control signal is applied to a first driving path that operates based on the first bit
  • the second pre-emphasis control signal is applied to a second driving path that operates based on the second bit.
  • a drive strength of at least one of the first and second driving paths increases based on at least activated one of the first and second pre-emphasis control signals such that a first transition time, during which the output data signal is transitioned from the first voltage level to the second voltage level, decreases.
  • the output data signal that is the multi-level signal is generated based on the first and second driving paths such that the first transition time of the output data signal is changed and a second transition time, during which the output data signal is transitioned from the first voltage level to the third voltage level, is maintained.
  • a transmitter configured to generate a multi-level signal having one of three or more voltage levels that are different from one another includes a multiplexer, an edge detection logic circuit, and two or more driving paths.
  • the multiplexer receives input data including two or more bits, and divides the input data into the two or more bits.
  • the edge detection logic circuit detects a first edge based on the two or more bits, and activates at least one of two or more pre-emphasis control signals when the first edge is detected.
  • the first edge is an edge in which an output data signal is transitioned from a first voltage level to a second voltage level.
  • the two or more driving paths generate the output data signal that is the multi-level signal based on the two or more bits and the two or more pre-emphasis control signals.
  • the output data signal is generated by changing a drive strength of at least one of the two or more driving paths such that a first transition time, during which the output data signal is transitioned from the first voltage level to the second voltage level, is changed.
  • a second transition time during which the output data signal is transitioned from the first voltage level to a third voltage level different from the second voltage level, is maintained.
  • the memory controller includes a first transmitter and a second transmitter.
  • the first transmitter generates a first output data signal that is the multi-level signal based on first input data.
  • the second transmitter generates a second output data signal that is the multi-level signal based on second input data.
  • the memory device includes a first receiver and a second receiver.
  • the first receiver receives the first output data signal.
  • the second receiver receives the second output data signal.
  • the first channel connects the first transmitter with the first receiver, and transmits the first output data signal.
  • the second channel connects the second transmitter with the second receiver, and transmits the second output data signal.
  • the first transmitter includes a multiplexer, an edge detection logic circuit, and two or more driving paths.
  • the multiplexer receives the first input data including two or more bits, and divides the first input data into the two or more bits.
  • the edge detection logic circuit detects a first edge based on the two or more bits, and activates at least one of two or more pre-emphasis control signals when the first edge is detected.
  • the first edge is an edge in which the first output data signal is transitioned from a first voltage level to a second voltage level.
  • the two or more driving paths generate the first output data signal based on the two or more bits and the two or more pre-emphasis control signals.
  • the first output data signal is generated by changing a drive strength of at least one of the two or more driving paths such that a first transition time, during which the first output data signal is transitioned from the first voltage level to the second voltage level, is changed.
  • the memory device includes a first transmitter and a second transmitter.
  • the first transmitter generates a first output data signal that is the multi-level signal based on first input data.
  • the second transmitter generates a second output data signal that is the multi-level signal based on second input data.
  • the memory controller includes a first receiver and a second receiver.
  • the first receiver receives the first output data signal.
  • the second receiver receives the second output data signal.
  • the first channel connects the first transmitter with the first receiver, and transmits the first output data signal.
  • the second channel connects the second transmitter with the second receiver, and transmits the second output data signal.
  • the first transmitter includes a multiplexer, an edge detection logic circuit, and two or more driving paths.
  • the multiplexer receives the first input data including two or more bits, and divides the first input data into the two or more bits.
  • the edge detection logic circuit detects a first edge based on the two or more bits, and activates at least one of two or more pre-emphasis control signals when the first edge is detected.
  • the first edge is an edge in which the first output data signal is transitioned from a first voltage level to a second voltage level.
  • the two or more driving paths generate the first output data signal based on the two or more bits and the two or more pre-emphasis control signals.
  • the first output data signal is generated by changing a drive strength of at least one of the two or more driving paths such that a first transition time, during which the first output data signal is transitioned from the first voltage level to the second voltage level, is changed.
  • a transmitter configured to generate a multi-level signal having one of three or more voltage levels that are different from one another includes a multiplexer, an edge detection logic circuit, a first driving path, and a second driving path.
  • the multiplexer is configured to divide input data into two or more bits.
  • the edge detection logic circuit is configured to detect a first edge based on the two or more bits, and to activate at least one of a first pre-emphasis control signal and a second pre-emphasis control signal when the first edge is detected.
  • the first edge is an edge in which an output data signal is transitioned from a first voltage level to a second voltage level.
  • the first driving path includes a first pre-emphasis driver circuit configured to generate a first current in response to the first pre-emphasis control signal, and a first data buffer configured to receive one of the two or more bits.
  • the second driving path includes a second pre-emphasis driver circuit configured to generate a second current in response to the second pre-emphasis control signal, and a second data buffer configured to receive one of the two or more bits.
  • the first driving path and the second driving path include driver circuits configured to generate driving currents, and the second driving path includes more driver circuits than the first driving path.
  • the first and second driving paths generate the output data signal that is the multi-level signal based on the driving currents generated by the driver circuits and the first and second currents generated by the first and second pre-emphasis driver circuits.
  • the output data signal is generated by changing a drive strength of at least one of the first and second driving paths such that a first transition time, during which the output data signal is transitioned from the first voltage level to the second voltage level, is changed.
  • a second transition time during which the output data signal is transitioned from the first voltage level to a third voltage level different from the second voltage level, is maintained.
  • FIG. 1 is a flowchart illustrating a method of generating a multi-level signal according to an exemplary embodiment of the inventive concept.
  • FIG. 2 is a flowchart illustrating an example of changing a drive strength of at least one of two or more driving paths in FIG. 1 according to an exemplary embodiment of the inventive concept.
  • FIG. 3 is a block diagram illustrating a memory system according to an exemplary embodiment of the inventive concept.
  • FIGS. 4A and 4B are block diagrams illustrating a memory system according to an exemplary embodiment of the inventive concept.
  • FIG. 5 is a block diagram illustrating a memory controller included in a memory system according to an exemplary embodiment of the inventive concept.
  • FIG. 6 is a block diagram illustrating a memory device included in a memory system according to an exemplary embodiment of the inventive concept.
  • FIGS. 7A, 7B, and 7C are diagrams for describing a data signal generated by a method of generating a multi-level signal according to an exemplary embodiment of the inventive concept.
  • FIG. 8 is a block diagram illustrating a transmitter according to an exemplary embodiment of the inventive concept.
  • FIG. 9 is a block diagram illustrating an edge detection logic included in the transmitter of FIG. 8 according to an exemplary embodiment of the inventive concept.
  • FIGS. 10A and 10B are block diagrams illustrating an edge detection circuit included in the edge detection logic of FIG. 9 according to exemplary embodiments of the inventive concept.
  • FIGS. 11A, 11B, 11C, 11D, 11E, and 12 are diagrams for describing operations performed by a method of generating a multi-level signal and a transmitter according to an exemplary embodiment of the inventive concept.
  • FIG. 13 is a flowchart illustrating an example of changing a drive strength of at least one of two or more driving paths in FIG. 1 according to an exemplary embodiment of the inventive concept.
  • FIG. 14 is a diagram for describing a data signal generated by a method of generating a multi-level signal according to an exemplary embodiment of the inventive concept.
  • FIG. 15 is a block diagram illustrating a transmitter according to an exemplary embodiment of the inventive concept.
  • FIGS. 16 and 17 are flowcharts illustrating a method of transmitting data according to exemplary embodiments of the inventive concept.
  • FIGS. 18A and 18B are block diagrams illustrating a memory system according to an exemplary embodiment of the inventive concept.
  • FIG. 19 is a block diagram illustrating a computing system according to an exemplary embodiment of the inventive concept.
  • FIG. 20 is a block diagram illustrating a communication system according to an exemplary embodiment of the inventive concept.
  • Exemplary embodiments of the inventive concept provide a method of generating a multi-level signal capable of having improved or enhanced signal characteristics using selective equalization while a signal is generated based on multi-level signaling.
  • Exemplary embodiments of the inventive concept also provide a method of transmitting data using the method of generating the multi-level signal.
  • Exemplary embodiments of the inventive concept further provide a transmitter and a memory system that perform the method of transmitting the data and the method of generating the multi-level signal, respectively.
  • FIG. 1 is a flowchart illustrating a method of generating a multi-level signal according to an exemplary embodiment of the inventive concept.
  • a method of generating a multi-level signal is performed to transmit or issue a multi-level signal that has one of three or more different voltage levels during one unit interval (UI), and is performed by a transmitter that generates or transmits the multi-level signal.
  • the transmitter may be included in various communication systems and/or signal transmission systems, and may be included in, for example, a memory system. Configurations of the transmitter, the memory system, and the multi-level signal will be described in detail later.
  • input data including two or more bits is received (operation S 100 ).
  • the input data may be multi-bit data for generating the multi-level signal.
  • a drive strength of at least one of two or more driving paths is changed based on the two or more bits included in the input data (operation S 200 ).
  • the two or more driving paths may be included in the transmitter, and each of the two or more driving paths may operate based on a respective one of the two or more bits.
  • the drive strength of the at least one of the two or more driving paths may be changed such that a first transition time, during which an output data signal is transitioned from a first voltage level to a second voltage level, is changed (e.g., such that a first slope, at which the output data signal is transitioned from the first voltage level to the second voltage level, is changed).
  • the first transition time may represent a time interval for transitioning the output data signal from the first voltage level to the second voltage level.
  • the operation of changing the drive strength may be referred to as an equalizing operation or an equalization. Operation S 200 will be described with reference to FIGS. 2 and 13 .
  • the output data signal that is the multi-level signal is generated based on the input data and operation S 200 (operation S 300 ).
  • the first transition time for transitioning from the first voltage level to the second voltage level may be changed (e.g., the first slope may be changed), and a second transition time, during which the output data signal is transitioned from the first voltage level to a third voltage level (different from the second voltage level), may be maintained or unchanged (e.g., a second slope, at which the output data signal is transitioned from the first voltage level to the third voltage level, may be maintained).
  • the second transition time may represent a time interval for transitioning the output data signal from the first voltage level to the third voltage level.
  • the equalizing operation may be performed when the output data signal is transitioned from the first voltage level to the second voltage level, and the equalizing operation may not be performed when the output data signal is transitioned from the first voltage level to the third voltage level.
  • the output data signal is generated based on a multi-level signaling scheme.
  • the multi-level signaling scheme may be used as a means of compressing bandwidth to transmit data at a given bit rate.
  • two single symbols usually two voltage levels, may be used to represent ‘1’ and ‘0,’ and thus the symbol rate may be equal to the bit rate.
  • the principle of the multi-level signaling scheme may be to use a larger alphabet of m symbols to represent data, so that each symbol may represent more than one bit of data.
  • the number of symbols that needs to be transmitted may be less than the number of bits (e.g., the symbol rate may be less than the bit rate), and thus the bandwidth may be compressed.
  • the alphabet of symbols may be constructed from a number of different voltage levels. For example, in a four-level scheme, groups of two data bits may be mapped to one of four symbols. Only one symbol need be transmitted for each pair of data bits, so the symbol rate may be half of the bit rate.
  • the multi-level signaling scheme may be used to increase a data transmission (or transfer) rate without increasing the frequency of data transmission and/or a transmission power of the communicated data.
  • An example of one type of the multi-level signaling scheme may be a pulse-amplitude modulation (PAM) scheme, where a unique symbol of a multi-level signal may represent a plurality of bits of data.
  • PAM pulse-amplitude modulation
  • the number of possible pulse amplitudes in a digital PAM scheme may be some power of two.
  • the inventive concept is not limited thereto, and exemplary embodiments of the inventive concept may be applied or employed to a K-level PAM (e.g., PAM(K)) having K possible pulse amplitudes, where K is a natural number greater than or equal to three.
  • K is a natural number greater than or equal to three.
  • a selective or adaptive equalization scheme may be implemented.
  • the selective equalization scheme existing or conventional driving paths may be used as is, and the equalizing operation may be performed only when a specific level transition occurs on the output data signal.
  • the equalizing operation may be performed only on some level transitions that are capable of occurring on the multi-level signal. Accordingly, as compared to an example where the equalizing operation is performed on all level transitions, power consumption may be reduced and the signal characteristic may be efficiently improved or enhanced.
  • FIG. 2 is a flowchart illustrating an example of changing a drive strength of at least one of two or more driving paths in FIG. 1 according to an exemplary embodiment of the inventive concept.
  • the input data may be divided into the two or more bits (operation S 210 ). It may be determined based on the two or more bits whether a first edge in which the output data signal is transitioned from the first voltage level to the second voltage level is detected (operation S 220 ).
  • the first voltage level may correspond to a lowest voltage level and the second voltage level may correspond to a highest voltage level.
  • the inventive concept is not limited thereto.
  • the first voltage level may not correspond to the lowest voltage level, or the second voltage level may not correspond to the highest voltage level.
  • At least one of two or more pre-emphasis control signals may be activated (operation S 230 ), and the drive strength of the at least one of the two or more driving paths may increase based on the activated pre-emphasis control signal such that the first transition time of the output data signal decreases (e.g., such that the first slope of the output data signal increases) (operation S 240 ).
  • the equalizing operation may be performed on the first edge.
  • each of the two or more driving paths may include a respective one of two or more pre-emphasis driver circuits, and each of the two or more pre-emphasis driver circuits may operate based on a respective one of the two or more pre-emphasis control signals.
  • a specific pre-emphasis control signal is activated, a corresponding pre-emphasis driver circuit may be enabled, and the drive strength may increase by the enabled pre-emphasis driver circuit.
  • the amount of increment of the drive strength (e.g., the amount of decrement of the first transition time and/or the amount of increment of the first slope) may be determined based on the number and type of the activated pre-emphasis control signals.
  • operation S 220 When the first edge is not detected (operation S 220 : NO), for example, when a second edge in which the output data signal is transitioned from the first voltage level to the third voltage level is detected, all of the two or more pre-emphasis control signals may be deactivated, and the drive strength of all of the two or more driving paths may be maintained such that the second transition time of the output data signal is maintained (e.g., such that the second slope of the output data signal is maintained) (operation S 250 ). In other words, the equalizing operation may not be performed on the second edge.
  • the first transition time when the equalizing operation is performed on the first edge, the first transition time may decrease and the first slope may increase as compared to when the equalizing operation is not performed on the first edge.
  • the second transition time and the second slope may be maintained.
  • the first transition time and the second transition time may become different from each other.
  • FIG. 2 illustrates an example where the selective equalization scheme is performed only on a single edge (e.g., on the first edge), the inventive concept is not limited thereto, and the selective equalization scheme may be performed on two or more edges as will be described with reference to FIG. 13 .
  • FIG. 3 is a block diagram illustrating a memory system according to an exemplary embodiment of the inventive concept.
  • a memory system 10 includes a memory controller 20 and a memory device 40 .
  • the memory system 10 may further include a plurality of signal lines 30 that electrically connect the memory controller 20 with the memory device 40 .
  • the memory device 40 is controlled by the memory controller 20 .
  • the memory controller 20 may store (e.g., write or program) data into the memory device 40 , or may retrieve (e.g., read or sense) data from the memory device 40 .
  • the plurality of signal lines 30 may include control lines, command lines, address lines, data input/output (I/O) lines, and power lines.
  • the memory controller 20 may transmit a command CMD, an address ADDR, and a control signal CTRL to the memory device 40 via the command lines, the address lines, and the control lines, respectively, may exchange a data signal MLDAT with the memory device 40 via the data I/O lines, and may transmit a power supply voltage PWR to the memory device 40 via the power lines.
  • the data signal MLDAT may be the multi-level signal that is generated and transmitted according to an exemplary embodiment of the inventive concept.
  • the plurality of signal lines 30 may further include data strobe signal (DQS) lines for transmitting a DQS signal.
  • DQS data strobe signal
  • the signal lines 30 may be referred to as a channel
  • the term “channel” as used herein may represent signal lines that include the data I/O lines for transmitting the data signal MLDAT.
  • the inventive concept is not limited thereto, and the channel may further include the command lines for transmitting the command CMD and/or the address lines for transmitting the address ADDR.
  • FIGS. 4A and 4B are block diagrams illustrating a memory system according to an exemplary embodiment of the inventive concept.
  • a memory system 11 includes a memory controller 21 , a memory device 41 , and a plurality of channels 31 a , 31 b , and 31 c .
  • the number of the channels 31 a , 31 b , and 31 c may be N, where N is a natural number greater than or equal to two.
  • the memory controller 21 may include a plurality of transmitters 25 a , 25 b , and 25 c , a plurality of receivers 27 a , 27 b , and 27 c , and a plurality of data I/O pads 29 a , 29 b , and 29 c .
  • the memory device 41 may include a plurality of transmitters 45 a , 45 b , and 45 c , a plurality of receivers 47 a , 47 b , and 47 c , and a plurality of data I/O pads 49 a , 49 b , and 49 c.
  • Each of the plurality of transmitters 25 a , 25 b , 25 c , 45 a , 45 b , and 45 c may generate a multi-level signal, may perform the method of generating multi-level signal according to exemplary embodiments of the inventive concept described with reference to FIG. 1 , and may be a transmitter according to exemplary embodiments of the inventive concept which will be described with reference to FIGS. 8 and 15 .
  • Each of the plurality of receivers 27 a , 27 b , 27 c , 47 a , 47 b , and 47 c may receive the multi-level signal.
  • the plurality of transmitters 25 a , 25 b , 25 c , 45 a , 45 b , and 45 c and the plurality of receivers 27 a , 27 b , 27 c , 47 a , 47 b , and 47 c may perform a method of transmitting data according to exemplary embodiments of the inventive concept, which will be described with reference to FIGS. 16 and 17 , through the plurality of channels 31 a , 31 b , and 31 c.
  • Each of the plurality of data I/O pads 29 a , 29 b , 29 c , 49 a , 49 b , and 49 c may be connected to a respective one of the plurality of transmitters 25 a , 25 b , 25 c , 45 a , 45 b , and 45 c and a respective one of the plurality of receivers 27 a , 27 b , 27 c , 47 a , 47 b , and 47 c.
  • the plurality of channels 31 a , 31 b , and 31 c may connect the memory controller 21 with the memory device 41 .
  • Each of the plurality of channels 31 a , 31 b , and 31 c may be connected to a respective one of the plurality of transmitters 25 a , 25 b , and 25 c and a respective one of the plurality of receivers 27 a , 27 b , and 27 c through a respective one of the plurality of data I/O pads 29 a , 29 b , and 29 c .
  • each of the plurality of channels 31 a , 31 b , and 31 c may be connected to a respective one of the plurality of transmitters 45 a , 45 b , and 45 c and a respective one of the plurality of receivers 47 a , 47 b , and 47 c through a respective one of the plurality of data I/O pads 49 a , 49 b , and 49 c .
  • the multi-level signal may be transmitted through each of the plurality of channels 31 a , 31 b , and 31 c.
  • FIG. 4A illustrates an operation of transferring data from the memory controller 21 to the memory device 41 .
  • the transmitter 25 a may generate an output data signal DS 11 , which is the multi-level signal, based on input data DAT 11
  • the output data signal DS 11 may be transmitted from the memory controller 21 to the memory device 41 through the channel 31 a
  • the receiver 47 a may receive the output data signal DS 11 to obtain data ODAT 11 corresponding to the input data DAT 11 .
  • the transmitter 25 b may generate an output data signal DS 21 , which is the multi-level signal, based on input data DAT 21
  • the output data signal DS 21 may be transmitted to the memory device 41 through the channel 31 b
  • the receiver 47 b may receive the output data signal DS 21 to obtain data ODAT 21 corresponding to the input data DAT 21
  • the transmitter 25 c may generate an output data signal DSN 1 , which is the multi-level signal, based on input data DATN 1
  • the output data signal DSN 1 may be transmitted to the memory device 41 through the channel 31 c
  • the receiver 47 c may receive the output data signal DSN 1 to obtain data ODATN 1 corresponding to the input data DATN 1 .
  • the input data DAT 11 , DAT 21 , and DATN 1 may be write data to be written into the memory device 41 .
  • FIG. 4B illustrates an operation of transferring data from the memory device 41 to the memory controller 21 .
  • the transmitter 45 a may generate an output data signal DS 12 , which is the multi-level signal, based on input data DAT 12
  • the output data signal DS 12 may be transmitted from the memory device 41 to the memory controller 21 through the channel 31 a
  • the receiver 27 a may receive the output data signal DS 12 to obtain data ODAT 12 corresponding to the input data DAT 12 .
  • the transmitter 45 b may generate an output data signal DS 22 , which is the multi-level signal, based on input data DAT 22
  • the output data signal DS 22 may be transmitted to the memory controller 21 through the channel 31 b
  • the receiver 27 b may receive the output data signal DS 22 to obtain data ODAT 22 corresponding to the input data DAT 22
  • the transmitter 45 c may generate an output data signal DSN 2 , which is the multi-level signal, based on input data DATN 2
  • the output data signal DSN 2 may be transmitted to the memory controller 21 through the channel 31 c
  • the receiver 27 c may receive the output data signal DSN 2 to obtain data ODATN 2 corresponding to the input data DATN 2 .
  • the input data DAT 12 , DAT 22 , and DATN 2 may be read data retrieved from the memory device 41 .
  • FIG. 5 is a block diagram illustrating a memory controller included in a memory system according to an exemplary embodiment of the inventive concept.
  • a memory controller 100 may include at least one processor 110 , a buffer memory 120 , a host interface 130 , an error correction code (ECC) block 140 , and a memory interface 150 .
  • processor 110 may include at least one processor 110 , a buffer memory 120 , a host interface 130 , an error correction code (ECC) block 140 , and a memory interface 150 .
  • ECC error correction code
  • the processor 110 may control an operation of the memory controller 100 in response to a command and/or request received via the host interface 130 from an external host.
  • the processor 110 may control respective components by employing firmware for operating a memory device (e.g., the memory device 40 in FIG. 3 ).
  • the buffer memory 120 may store instructions and data executed and processed by the processor 110 .
  • the buffer memory 120 may be implemented with a volatile memory device such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a cache memory, or the like.
  • DRAM dynamic random access memory
  • SRAM static random access memory
  • cache memory or the like.
  • the host interface 130 may provide physical connections between the external host and the memory controller 100 .
  • the host interface 130 may provide an interface corresponding to a bus format of the external host for communication between the external host and the memory controller 100 .
  • the bus format of the external host may be a small computer system interface (SCSI) or a serial attached SCSI (SAS) interface.
  • the bus format of the external host may be a universal serial bus (USB), a peripheral component interconnect (PCI) express (PCIe), an advanced technology attachment (ATA), a parallel ATA (PATA), a serial ATA (SATA), a nonvolatile memory (NVMe), etc., format.
  • the ECC block 140 for error correction may perform coded modulation using a Bose-Chaudhuri-Hocquenghem (BCH) code, a low-density parity-check (LDPC) code, a turbo code, a Reed-Solomon code, a convolution code, a recursive systematic convolutional code (RSC), a trellis-coded modulation (TCM), a block coded modulation (BCM), etc., or may perform ECC encoding and ECC decoding using the above-described codes or other error correction codes.
  • BCH Bose-Chaudhuri-Hocquenghem
  • LDPC low-density parity-check
  • turbo code a Reed-Solomon code
  • a convolution code a recursive systematic convolutional code (RSC), a trellis-coded modulation (TCM), a block coded modulation (BCM), etc.
  • RSC recursive systematic convolutional
  • the memory interface 150 may exchange data with the memory device.
  • the memory interface 150 may transmit a command and an address to the memory device, and may transmit data to the memory device or receive data read from the memory device.
  • a transmitter e.g., the transmitter 25 a in FIG. 4A
  • a receiver e.g., the receiver 27 a in FIG. 4A
  • receives the multi-level signal may be included in the memory interface 150 .
  • FIG. 6 is a block diagram illustrating a memory device included in a memory system according to an exemplary embodiment of the inventive concept.
  • a memory device 200 includes a control logic 210 , a refresh control circuit 215 , an address register 220 , a bank control logic 230 , a row address multiplexer 240 , a column address latch 250 , a row decoder, a column decoder, a memory cell array, a sense amplifier unit, an input/output (I/O) gating circuit 290 , a data I/O buffer 295 , an on-die termination (ODT) circuit 297 , and a data I/O pad 299 .
  • the memory device 200 may be, e.g., a volatile memory device.
  • the memory device 200 may be one of various volatile memory devices such as a dynamic random access memory (DRAM).
  • DRAM dynamic random access memory
  • the memory cell array may include a plurality of memory cells.
  • the memory cell array may include a plurality of bank arrays, e.g., first through fourth bank arrays 280 a , 280 b , 280 c , and 280 d .
  • the row decoder may include a plurality of bank row decoders, e.g., first through fourth bank row decoders 260 a , 260 b , 260 c , and 260 d connected to the first through fourth bank arrays 280 a , 280 b , 280 c , and 280 d , respectively.
  • the column decoder may include a plurality of bank column decoders, e.g., first through fourth bank column decoders 270 a , 270 b , 270 c , and 270 d connected to the first through fourth bank arrays 280 a , 280 b , 280 c , and 280 d , respectively.
  • the sense amplifier unit may include a plurality of bank sense amplifiers, e.g., first through fourth bank sense amplifiers 285 a , 285 b , 285 c , and 285 d connected to the first through fourth bank arrays 280 a , 280 b , 280 c , and 280 d , respectively.
  • the first through fourth bank arrays 280 a ⁇ 280 d , the first through fourth bank row decoders 260 a ⁇ 260 d , the first through fourth bank column decoders 270 a ⁇ 270 d , and the first through fourth bank sense amplifiers 285 a ⁇ 285 d may form first through fourth banks, respectively.
  • the first bank array 280 a , the first bank row decoder 260 a , the first bank column decoder 270 a , and the first bank sense amplifier 285 a may form the first bank;
  • the second bank array 280 b , the second bank row decoder 260 b , the second bank column decoder 270 b , and the second bank sense amplifier 285 b may form the second bank;
  • the third bank array 280 c , the third bank row decoder 260 c , the third bank column decoder 270 c , and the third bank sense amplifier 285 c may form the third bank;
  • the fourth bank array 280 d , the fourth bank row decoder 260 d , the fourth bank column decoder 270 d , and the fourth bank sense amplifier 285 d may form the fourth bank.
  • the address register 220 may receive the address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from a memory controller (e.g., the memory controller 20 in FIG. 3 ).
  • the address register 220 may provide the received bank address BANK_ADDR to the bank control logic 230 , may provide the received row address ROW_ADDR to the row address multiplexer 240 , and may provide the received column address COL_ADDR to the column address latch 250 .
  • the bank control logic 230 may generate bank control signals in response to receipt of the bank address BANK_ADDR.
  • One of the first through fourth bank row decoders 260 a ⁇ 260 d corresponding to the received bank address BANK_ADDR may be activated in response to the bank control signals generated by the bank control logic 230
  • one of the first through fourth bank column decoders 270 a ⁇ 270 d corresponding to the received bank address BANK_ADDR may be activated in response to the bank control signals generated by the bank control logic 230 .
  • the refresh control circuit 215 may generate a refresh address REF_ADDR in response to receipt of a refresh command or entrance of any self-refresh mode.
  • the refresh control circuit 215 may include a refresh counter that is configured to sequentially change the refresh address REF_ADDR from a first address of the memory cell array to a last address of the memory cell array.
  • the refresh control circuit 215 may receive control signals from the control logic 210 .
  • the row address multiplexer 240 may receive the row address ROW_ADDR from the address register 220 , and may receive the refresh address REF_ADDR from the refresh control circuit 215 .
  • the row address multiplexer 240 may selectively output the row address ROW_ADDR or the refresh address REF_ADDR.
  • a row address output from the row address multiplexer 240 (e.g., the row address ROW_ADDR or the refresh address REF_ADDR) may be applied to the first through fourth bank row decoders 260 a ⁇ 260 d.
  • the activated one of the first through fourth bank row decoders 260 a ⁇ 260 d may decode the row address output from the row address multiplexer 240 , and may activate a wordline corresponding to the row address.
  • the activated bank row decoder may apply a wordline driving voltage to the wordline corresponding to the row address.
  • the column address latch 250 may receive the column address COL_ADDR from the address register 220 , and may temporarily store the received column address COL_ADDR. The column address latch 250 may apply the temporarily stored or received column address COL_ADDR to the first through fourth bank column decoders 270 a ⁇ 270 d .
  • the activated one of the first through fourth bank column decoders 270 a ⁇ 270 d may decode the column address COL_ADDR output from the column address latch 250 , and may control the I/O gating circuit 290 to output data corresponding to the column address COL_ADDR.
  • the I/O gating circuit 290 may include a circuitry for gating I/O data.
  • the I/O gating circuit 290 may include an input data mask logic, read data latches for storing data output from the first through fourth bank arrays 280 a ⁇ 280 d , and write drivers for writing data to the first through fourth bank arrays 280 a ⁇ 280 d.
  • Data DQ to be read from one of the first through fourth bank arrays 280 a ⁇ 280 d may be sensed by a sense amplifier coupled to the one bank array, and may be stored in the read data latches.
  • the data DQ stored in the read data latches may be provided to the memory controller via the data I/O buffer 295 and the data I/O pad 299 .
  • Data DQ received via the data I/O pad 299 that are to be written to one of the first through fourth bank arrays 280 a - 280 d may be provided from the memory controller to the data I/O buffer 295 .
  • the data DQ received via the data I/O pad 299 and provided to the data I/O buffer 295 may be written to the one bank array via the write drivers in the I/O gating circuit 290 .
  • a transmitter e.g., the transmitter 45 a in FIG. 4A
  • a receiver e.g., the receiver 47 a in FIG. 4A
  • receives the multi-level signal may be included in the data I/O buffer 295 .
  • the control logic 210 may control an operation of the memory device 200 .
  • the control logic 210 may generate control signals for the memory device 200 to perform a data write operation or a data read operation.
  • the control logic 210 may include a command decoder 211 that decodes the command CMD received from the memory controller and a mode register 212 that sets an operation mode of the memory device 200 .
  • the ODT circuit 297 may be connected to the data I/O pad 299 and the data I/O buffer 295 . When the ODT circuit 297 is enabled, an ODT operation may be performed. The ODT operation may reduce (and/or prevent) a signal from being reflected by using a termination resistor to improve signal integrity.
  • the memory device included in the memory system may be any volatile memory device and/or any nonvolatile memory device, e.g., a flash memory, a phase random access memory (PRAM), a resistive random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), a thyristor random access memory (TRAM), etc.
  • a flash memory e.g., a phase random access memory (PRAM), a resistive random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), a thyristor random access memory (TRAM), etc.
  • PRAM phase random access memory
  • RRAM resistive random access memory
  • NFGM nano floating gate memory
  • PoRAM polymer random access memory
  • MRAM magnetic random access memory
  • FIGS. 7A, 7B, and 7C are diagrams for describing a data signal generated by a method of generating a multi-level signal according to an exemplary embodiment of the inventive concept.
  • FIG. 7A illustrates an ideal eye diagram of a data signal (e.g., a PAM 4 signal) generated based on the 4 -level scheme (e.g., the PAM 4 scheme).
  • FIG. 7B is a simplified diagram illustrating the eye diagram of FIG. 7A .
  • FIG. 7C is a diagram illustrating the selective equalization scheme according to an exemplary embodiment of the inventive concept.
  • an eye diagram may be used to indicate the quality of signals in high-speed transmissions.
  • the eye diagram may represent four symbols of a signal (e.g., ‘00,’‘01,’‘10,’ and ‘11’), and each of the four symbols may be represented by a respective one of different voltage levels (e.g., voltage amplitudes) VL 11 , VL 21 , VL 31 , and VL 41 .
  • the eye diagram may be used to provide a visual indication of the health of the signal integrity, and may indicate noise margins of the data signal.
  • an oscilloscope or other computing device may sample a digital signal according to a sample period SP (e.g., a unit interval or a bit period).
  • the sample period SP may be defined by a clock associated with the transmission of the measured signal.
  • the oscilloscope or other computing device may measure the voltage level of the signal during the sample period SP to form a plurality of traces TRC.
  • Various characteristics associated with the measured signal may be determined by overlaying the plurality of traces TRC.
  • the eye diagram may be used to identify a number of characteristics of a communication signal such as jitter, crosstalk, electromagnetic interference (EMI), signal loss, signal-to-noise ratio (SNR), other characteristics, or combinations thereof.
  • a communication signal such as jitter, crosstalk, electromagnetic interference (EMI), signal loss, signal-to-noise ratio (SNR), other characteristics, or combinations thereof.
  • EMI electromagnetic interference
  • SNR signal-to-noise ratio
  • a width W of an eye in the eye diagram may be used to indicate a timing synchronization of the measured signal or jitter effects of the measured signal.
  • the eye diagram may indicate an eye opening OP, which represents a peak-to-peak voltage difference between various voltage levels VL 11 , VL 21 , VL 31 , and VL 41 .
  • the eye opening OP may be related to a voltage margin for discriminating between different voltage levels VL 11 , VL 21 , VL 31 , and VL 41 of the measured signal.
  • the eye diagram may be used to identify a rise time RT and/or a fall time FT for transitions from a first amplitude to a second amplitude.
  • the rise time RT or the fall time FT may indicate a time for transitioning from one voltage level to another voltage level, may be related to or associated with a rising edge and a falling edge, respectively, and may correspond to the first and second transition times described with reference to FIG. 1 .
  • the slope of the trace TRC during the rise time RT or the fall time FT may indicate the sensitivity of the signal to timing error, among other aspects.
  • the eye diagram may be used to identify an amount of jitter JT in the measured signal.
  • the jitter JT may refer to a timing error that results from a misalignment of rise and fall times.
  • the jitter JT may occur when the rising edge or the falling edge occurs at a time that is different from an ideal time defined by the data clock.
  • the jitter JT may be caused by signal reflections, intersymbol interference, crosstalk, process-voltage-temperature (PVT) variations, random jitter, additive noise, or combinations thereof.
  • PVT process-voltage-temperature
  • FIG. 7B different first, second, third, and fourth voltage levels VL 11 , VL 21 , VL 31 , and VL 41 of the data signal that is the PAM 4 signal are illustrated, and first, second, and third eyes EYE 11 , EYE 21 , and EYE 31 of the data signal are illustrated.
  • the parts illustrated by the thick solid lines represent the size of the eyes EYE 11 , EYE 21 , and EYE 31 .
  • the first voltage level VL 11 may be lower than the second voltage level VL 21
  • the second voltage level VL 21 may be lower than the third voltage level VL 31
  • the third voltage level VL 31 may be lower than the fourth voltage level VL 41
  • the first eye EYE 11 may be positioned between the first and second voltage levels VL 11 and VL 21
  • the second eye EYE 21 may be positioned between the second and third voltage levels VL 21 and VL 31
  • the third eye EYE 31 may be positioned between the third and fourth voltage levels VL 31 and VL 41 .
  • the characteristic of the first eye EYE 11 may be determined by a falling edge (e.g., ‘11’->‘00’) from the fourth voltage level VL 41 to the first voltage level VL 11 , a rising edge (e.g., ‘00’->‘01’) from the first voltage level VL 11 to the second voltage level VL 21 , a rising edge (e.g., ‘00’->‘11’) from the first voltage level VL 11 to the fourth voltage level VL 41 , and a falling edge (e.g., ‘01’->‘00’) from the second voltage level VL 21 to the first voltage level VL 11 .
  • a falling edge e.g., ‘11’->‘00’
  • the characteristic of the second eye EYE 21 may be determined by rising and falling edges (e.g., ‘01’ ⁇ ->‘11’) between the second and fourth voltage levels VL 21 and VL 41 , and rising and falling edges (e.g., ‘00’ ⁇ ->‘10’) between the first and third voltage levels VL 11 and VL 31 .
  • the characteristic of the third eye EYE 31 may be determined by rising and falling edges (e.g., ‘10’ ⁇ ->‘11’) between the third and fourth voltage levels VL 31 and VL 41 , and rising and falling edges (e.g., ‘00’ ⁇ ->‘11’) between the first and fourth voltage levels VL 11 and VL 41 .
  • the equalizing operation When the equalizing operation is performed on all edges (e.g., all level transitions), the equalizing operation may also be performed on edges that do not affect the eye characteristics.
  • the equalizing operation that is not appropriate for the eye characteristics may cause unnecessary power consumption, and may deteriorate or degrade the eye characteristics in some cases.
  • the equalizing operation when the equalizing operation is performed only on some edges (e.g., some level transitions) according to exemplary embodiments of the inventive concept, power consumption may be reduced and the signal characteristic may be efficiently improved or enhanced.
  • FIG. 7C the change in the power consumption and the amount of jitter according to the number of times of equalizing operations is illustrated as a graph.
  • a horizontal axis represents the number of times of equalizing operations are performed (EQL) or the number of level transitions in which the equalizing operation is performed.
  • Vertical axes represent the power consumption (PWR) and the amount of jitter (JT).
  • the power consumption may increase, and the amount of jitter may decrease to improve the jitter characteristics.
  • the target and number of the equalizing operations may be set in consideration of the power consumption and characteristics of channels through which data signals are transmitted, and thus the selective equalization scheme may be implemented for optimal performance.
  • FIG. 8 is a block diagram illustrating a transmitter according to an exemplary embodiment of the inventive concept.
  • a transmitter 500 includes a multiplexer 510 , an edge detection logic 520 , and two or more driving paths 540 and 550 .
  • the transmitter 500 may further include a data 1 / 0 pad 580 .
  • the edge detection logic 520 may be a circuit.
  • the multiplexer 510 receives input data DAT 1 including two or more bits D 0 and D 1 , and divides the input data DAT 1 into the two or more bits D 0 and D 1 .
  • the edge detection logic 520 detects a first edge based on the two or more bits D 0 and D 1 , and activates at least one of two or more pre-emphasis control signals PECS 1 and PECS 2 when the first edge is detected.
  • the first edge represents an edge in which an output data signal DS 1 is transitioned from a first voltage level to a second voltage level.
  • the two or more driving paths 540 and 550 generate the output data signal DS 1 that is a multi-level signal based on the two or more bits D 0 and D 1 and the two or more pre-emphasis control signals PECS 1 and PECS 2 .
  • the data I/O pad 580 may output the output data signal DS 1 .
  • the output data signal DS 1 is generated by changing a drive strength of at least one of the two or more driving paths 540 and 550 such that a first transition time, during which the output data signal DS 1 is transitioned from the first voltage level to the second voltage level, is changed.
  • the transmitter 500 may perform the method of generating the multi-level signal according to an exemplary embodiment of the inventive concept.
  • the edge detection logic 520 may be set to detect the first edge among a plurality of edges included in the output data signal DS 1 based on a plurality of edge detection enable signals EDEN.
  • the first and second voltage levels may be determined based on the plurality of edge detection enable signals EDEN.
  • the plurality of edge detection enable signals EDEN may be preset (or set in advance), and the first and second voltage levels may be predetermined (or determined in advance) based on a characteristic of a channel transmitting the output data signal DS 1 .
  • the plurality of edge detection enable signals EDEN may be set in real time (or during runtime), and the first and second voltage levels may be determined in real time based on characteristic data that represents the characteristic of the channel transmitting the output data signal DS 1 and is received from outside.
  • characteristic data may be provided from an eye monitor circuit included in a receiver that receives the output data signal DS 1 .
  • the input data DAT 1 may include a first bit D 0 and a second bit D 1 that are different from each other, and the multiplexer 510 may divide the input data DAT 1 into the first bit D 0 and the second bit D 1 based on a four-phase clock signal CK_ 4 P.
  • the two or more driving paths 540 and 550 may include a first driving path 540 that operates based on the first bit D 0 and a first pre-emphasis control signal PECS 1 , and a second driving path 550 that operates based on the second bit D 1 and a second pre-emphasis control signal PECS 2 .
  • the output data signal DS 1 may correspond to the data signal illustrated in FIGS. 7A and 7B , and may have one of the first, second, third and fourth voltage levels VL 11 , VL 21 , VL 31 , and VL 41 , that are different from each other, during one unit interval.
  • the first bit D 0 may be a least significant bit (LSB) of the input data DAT 1
  • the second bit D 1 may be a most significant bit (MSB) of the input data DAT 1
  • the first driving path 540 may be a data path for the LSB
  • the second driving path 550 may be a data path for the MSB.
  • the first driving path 540 may include a first data buffer 541 , a first driver circuit 543 , and a first pre-emphasis driver circuit 545 .
  • the first data buffer 541 may temporarily store the first bit D 0 .
  • the first driver circuit 543 may generate a first driving current I 1 for generating the output data signal DS 1 based on an output of the first data buffer 541 .
  • the first pre-emphasis driver circuit 545 may generate a first current IP 1 for increasing a first drive strength of the first driving path 540 based on the first pre-emphasis control signal PECS 1 .
  • the second driving path 550 may include a second data buffer 551 , a second driver circuit 553 , a third driver circuit 555 , and a second pre-emphasis driver circuit 557 .
  • the second data buffer 551 may temporarily store the second bit D 1 .
  • the second driver circuit 553 may generate a second driving current 12 for generating the output data signal DS 1 based on an output of the second data buffer 551 .
  • the third driver circuit 555 may generate a third driving current 13 for generating the output data signal DS 1 based on the output of the second data buffer 551 .
  • the second pre-emphasis driver circuit 557 may generate a second current IP 2 for increasing a second drive strength of the second driving path 550 based on the second pre-emphasis control signal PECS 2 .
  • the second and third driver circuits 553 and 555 may be substantially simultaneously enabled or disabled based on the output of the second data buffer 551 .
  • the second driving path 550 that is the data path for the MSB should have a greater driving capability than the first driving path 540 that is the data path for the LSB.
  • the second driving path 550 may include more driver circuits than the first driving path 540 , e.g., two driver circuits 553 and 555 that are enabled/disabled at substantially the same time.
  • the first and second driving paths 540 and 550 generate the output data signal DS 1 that is the multi-level signal based on the driving currents (e.g., I 1 , I 2 , and 13 ) generated by the driver circuits (e.g., 543 , 553 , and 555 ) and the first and second currents (e.g., IP 1 and IP 2 ) generated by the first and second pre-emphasis driver circuits (e.g., 545 and 557 ).
  • the driving currents e.g., I 1 , I 2 , and 13
  • the driver circuits e.g., 543 , 553 , and 555
  • the first and second currents e.g., IP 1 and IP 2
  • the drive strength of at least one of the first and second driving paths 540 and 550 is changed by activating the first pre-emphasis control signal PECS 1 applied to the first driving path 540 to increase a first drive strength of the first driving path 540 , or by activating the second pre-emphasis control signal PECS 2 applied to the second driving path 550 to increase a second drive strength of the second driving path 550 .
  • Pre-emphasis is a type of equalizing operation. Pre-emphasizing a signal may include boosting the high-frequency components of the signal to compensate for attenuation incurred in the channel. Generally, “pre-emphasis” refers to increasing a signal amplitude after a transition of the signal. The pre-emphasis in this context may be accomplished by amplifying the high frequency components of the signal (e.g., increasing the energy content of the high frequency components to compensate for degradation of those components due to channel loss), which increases the overall amplitude of the signal. In addition, a drive strength of a signal indicates a voltage or current of the signal, and for example, the drive strength of the signal may increase when the pre-emphasis is performed. Although the equalizing operation according to an exemplary embodiment of the inventive concept is described based on pre-emphasis, the equalizing operation is not limited thereto.
  • At least one pre-driver circuit may be disposed between the data buffers 541 and 551 and the driver circuits 543 , 553 , and 555 , and/or between the edge detection logic 520 and the pre-emphasis driver circuits 545 and 557 .
  • the pre-driver circuit may condition or modify the received signal before passing it to the next stage (e.g., the pre-driver may modify the received signal to improve the characteristics or quality of the communication signal).
  • the pre-driver circuit may additionally or alternatively act as a selector.
  • FIG. 8 illustrates that a configuration 530 for increasing the drive strength includes one pre-emphasis driver circuit 545 included in the first driving path 540 and one pre-emphasis driver circuit 557 included in the second driving path 550
  • the inventive concept is not limited thereto, and the number of pre-emphasis driver circuits may be changed.
  • the number of the driver circuits 543 , 553 , and 555 may also be changed, and the number of the driver circuits 543 , 553 , and 555 and the number of the pre-emphasis driver circuits 545 and 557 may be equal to or different from each other.
  • FIG. 9 is a block diagram illustrating an edge detection logic included in the transmitter of FIG. 8 according to an exemplary embodiment of the inventive concept.
  • the edge detection logic 520 may include a plurality of edge detection circuits 521 , 522 , 523 , 524 , 525 , 526 , 531 , 532 , 533 , 534 , 535 , and 536 .
  • the edge detection circuits 521 , 522 , 523 , 524 , 525 , and 526 may be selectively enabled based on edge detection enable signals EDEN_R 1 , EDEN_R 2 , EDEN_R 3 , EDEN_R 4 , EDEN_R 5 , and EDEN_R 6 , respectively.
  • each of the edge detection circuits 521 , 522 , 523 , 524 , 525 , and 526 may detect a respective rising edge of the output data signal DS 1 based on the first and second bits D 0 and D 1 to activate at least one of the pre-emphasis control signals PECS 1 and PECS 2 .
  • the edge detection circuit 521 may be enabled based on the edge detection enable signal EDEN_R 1 .
  • the edge detection circuit 521 may detect a first rising edge (e.g., ‘00’->‘11’) in which the output data signal DS 1 is transitioned from the first voltage level VL 11 that is the lowest voltage level to the fourth voltage level VL 41 that is the highest voltage level. For example, when the first rising edge is detected by the edge detection circuit 521 , the edge detection circuit 521 may activate both of the pre-emphasis control signals PECS 1 and PECS 2 .
  • a first rising edge e.g., ‘00’->‘11’
  • the edge detection circuits 531 , 532 , 533 , 534 , 535 , and 536 may be selectively enabled based on edge detection enable signals EDEN_F 1 , EDEN_F 2 , EDEN_F 3 , EDEN_F 4 , EDEN_F 5 , and EDEN_F 6 , respectively.
  • each of the edge detection circuits 531 , 532 , 533 , 534 , 535 , and 536 may detect a respective falling edge of the output data signal DS 1 based on the first and second bits D 0 and D 1 to activate at least one of the pre-emphasis control signals PECS 1 and PECS 2 .
  • the edge detection circuit 531 may be enabled based on the edge detection enable signal EDEN_Fl.
  • the edge detection circuit 531 may detect a first falling edge (e.g., ‘11’->‘00’) in which the output data signal DS 1 is transitioned from the fourth voltage level VL 41 to the first voltage level VL 11 .
  • a first falling edge e.g., ‘11’->‘00’
  • the edge detection circuit 531 may activate both of the pre-emphasis control signals PECS 1 and PECS 2 .
  • both of two pre-emphasis control signals PECS 1 and PECS 2 may be activated. In other cases, only one of the pre-emphasis control signals PECS 1 and PECS 2 may be activated.
  • FIGS. 10A and 10B are block diagrams illustrating an edge detection circuit included in the edge detection logic of FIG. 9 according to exemplary embodiments of the inventive concept.
  • the edge detection circuit 521 may include a NOR gate 611 , an AND gate 613 , a delay circuit 615 , and a multiplexer 617 .
  • the NOR gate 611 may perform a NOR operation on the first and second bits D 0 and D 1 .
  • the AND gate 613 may perform an AND operation on the first and second bits D 0 and D 1 .
  • the delay circuit 615 may delay an output of the NOR gate 611 .
  • the multiplexer 617 may output one of an output of the delay circuit 615 and an output of the AND gate 613 as the first and second pre-emphasis control signals PECS 1 and PECS 2 based on the edge detection enable signal EDEN_R 1 .
  • the multiplexer 617 may output the output of the delay circuit 615 when the edge detection enable signal EDEN_R 1 is activated, and may output the output of the AND gate 613 when the edge detection enable signal EDEN_R 1 is deactivated.
  • the multiplexer 617 may output the activated first and second pre-emphasis control signals PECS 1 and PECS 2 .
  • the edge detection circuit 524 may include a NOR gate 621 , an AND gate 623 , a delay circuit 625 , and a multiplexer 627 .
  • the descriptions of elements already described with reference to FIG. 10A will be omitted.
  • the NOR gate 621 and the delay circuit 625 may be substantially the same as the NOR gate 611 and the delay circuit 615 in FIG. 10A , respectively.
  • the AND gate 623 may perform an AND operation on an inverted bit of the first bit D 0 and the second bit D 1 .
  • the multiplexer 627 may output one of an output of the delay circuit 625 and an output of the AND gate 623 as the second pre-emphasis control signal PECS 2 based on the edge detection enable signal EDEN_R 4 .
  • the multiplexer 627 may output the activated second pre-emphasis control signal PECS 2 .
  • the first pre-emphasis control signal PECS 1 may not be generated or may always be deactivated.
  • the remaining edge detection circuits 522 , 523 , 525 , 526 , 531 , 532 , 533 , 534 , 535 , and 536 may also be implemented to detect corresponding edges, and may have configurations similar to those of FIGS. 10A and 10B .
  • FIGS. 11A, 11B, 11C, 11D, 11E, and 12 are diagrams for describing operations performed by a method of generating a multi-level signal and a transmitter according to an exemplary embodiment of the inventive concept.
  • FIGS. 11A, 11B, 11C, 11D, and 11E are enlarged views of a portion ‘A’ in FIG. 7B .
  • a graph on the left illustrates a case in which the selective equalization scheme according to an exemplary embodiment of the inventive concept is not applied
  • a graph on the right illustrates a case in which the selective equalization scheme according to an exemplary embodiment of the inventive concept is applied.
  • all edges may have the same transition time TT 1 and TT 2 .
  • the edge detection circuit 521 may be enabled, a slope of the first rising edge (e.g., ‘00’->‘11’) transitioning from the first voltage level VL 11 to the fourth voltage level VL 41 may increase, and a transition time of the first rising edge may decrease from TT 1 to TT 11 .
  • the jitter characteristic of the eye EYE 31 may be improved from JT_HO to JT_H 1 .
  • the edge detection circuit 527 may be additionally enabled, a slope of the first falling edge (e.g., ‘11’->‘00’) transitioning from the fourth voltage level VL 41 to the first voltage level VL 11 may further increase, and a transition time of the first falling edge may further decrease.
  • the jitter characteristic of the eye EYE 11 may be further improved from JT_LO to JT_L 2 .
  • the edge detection circuits 522 and 532 may be additionally enabled.
  • slopes of a second rising edge (e.g., ‘00’->‘10’) transitioning from the first voltage level VL 11 to the third voltage level VL 31 and a second falling edge (e.g., ‘11’->‘01’) transitioning from the fourth voltage level VL 41 to the second voltage level VL 21 may further increase, and transition times of the second rising edge and the second falling edge may further decrease.
  • the jitter characteristic of the eye EYE 21 may be further improved from JT_MO to JT_M 3 .
  • the edge detection circuits 523 , 524 , 525 , 533 , 534 , and 535 may be additionally enabled.
  • slopes of a third rising edge (e.g., ‘00’->‘01’) transitioning from the first voltage level VL 11 to the second voltage level VL 21 , the fourth rising edge (e.g., ‘01’->‘11’) transitioning from the second voltage level VL 21 to the fourth voltage level VL 41 , a fifth rising edge (e.g., ‘01’->‘10’) transitioning from the second voltage level VL 21 to the third voltage level VL 31 , a third falling edge (e.g., ‘11’->‘10’) transitioning from the fourth voltage level VL 41 to the third voltage level VL 31 , a fourth falling edge (e.g., ‘10’->‘00’) transitioning from the third voltage level VL 31 to the first voltage level VL 11 , and a fifth falling edge (e.g., ‘10’->‘01’) transitioning from the third voltage level VL 31 to the second voltage level VL 21 may further increase, and transition times of the third, fourth, and fifth rising edges
  • all of the edge detection circuits 521 , 522 , 523 , 524 , 525 , 526 , 531 , 532 , 533 , 534 , 535 , and 536 may be enabled, slopes of all of the rising edges and the falling edges may increase, and transition times of all of the rising edges and the falling edges may decrease.
  • the jitter characteristics of all of the eyes EYE 11 , EYE 21 , and EYE 31 may be improved from JTO to JTS.
  • the cases on the right in FIGS. 11A, 11B, 11C, 11D, and 11E are represented in the graph of FIG. 7C as CASE 1 , CASE 2 , CASE 3 , CASE 4 , and CASE 5 , respectively.
  • the target and number of the equalizing operations may be set in consideration of the power consumption and characteristics of channels.
  • FIG. 13 is a flowchart illustrating an example of changing a drive strength of at least one of two or more driving paths in FIG. 1 according to an exemplary embodiment of the inventive concept. The descriptions of elements already described with reference to FIG. 2 will be omitted.
  • operations S 210 , S 230 , S 240 , and S 250 in FIG. 13 may be substantially the same as operations S 210 , S 230 , S 240 , and S 250 in FIG. 2 , respectively.
  • At least one of the two or more pre-emphasis control signals may be activated (operation S 230 ), and the drive strength of the at least one of the two or more driving paths may increase based on the activated pre-emphasis control signal such that a transition time of the output data signal for the detected target edge decreases (operation S 240 ).
  • FIG. 2 may correspond to FIG. 11A in which the equalizing operation is performed on only one edge
  • FIG. 13 may correspond to FIGS. 11B, 11C, 11D, and 11E in which the equalizing operation is performed on two or more edges.
  • FIG. 14 is a diagram for describing a data signal generated by a method of generating a multi-level signal according to an exemplary embodiment of the inventive concept. The descriptions of elements already described with reference to FIG. 7B will be omitted.
  • first, second, third, fourth, fifth, sixth, seventh, and eighth voltage levels VL 12 , VL 22 , VL 32 , VL 42 , VL 52 , VL 62 , VL 72 , and VL 82 of a data signal (e.g., a PAM 8 signal) that is generated based on the 8 -level scheme (e.g., the PAM 8 scheme) are illustrated, and first, second, third, fourth, fifth, sixth, and seventh eyes EYE 12 , EYE 22 , EYE 32 , EYE 42 , EYE 52 , EYE 62 , and EYE 72 of the data signal are illustrated.
  • the equalizing operation may be selectively performed only on some edges that affect the eye characteristics.
  • FIG. 15 is a block diagram illustrating a transmitter according to an exemplary embodiment of the inventive concept. The descriptions of elements already described with reference to FIG. 8 will be omitted.
  • a transmitter 700 includes a multiplexer 710 , an edge detection logic 720 , and two or more driving paths 740 , 750 , and 760 .
  • the transmitter 700 may further include a data I/O pad 780 .
  • the multiplexer 710 , the edge detection logic 720 , the driving paths 740 , 750 , and 760 , and the data I/O pad 780 may correspond to the multiplexer 510 , the edge detection logic 520 , the driving paths 540 and 550 , and the data I/O pad 580 in FIG. 8 , respectively.
  • input data DAT 2 may include a first bit D 0 , a second bit D 1 , and a third bit D 2 that are different from one another, and the multiplexer 710 may divide the input data DAT 2 into the first, second, and third bits D 0 , D 1 , and D 2 based on an eight-phase clock signal CK_ 8 P.
  • the two or more driving paths 740 , 750 , and 760 may include a first driving path 740 that operates based on the first bit D 0 and a first pre-emphasis control signal PECS 1 , a second driving path 750 that operates based on the second bit D 1 and a second pre-emphasis control signal PECS 2 , and a third driving path 760 that operates based on the third bit D 2 and a third pre-emphasis control signal PECS 3 .
  • An output data signal DS 2 may correspond to the data signal illustrated in FIG.
  • VL 14 may have one the first, second, third, fourth, fifth, sixth, seventh, and eighth voltage levels VL 12 , VL 22 , VL 32 , VL 42 , VL 52 , VL 62 , VL 72 , and VL 82 , that are different from one another, during one unit interval.
  • the first bit D 0 may be a LSB of the input data DAT 2
  • the second bit D 1 may be a central significant bit (CSB) of the input data DAT 2
  • the third bit D 2 may be an MSB of the input data DAT 2 .
  • the first driving path 740 may include a first data buffer 741 , a first driver circuit 743 , and a first pre-emphasis driver circuit 745 .
  • the second driving path 750 may include a second data buffer 751 , a second driver circuit 753 , a third driver circuit 755 , and a second pre-emphasis driver circuit 757 .
  • the third driving path 760 may include a third data buffer 761 , a fourth driver circuit 763 , a fifth driver circuit 765 , a sixth driver circuit 767 , a seventh driver circuit 769 , and a third pre-emphasis driver circuit 771 .
  • Operations of the data buffers 741 , 751 , and 761 , operations of the driver circuits 743 , 753 , 755 , 763 , 765 , 767 , and 769 generating driving currents I 1 , I 2 , I 3 , I 4 , I 5 , I 6 , and I 7 , respectively, and operations of the pre-emphasis driver circuits 745 , 757 , and 771 generating currents IP 1 , IP 2 , and IP 3 may be substantially the same as those described with reference to FIG. 8 .
  • FIG. 15 illustrates that a configuration 730 for increasing the drive strength includes the pre-emphasis driver circuits 745 , 757 , and 771 included in the driving paths 740 , 750 , and 760 , the inventive concept is not limited thereto.
  • FIGS. 16 and 17 are flowcharts illustrating a method of transmitting data according to exemplary embodiments of the inventive concept.
  • a first output data signal that is a multi-level signal is generated based on first input data (operation S 1100 ).
  • a second output data signal that is the multi-level signal is generated based on second input data (operation S 1200 ).
  • the first output data signal and the second output data signal are transmitted through a first channel and a second channel, respectively (operation S 1300 ).
  • operations S 1100 and S 1200 in FIG. 17 may be substantially the same as operations S 1100 and S 1200 in FIG. 16 , respectively.
  • An N-th output data signal that is the multi-level signal is generated based on N-th input data (operation S 1400 ).
  • the first through N-th output data signals are transmitted through first through N-th channels, respectively (operation S 1500 ).
  • Each of operations S 1100 , S 1200 , and S 1400 may be performed based on the method of generating the multi-level signal according to exemplary embodiments of the inventive concept described with reference to FIGS. 1 through 15 .
  • a drive strength of at least one of two or more driving paths may be changed based on the two or more bits included in the first input data such that a first transition time, during which the first output data signal is transitioned from a first voltage level to a second voltage level, is changed.
  • the first output data signal may be generated such that the first transition time of the first output data signal is changed and a second transition time, during which the first output data signal is transitioned from the first voltage level to a third voltage level different from the second voltage level, is maintained.
  • a drive strength of at least one of two or more driving paths may be changed based on the two or more bits included in the second input data such that a third transition time, during which the second output data signal is transitioned from the first voltage level to the second voltage level, is changed.
  • the second output data signal may be generated such that the third transition time of the second output data signal is changed and a fourth transition time, during which the second output data signal is transitioned from the first voltage level to the third voltage level, is maintained.
  • a drive strength of at least one of two or more driving paths may be changed based on the two or more bits included in the second input data such that a third transition time, during which the second output data signal is transitioned from a fourth voltage level different from the first voltage level to the second voltage level, is changed.
  • the second output data signal may be generated such that the third transition time of the second output data signal is changed and a fourth transition time, during which the second output data signal is transitioned from the fourth voltage level to the third voltage level, is maintained.
  • characteristics of the first and second channels in FIG. 16 may be substantially the same as each other, and characteristics of the first through N-th channels in FIG. 17 may be substantially the same as one another.
  • all of the output data signals may have substantially the same waveform (e.g., one of the waveforms in FIGS. 11A through 11E ).
  • characteristics of the first and second channels in FIG. 16 may be different from each other, and characteristics of the first through N-th channels in FIG. 17 may be different from one another.
  • the output data signals may have different waveforms (e.g., different waveforms among the waveforms in FIGS. 11A through 11E ) in consideration of the characteristics of the channels.
  • the methods of transmitting the data of FIGS. 16 and 17 may be performed by the memory system according to exemplary embodiments of the inventive concept.
  • the output data signals may be generated by the memory controller 21 (e.g., by the transmitters 25 a , 25 b , and 25 c ).
  • the output data signals may be generated by the memory device 41 (e.g., by the transmitters 45 a , 45 b , and 45 c ).
  • FIGS. 18A and 18B are block diagrams illustrating a memory system according to an exemplary embodiment of the inventive concept. The descriptions of elements already described with reference to FIGS. 4A and 4B will be omitted.
  • a memory system 12 includes a memory controller 22 , a memory device 42 , and the plurality of channels 31 a , 31 b , and 31 c.
  • the memory system 12 may be substantially the same as the memory system 11 of FIG. 4A , except that the memory device 42 and the memory controller 22 further include an eye monitor circuit 51 a and an enable signal generation circuit 53 a , respectively.
  • the eye monitor circuit 51 a may be connected to the plurality of channels 31 a , 31 b , and 31 c , and may generate characteristic data CDAT 1 that represents characteristics of the channels 31 a , 31 b , and 31 c based on the received output data signals DS 11 , DS 21 and DS 31 .
  • the enable signal generation circuit 53 a may generate the edge detection enable signals EDEN based on the characteristic data CDAT 1 . It may be determined in real time, based on the characteristics of the channels 31 a , 31 b , and 31 c , that the equalizing operation is to be performed on which edge.
  • a memory system 13 includes a memory controller 23 , a memory device 43 , and the plurality of channels 31 a , 31 b , and 31 c.
  • the memory system 13 may be substantially the same as the memory system 11 of FIG. 4B , except that the memory controller 23 and the memory device 43 further include an eye monitor circuit 51 b generating characteristic data CDAT 2 and an enable signal generation circuit 53 b , respectively.
  • the eye monitor circuit 51 b and the enable signal generation circuit 53 b may be substantially the same as the eye monitor circuit 51 a and the enable signal generation circuit 53 a in FIG. 18A , respectively.
  • FIG. 19 is a block diagram illustrating a computing system according to an exemplary embodiment of the inventive concept.
  • a computing system 1300 includes a processor 1310 , a system controller 1320 , and a memory system 1330 .
  • the computing system 1300 may further include an input device 1350 , an output device 1360 , and a storage device 1370 .
  • the memory system 1330 includes a plurality of memory devices 1334 and a memory controller 1332 for controlling the memory devices 1334 .
  • the memory controller 1332 may be included in the system controller 1320 .
  • the memory system 1330 may be the memory system according to exemplary embodiments of the inventive concept, and may perform the method of generating the multi-level signal and the method of transmitting the data according to exemplary embodiments of the inventive concept.
  • the processor 1310 may perform various computing functions, such as executing specific software instructions for performing specific calculations or tasks.
  • the processor 1310 may be connected to the system controller 1320 via a processor bus.
  • the system controller 1320 may be connected to the input device 1350 , the output device 1360 , and the storage device 1370 via an expansion bus. As such, the processor 1310 may control the input device 1350 , the output device 1360 , and the storage device 1370 using the system controller 1320 .
  • FIG. 20 is a block diagram illustrating a communication system according to an exemplary embodiment of the inventive concept.
  • a communication system 2000 includes a first communication device 2100 , a second communication device 2200 , and a channel 2300 .
  • the first communication device 2100 includes a first transmitter 2110 and a first receiver 2120 .
  • the second communication device 2200 includes a second transmitter 2210 and a second receiver 2220 .
  • the first transmitter 2110 and the first receiver 2120 are connected to the second transmitter 2210 and the second receiver 2220 through the channel 2300 .
  • each of the first and second communication devices 2100 and 2200 may include a plurality of transmitters and a plurality of receivers
  • the communication system 2000 may include a plurality of channels for connecting the plurality of transmitters and the plurality of receivers.
  • the transmitters 2110 and 2210 may be the transmitter according to exemplary embodiments of the inventive concept, and may perform the method of generating the multi-level signal and the method of transmitting the data according to exemplary embodiments of the inventive concept.
  • the inventive concept may be applied to various devices and systems that include memory devices and memory systems.
  • the inventive concept may be applied to systems such as a personal computer (PC), a server computer, a data center, a workstation, a mobile phone, a smart phone, a tablet computer, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a portable game console, a music player, a camcorder, a video player, a navigation device, a wearable device, an internet of things (IoT) device, an internet of everything (IoE) device, an e-book reader, a virtual reality (VR) device, an augmented reality (AR) device, a robotic device, a drone, etc.
  • PC personal computer
  • server computer a data center
  • workstation a mobile phone, a smart phone, a tablet computer, a laptop computer
  • PDA personal digital assistant
  • PMP portable multimedia player
  • digital camera a portable game console
  • music player a camcord
  • a selective or adaptive equalization scheme may be implemented.
  • existing or conventional driving paths may be used as is, and the equalizing operation may be performed only when a specific level transition occurs on the output data signal.
  • the equalizing operation may be performed only on some level transitions that are capable of occurring on the multi-level signal. Accordingly, as compared to a case where the equalizing operation is performed on all level transitions, power consumption may be reduced and the signal characteristic may be efficiently improved or enhanced.

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