US20210384250A1 - Solid-state imaging device and electronic apparatus - Google Patents

Solid-state imaging device and electronic apparatus Download PDF

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US20210384250A1
US20210384250A1 US17/282,420 US201917282420A US2021384250A1 US 20210384250 A1 US20210384250 A1 US 20210384250A1 US 201917282420 A US201917282420 A US 201917282420A US 2021384250 A1 US2021384250 A1 US 2021384250A1
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solid
imaging device
state imaging
fixed charge
groove portion
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US12107112B2 (en
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Itaru Oshiyama
Shinichiro Noudo
Yasufumi Miyoshi
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14625—Optical elements or arrangements associated with the device
    • H01L27/14627—Microlenses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H01L27/14623—Optical shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14625—Optical elements or arrangements associated with the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1464—Back illuminated imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N5/374—

Definitions

  • the present technology relates to a solid-state imaging device and an electronic apparatus.
  • An object of the present disclosure is to provide a solid-state imaging device and an electronic apparatus having further improved characteristics such as reduction of optical color mixing.
  • a solid-state imaging device of the present disclosure includes (a) a substrate; (b) a plurality of photoelectric conversion portions formed on the substrate; (c) groove portions provided between adjacent photoelectric conversion portions; and (d) a fixed charge film which covers a sidewall surface and a bottom surface of the groove portions, and a light reception surface side of the substrate and which contains at least one of hafnium, aluminum, zirconium, tantalum, and titanium, wherein (e) at least some of open ends of the groove portions are closed by the fixed charge film with a void left inside the groove portion.
  • An electronic apparatus of the present disclosure includes (a) a solid-state imaging device including a substrate, a plurality of photoelectric conversion portions formed on the substrate, groove portions provided between adjacent photoelectric conversion portions, and a fixed charge film which covers a sidewall surface and a bottom surface of the groove portions, and a light reception surface side of the substrate and which contains at least one of hafnium, aluminum, zirconium, tantalum, and titanium; (b) an optical lens that forms an image of image light from a subject on an imaging surface of the solid-state imaging device; and (c) a signal processing circuit that performs signal processing on a signal output from the solid-state imaging device, wherein (d) at least some of open ends of the groove portion are closed by the fixed charge film with a void left inside the groove portion.
  • FIG. 1 is a diagram illustrating an overall configuration of a solid-state imaging device according to a first embodiment of the present disclosure.
  • FIG. 2 is a diagram illustrating a cross-sectional configuration of a pixel region taken along line A-A of FIG. 1 .
  • FIG. 3 is a diagram illustrating a planar structure of a groove portion taken along line B-B of FIG. 2 .
  • FIG. 4 is an enlarged view of main portions illustrating an enlarged cross-sectional structure of an element isolation portion.
  • FIG. 5A is a diagram illustrating a flow of processing of manufacturing the solid-state imaging device according to the first embodiment.
  • FIG. 5B is a diagram illustrating the flow of processing of manufacturing the solid-state imaging device according to the first embodiment.
  • FIG. 5C is a diagram illustrating the flow of processing of manufacturing the solid-state imaging device according to the first embodiment.
  • FIG. 5D is a diagram illustrating the flow of processing of manufacturing the solid-state imaging device according to the first embodiment.
  • FIG. 5E is a diagram illustrating the flow of processing of manufacturing the solid-state imaging device according to the first embodiment.
  • FIG. 6 is a diagram illustrating a planar layout of a substrate of a solid-state imaging device according to a modification example.
  • FIG. 7 is a diagram illustrating a cross-sectional configuration of a pixel region of a solid-state imaging device according to the related art.
  • FIG. 8A is a diagram illustrating a configuration of an intersection portion of a solid-state imaging device according to the modification example.
  • FIG. 8B is a diagram illustrating the configuration of the intersection portion of the solid-state imaging device according to the modification example.
  • FIG. 8C is a diagram illustrating the configuration of the intersection portion of the solid-state imaging device according to the modification example.
  • FIG. 8D is a diagram illustrating the configuration of the intersection portion of the solid-state imaging device according to the modification example.
  • FIG. 8E is a diagram illustrating the configuration of the intersection portion of the solid-state imaging device according to the modification example.
  • FIG. 9A is a diagram illustrating the configuration of the intersection portion of the solid-state imaging device according to the modification example.
  • FIG. 9B is a diagram illustrating the configuration of the intersection portion of the solid-state imaging device according to the modification example.
  • FIG. 9C is a diagram illustrating the configuration of the intersection portion of the solid-state imaging device according to the modification example.
  • FIG. 9D is a diagram illustrating the configuration of the intersection portion of the solid-state imaging device according to the modification example.
  • FIG. 9E is a diagram illustrating the configuration of the intersection portion of the solid-state imaging device according to the modification example.
  • FIG. 10A is a diagram illustrating the configuration of the intersection portion of the solid-state imaging device according to the modification example.
  • FIG. 10B is a diagram illustrating the configuration of the intersection portion of the solid-state imaging device according to the modification example.
  • FIG. 10C is a diagram illustrating the configuration of the intersection portion of the solid-state imaging device according to the modification example.
  • FIG. 10D is a diagram illustrating the configuration of the intersection portion of the solid-state imaging device according to the modification example.
  • FIG. 10E is a diagram illustrating the configuration of the intersection portion of the solid-state imaging device according to the modification example.
  • FIG. 11A is a diagram illustrating the configuration of the intersection portion of the solid-state imaging device according to the modification example.
  • FIG. 11B is a diagram illustrating the configuration of the intersection portion of the solid-state imaging device according to the modification example.
  • FIG. 11C is a diagram illustrating the configuration of the intersection portion of the solid-state imaging device according to the modification example.
  • FIG. 11D is a diagram illustrating the configuration of the intersection portion of the solid-state imaging device according to the modification example.
  • FIG. 11E is a diagram illustrating the configuration of the intersection portion of the solid-state imaging device according to the modification example.
  • FIG. 12 is a diagram illustrating the configuration of the intersection portion of the solid-state imaging device according to the modification example.
  • FIG. 13 is a diagram illustrating the configuration of the intersection portion of the solid-state imaging device according to the modification example.
  • FIG. 14A is a diagram illustrating a pixel structure of the solid-state imaging device according to the modification example.
  • FIG. 14B is a diagram illustrating the pixel structure of the solid-state imaging device according to the modification example.
  • FIG. 14C is a diagram illustrating the pixel structure of the solid-state imaging device according to the modification example.
  • FIG. 14D is a diagram illustrating the pixel structure of the solid-state imaging device according to the modification example.
  • FIG. 15A is a diagram illustrating a flow of processing of manufacturing a solid-state imaging device according to a modification example.
  • FIG. 15B is a diagram illustrating a cross-sectional configuration taken along line C-C of FIG. 15A .
  • FIG. 15C is a diagram illustrating a flow of processing of manufacturing a solid-state imaging device according to a modification example.
  • FIG. 15D is a diagram illustrating a cross-sectional configuration taken along line D-D of FIG. 15C .
  • FIG. 15E is a diagram illustrating a flow of processing of manufacturing the solid-state imaging device according to the modification example.
  • FIG. 15F is a diagram illustrating a cross-sectional configuration taken along line E-E of FIG. 15E .
  • FIG. 15G is a diagram illustrating a flow of processing of manufacturing a solid-state imaging device according to a modification example.
  • FIG. 15H is a diagram illustrating a cross-sectional configuration taken along line F-F of FIG. 15G .
  • FIG. 15I is a diagram illustrating a flow of processing of manufacturing a solid-state imaging device according to a modification example.
  • FIG. 15J is a diagram illustrating a cross-sectional configuration taken along line G-G of FIG. 15I .
  • FIG. 15K is a diagram illustrating a flow of processing of manufacturing a solid-state imaging device according to a modification example.
  • FIG. 15L is a diagram illustrating a cross-sectional configuration taken along line H-H of FIG. 15K .
  • FIG. 15M is a diagram illustrating a flow of processing of manufacturing a solid-state imaging device according to a modification example.
  • FIG. 15N is a diagram illustrating a cross-sectional configuration taken along line I-I of FIG. 15M .
  • FIG. 16A is a diagram illustrating a flow of processing of manufacturing a solid-state imaging device according to the related art.
  • FIG. 16B is a diagram illustrating a cross-sectional configuration taken along line J-J of FIG. 16A
  • FIG. 16C is a diagram illustrating a flow of processing of manufacturing a solid-state imaging device according to the related art.
  • FIG. 16D is a diagram illustrating a cross-sectional configuration taken along line K-K of FIG. 16C .
  • FIG. 16E is a diagram illustrating a flow of processing of manufacturing a solid-state imaging device according to the related art.
  • FIG. 16F is a diagram illustrating a cross-sectional configuration taken along line L-L of FIG. 16E .
  • FIG. 17A is a diagram illustrating a flow of processing of manufacturing a solid-state imaging device according to a modification example.
  • FIG. 17B is a diagram illustrating a cross-sectional configuration taken along line M-M of FIG. 17A .
  • FIG. 17C is a diagram illustrating a flow of processing of manufacturing a solid-state imaging device according to a modification example.
  • FIG. 17D is a diagram illustrating a cross-sectional configuration taken along line N-N of FIG. 17C .
  • FIG. 17E is a diagram illustrating a flow of processing of manufacturing a solid-state imaging device according to a modification example.
  • FIG. 17F is a diagram illustrating a cross-sectional configuration taken along line O-O of FIG. 17E .
  • FIG. 17G is a diagram illustrating a flow of processing of manufacturing a solid-state imaging device according to a modification example.
  • FIG. 17H is a diagram illustrating a cross-sectional configuration taken along line P-P of FIG. 17G .
  • FIG. 17I is a diagram illustrating a flow of processing of manufacturing a solid-state imaging device according to a modification example.
  • FIG. 17J is a diagram illustrating a cross-sectional configuration taken along line Q-Q of FIG. 17I .
  • FIG. 18 is a diagram illustrating a planar layout of a fixed charge film of a solid-state imaging device according to a modification example.
  • FIG. 19 is a diagram illustrating a cross-sectional configuration of an element isolation portion of the solid-state imaging device according to the first embodiment.
  • FIG. 20 is a diagram illustrating a cross-sectional configuration of a pixel region of a solid-state imaging device according to a second embodiment of the present disclosure.
  • FIG. 21A is a diagram illustrating a flow of processing of manufacturing the solid-state imaging device according to the second embodiment.
  • FIG. 21B is a diagram illustrating a flow of processing of manufacturing the solid-state imaging device according to the second embodiment.
  • FIG. 22 is a cross-sectional view illustrating a cross-sectional configuration of a pixel region of a solid-state imaging device according to a modification example.
  • FIG. 23 is a cross-sectional view illustrating a cross-sectional configuration of a pixel region of a solid-state imaging device according to a modification example.
  • FIG. 24 is a cross-sectional view illustrating a cross-sectional configuration of a pixel region of a solid-state imaging device according to a modification example.
  • FIG. 25 is a cross-sectional view illustrating a cross-sectional configuration of a pixel region of a solid-state imaging device according to a modification example.
  • FIG. 26 is a schematic configuration diagram of an electronic apparatus according to a third embodiment of the present disclosure.
  • the present inventors have discovered the following problems in the solid-state imaging device described in PTL 1.
  • a difference between a refractive index of a substrate (for example, 3.9 in the case of silicon (Si)) and a refractive index of an insulation film (for example, 1.4 in the case of being silicon oxide (SiO 2 )) is small, there is a possibility of sufficient reflection characteristics not being obtained in a groove portion between adjacent photoelectric conversion portions, light being transmitted through the groove portion, and optical color mixing being caused.
  • a film thickness of a fixed charge film between the substrate and the insulation film is very small, influence on the reflection characteristics is small.
  • FIGS. 1 to 26 An example of the solid-state imaging device and the electronic apparatus according to the embodiment of the present disclosure will be described with reference to FIGS. 1 to 26 .
  • the embodiments of the present disclosure will be described in the following order.
  • the present disclosure is not limited to the following examples. Further, effects described in the present specification are merely examples and are not limited, and other effects may be obtained.
  • FIG. 1 is a schematic configuration diagram illustrating an entire solid-state imaging device according to a first embodiment of the present disclosure.
  • the solid-state imaging device 1 in FIG. 1 is a back-illuminated complementary metal oxide semiconductor (CMOS) image sensor.
  • CMOS complementary metal oxide semiconductor
  • the solid-state imaging device 1 ( 101 ) captures image light (incident light 106 ) from a subject through an optical lens 102 , converts an amount of incident light 106 formed as an image on an imaging surface to an electrical signal in units of pixels, and outputs the electrical signal as a pixel signal.
  • CMOS complementary metal oxide semiconductor
  • the solid-state imaging device 1 of the first embodiment includes a substrate 2 , a pixel region 3 , a vertical drive circuit 4 , a column signal processing circuit 5 , a horizontal drive circuit 6 , an output circuit 7 , and a control circuit 8 , as illustrated in FIG. 1 .
  • the pixel region 3 includes a plurality of pixels 9 arranged regularly in a two-dimensional array on the substrate 2 .
  • the pixel 9 includes a photoelectric conversion portion 24 illustrated in FIG. 2 and a plurality of pixel transistors (not illustrated).
  • the plurality of pixel transistors for example, four transistors such as a transfer transistor, a reset transistor, a selection transistor, and an amplifier transistor can be adopted. Further, for example, three transistors other than the selection transistor may be adopted.
  • the vertical drive circuit 4 is configured of, for example, a shift register, selects a desired pixel drive wiring 10 , supplies a pulse for driving the pixel 9 to the selected pixel drive wiring 10 , and drives the respective pixels 9 in units of rows. That is, the vertical drive circuit 4 selectively scans the respective pixels 9 in the pixel region 3 in a vertical direction sequentially in units of rows, and supplies a pixel signal based on signal charge generated by the photoelectric conversion portion 24 of each pixel 9 according to an amount of received light to the column signal processing circuit 5 through the vertical signal line 11 .
  • the column signal processing circuit 5 is disposed in each column of the pixel 9 , for example, and performs signal processing such as noise removal for each pixel column on a signal output from the pixel 9 for one row.
  • the column signal processing circuit 5 performs signal processing such as correlated double sampling (CDS) for removing fixed pattern noise unique to the pixel, and analog-to-digital (AD) conversion.
  • CDS correlated double sampling
  • AD analog-to-digital
  • the horizontal drive circuit 6 is configured of, for example, a shift register, sequentially outputs horizontal scanning pulses to the column signal processing circuit 5 to select the respective column signal processing circuits 5 in order, and causes the pixel signal subjected to signal processing to be output from the respective column signal processing circuits 5 to a horizontal signal line 12 .
  • the output circuit 7 performs signal processing on pixel signals sequentially supplied from the respective column signal processing circuits 5 through the horizontal signal line 12 and outputs resultant signals.
  • the signal processing for example, buffering, black level adjustment, column variation correction, and various digital signal processing can be used.
  • the control circuit 8 generates a clock signal or a control signal serving as a reference for an operation of the vertical drive circuit 4 , the column signal processing circuit 5 , the horizontal drive circuit 6 , and the like on the basis of a vertical synchronization signal, a horizontal synchronization signal, and a master clock signal.
  • the control circuit 8 outputs the generated clock signal or control signal to the vertical drive circuit 4 , the column signal processing circuit 5 , the horizontal drive circuit 6 , and the like.
  • FIG. 2 is a diagram illustrating a cross-sectional configuration of the pixel region 3 and the like of the solid-state imaging device 1 according to the first embodiment.
  • a back-illuminated CMOS image sensor CMOS type solid-state imaging device
  • CMOS type solid-state imaging device is used as the solid-state imaging device 1 .
  • the solid-state imaging device 1 of the first embodiment includes a light reception layer 18 in which the substrate 2 , a first fixed charge film 13 , a second fixed charge film 14 , an insulation film 15 , a light shielding film 16 , and a flattening film 17 are stacked in this order. Further, a condensing layer 21 in which a color filter layer 19 and an on-chip lens 20 are stacked in this order is formed on a surface of the light reception layer 18 on the flattening film 17 side (hereinafter, also referred to as “back surface S 1 side”).
  • a wiring layer 22 and a support substrate 23 are stacked in this order on a surface of the light reception layer 18 on the substrate 2 side (hereinafter also referred to as “front surface S 2 side”).
  • front surface S 2 side a surface of the light reception layer 18 on the substrate 2 side
  • back surface S 1 of the light reception layer 18 and a back surface of the flattening film 17 are the same surface
  • back surface S 1 the back surface of the flattening film 17
  • the front surface of the substrate 2 is also referred to as “front surface S 2 ” in the following description.
  • the substrate 2 is configured of, for example, a semiconductor substrate made of silicon (Si), and forms the pixel region 3 as illustrated in FIG. 1 .
  • a plurality of pixels 9 including a plurality of photoelectric conversion portions 24 formed (embedded) on the substrate 2 are arranged in a two-dimensional array, as illustrated in FIG. 2 .
  • the photoelectric conversion portion 24 includes p-type semiconductor regions 25 and 26 formed on the front surface S 2 side and the back surface S 3 side of the substrate 2 , respectively, and an n-type semiconductor region 27 formed between the p-type semiconductor regions 25 and 26 .
  • a photodiode is formed of a pn junction between the p-type semiconductor regions 25 and 26 and the n-type semiconductor regions 27 .
  • signal charge according to the amount of incident light is generated, and the generated signal charge is accumulated in the n-type semiconductor regions 27 .
  • electrons that cause a dark current generated at an interface of the substrate 2 are absorbed by holes that are majority carriers of the p-type semiconductor regions 25 and 26 formed on the front surface S 2 and the back surface S 3 of the substrate 2 , thereby curbing the dark current.
  • each photoelectric conversion portion 24 is electrically isolated by a pixel isolation layer 28 formed of a p-type semiconductor region and an element isolation portion 29 formed in the pixel isolation layer 28 .
  • the pixel isolation layer 28 and the element isolation portion 29 are formed in a grid pattern to surround each photoelectric conversion portion 24 , as illustrated in FIG. 3 .
  • the element isolation portion 29 has a groove portion 30 formed in a depth direction from the back surface S 3 side of the substrate 2 , as illustrated in FIG. 2 . That is, the groove portion 30 is engraved and formed between adjacent photoelectric conversion portions 24 on the back surface S 3 side of the substrate 2 (the pixel isolation layer 28 ).
  • the groove portion 30 is formed in a grid pattern configured of a straight portion 31 and an intersection portion 32 to surround each photoelectric conversion portion 24 , as illustrated in FIG. 3 , like the pixel isolation layer 28 and the element isolation portion 29 .
  • the straight portion 31 is a region that isolates two adjacent photoelectric conversion portions 24 , and is a portion in which the groove portions 30 do not intersect with each other.
  • the intersection portion 32 is a portion in which the groove portions 30 intersect with each other.
  • a depth of the groove portion 30 is, for example, equal to or greater than a depth of reaching a p-well layer 33 on which the pixel transistor is formed and smaller than a depth of reaching a floating diffusion portion 34 or a source/drain region.
  • the depth is set to about 0.25 to 5.0 ⁇ m when a depth of the floating diffusion portion 34 or the source/drain region is smaller than 1 ⁇ m.
  • a maximum width of an open end of the intersection portion 32 is usually wider than a maximum width of an open end of the straight portion 31 .
  • an open end of the groove portion 30 is closed by the second fixed charge film 14 so that the void 35 remains inside the groove portion 30 using a PVD method or a CVD method, as will be described below. Therefore, it is preferable for a width of an open end of the groove portion 30 (the straight portion 31 and the intersection portion 32 ) to be a width such that the entire open end of the intersection portion 32 can be closed by the second fixed charge film 14 based on a PVD method or a CVD method. For example, when the maximum width of the intersection portion 32 that can be closed by the second fixed charge film 14 is about 30 nm using the PVD method or the CVD method, the width of the open end of the straight portion 31 is about 20 nm.
  • the first fixed charge film 13 continuously covers a sidewall surface and a bottom surface of the groove portion 30 and the entirety on the back surface S 3 side (the entirety on the light reception surface side) of the substrate 2 .
  • a film thickness of the first fixed charge film 13 is a uniform film thickness in which the groove portion 30 is not completely filled so that a space is formed in the groove portion 30 .
  • the film thickness is about 15 nm. Accordingly, a groove-shaped space (the void 35 ) of which a sidewall surface and a bottom surface are surrounded by the first fixed charge film 13 is formed inside the groove portion 30 .
  • a high refractive index material film or a high dielectric film having negative charge capable of generating fixed charge and strengthening pinning by being deposited on the substrate 2 can be used.
  • an oxide, a nitride, or the like containing at least one element among hafnium (Hf), aluminum (Al), zirconium (Zr), tantalum (Ta), and titanium (Ti) can be adopted.
  • hafnium oxide (HfO 2 ) that can curb the generation of blisters by being deposited on the substrate 2 and is unlikely to peel off from a plane portion of the substrate 2 is more preferable.
  • La lanthanum
  • Pr praseodymium
  • Ce cerium
  • Nd neodymium
  • promethium Pm
  • Sm samarium
  • Eu europium
  • Gd gadolinium
  • Tb terbium
  • Dy dysprosium
  • Ho holmium
  • Tm samarium
  • Yb lutetium
  • an atomic layer deposition method hereinafter also referred to as “ALD method”
  • a chemical vapor deposition method hereinafter also referred to as “CVD method”.
  • ALD method atomic layer deposition method
  • CVD method chemical vapor deposition method
  • the first fixed charge film 13 having negative charge is formed on the sidewall surface and the bottom surface of the groove portion 30 and the entirety on the back surface S 3 side of the substrate 2 , an inversion layer is formed on a surface that is in contact with the first fixed charge film 13 . Accordingly, a silicon interface is pinned by the inversion layer and thus, a dark current is curbed. Further, when the groove portion 30 is formed on the substrate 2 , physical damage is likely to occur on the sidewall surface and the bottom surface of the groove portion 30 , and pinning-out is likely to occur in a peripheral portion of the groove portion 30 . In response to this problem, in the first embodiment, the first fixed charge film 13 having a fixed charge is formed on the sidewall surface and the bottom surface of the groove portion 30 , thereby preventing pinning-out.
  • the groove-shaped void 35 of which a sidewall surface and a bottom surface are surrounded by the first fixed charge film 13 is formed in the groove portion 30 , adjacent photoelectric conversion portions 24 are more reliably electrically isolated.
  • the second fixed charge film 14 closes the open end of the groove portion 30 , and continuously covers the entirety on the back surface S 4 side (the entirety on the light reception surface side) of the first fixed charge film 13 .
  • a film thickness of the second fixed charge film 14 is set to, for example, about 45 nm in order to more reliably close the open end of the groove portion 30 .
  • the inside of the groove portion 30 is closed with a void 35 (so-called void) left. That is, the element isolation portion 29 has a hollow structure having a void 35 .
  • the inside of the void 35 may be filled with air or may be in a vacuum state.
  • the second fixed charge film 14 enters the groove portion 30 so that the sidewall surface on the open end side of the groove portion 30 is covered, as illustrated in FIG. 4 .
  • the film thickness of the second fixed charge film 14 which covers the sidewall surface on the open end side of the groove portion 30 is larger on the open end side of the groove portion 30 than on the back side (bottom surface side).
  • the second fixed charge film 14 has a shape protruding toward an inner wall surface of the groove portion 30 from a center in a width direction of the open end, and the open end of the groove portion 30 is closed by the second fixed charge film 14 .
  • a depressed portion 14 a extending along the groove portion 30 and formed in a grid pattern is provided on a surface of the second fixed charge film 14 on the back surface S 5 side (light reception surface side).
  • a high refractive index material film or a high dielectric film having negative charge capable of generating fixed charge and strengthening pinning by being deposited on the substrate 2 can be used.
  • an oxide, a nitride, or the like containing at least one element among hafnium (Hf), aluminum (Al), zirconium (Zr), tantalum (Ta), and titanium (Ti) can be adopted.
  • a material corresponding to damage of the substrate 2 may be used.
  • aluminum oxide (Al 2 O 3 ) that strengthens pinning of the groove portion 30 is more preferable.
  • a method of forming the second fixed charge film 14 for example, a physical vapor deposition method (hereinafter also referred to as “PVD method”) or a CVD method can be used.
  • PVD method physical vapor deposition method
  • CVD method a chemical vapor deposition method
  • the insulation film 15 continuously covers the entirety on the back surface S 5 side (the entirety on the light reception surface side) of the second fixed charge film 14 .
  • a material of the insulation film 15 for example, an oxide film having a refractive index different from that of the second fixed charge film 14 can be adopted. Specifically, at least one of silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), and silicon oxynitride (SiON) can be adopted.
  • a material having no positive fixed charge and a material having less positive fixed charge are preferable.
  • the light shielding film 16 is formed in a grid pattern to open light reception surfaces of the plurality of photoelectric conversion portions 24 to a part of the insulation film 15 on the back surface S 6 side (a part on the light reception surface side). That is, the light shielding film 16 is formed at a position overlapping the groove portions 30 formed in a grid pattern when the light reception layer 18 is viewed from the back surface S 1 side.
  • a material of the light shielding film 16 for example, a material capable of shielding light can be adopted. Specifically, aluminum (Al), tungsten (W), copper (Cu) and the like can be adopted.
  • the flattening film 17 continuously covers the entirety on the back surface S 6 side (the entirety on the light reception surface side) of the insulation film 15 including the light shielding film 16 . Accordingly, the back surface S 1 of the light reception layer 18 is a flat surface without unevenness.
  • an organic material such as a resin can be used.
  • the color filter layer 19 is formed on the back surface S 1 side (light reception surface side) of the flattening film 17 in correspondence to a wavelength of light to be received by each pixel 9 such as R, G, and B.
  • the color filter layer 19 transmits light having a specific wavelength, and causes the transmitted light to be incident on the photoelectric conversion portion 24 in the substrate 2 .
  • the on-chip lens 20 is formed on the back surface S 7 side (light reception surface side) of the color filter layer 19 in correspondence to each pixel 9 .
  • the on-chip lens 20 collects the irradiation light, and causes the collected light to be efficiently incident on the photoelectric conversion portion 24 in the substrate 2 via the color filter layer 19 .
  • the wiring layer 22 is formed on the front surface S 2 side of the substrate 2 , and includes wirings 37 stacked as a plurality of layers (three layers in FIG. 2 ) via an interlayer insulation film 36 .
  • the pixel transistors constituting each pixel 9 are driven via the plurality of layers of wirings 37 formed in the wiring layer 22 .
  • the support substrate 23 is formed on a surface of the wiring layer 22 opposite to the side facing the substrate 2 .
  • the support substrate 23 is a substrate for ensuring the strength of the substrate 2 in processing of manufacturing the solid-state imaging device 1 .
  • silicon (Si) can be adopted.
  • the solid-state imaging device 1 having the above configuration, light is radiated from the back surface side of the substrate 2 (the back surface S 1 side of the light reception layer 18 ), the irradiated light is transmitted through the on-chip lens 20 and the color filter layer 19 , and the transmitted light is photoelectrically converted by the photoelectric conversion portion 24 such that signal charge is generated.
  • the generated signal charge is output as a pixel signal on the vertical signal line 11 illustrated in FIG. 1 formed of the wiring 37 via the pixel transistor formed on the front surface S 2 side of the substrate 2 .
  • FIGS. 5A, 5B, 5C, 5D, and 5E are cross-sectional views illustrating processing of manufacturing the solid-state imaging device 1 of the first embodiment.
  • the photoelectric conversion portion 24 , the pixel transistor, and the pixel isolation layer 28 are formed on the substrate 2 , and then the interlayer insulation film 36 and the wiring 37 are alternately formed on the front surface S 2 of the substrate 2 so that the wiring layer 22 is formed.
  • An impurity region such as the photoelectric conversion portion 24 formed on the substrate 2 is formed by implanting ion of a desired impurity into the substrate 2 from the front surface S 2 side of the substrate 2 .
  • the support substrate 23 made of silicon (see FIG. 5B ) is adhered to an outermost surface S 8 of the wiring layer 22 and then, a stack of the substrate 2 , the wiring layer 22 and the support substrate 23 is inverted. Manufacturing processing up to here is the same as for a normal back-illuminated solid-state imaging device. Subsequently, after the substrate 2 is inverted, the substrate 2 is polished from the back surface S 3 side to be thinned to a desired thickness, as illustrated in FIG. 5B .
  • each pixel 9 of the substrate 2 that is, at a portion in which the pixel isolation layer 28 is formed as illustrated in FIG. 5C , selective etching is performed in a depth direction from the back surface S 3 side of the substrate 2 (a direction from the back surface S 3 to the front surface S 2 ) so that the groove portion 30 having a desired depth is formed.
  • a method of forming the groove portion 30 for example, a method of providing a hard mask (not illustrated) having a desired opening on the back surface S 3 of the substrate 2 and performing etching through the provided hard mask can be adopted.
  • a step of forming the groove portion 30 can be shared with other substrate penetration processes. Thus, when the step is shared with other substrate penetration processes, the number of steps can be reduced.
  • the hard mask used for processing of the groove portion 30 is removed, and the first fixed charge film 13 is formed so that the sidewall surface and the bottom surface of the groove portion 30 and the entirety on the back surface S 3 side (the entirety on the light reception surface side) of the substrate 2 are continuously covered using the ALD method or the CVD method as illustrated in FIG. 5D .
  • the open end of the groove portion 30 is closed using the PVD method or the CVD method, and the second fixed charge film 14 is formed so that the entirety on the back surface S 4 side (the entirety on the light reception surface side) of the first fixed charge film 13 is covered.
  • a film forming condition is set so that the open end side of the groove portion 30 is closed before the inside of the groove portion 30 is completely embedded by the second fixed charge film 14 .
  • the film forming conditions is optimized such that the element isolation portion 29 having the void 35 can be formed. Accordingly, the straight portion 31 and the intersection portion 32 of the groove portion 30 illustrated in FIG. 3 are closed by the second fixed charge film 14 with the void 35 left inside the groove portion 30 .
  • An internal space of the void 35 is formed in a grid pattern extending along the straight portion 31 and the intersection portion 32 of the groove portion 30 .
  • the insulation film 15 is formed so that the entirety on the back surface S 5 side (the entirety on the light reception surface side) of the second fixed charge film 14 is covered using a PVD method or a CVD method.
  • a light shielding material layer is formed on the entirety on the back surface S 6 side of the insulation film 15 and then is patterned in a desired shape. Accordingly, the photoelectric conversion portion 24 is opened so that the light shielding film 16 that shields light between adjacent pixels 9 is formed, as illustrated in FIG. 5E .
  • the color filter layer 19 and the on-chip lens 20 are formed on the front surface S 2 side of the substrate 2 such that the solid-state imaging device 1 is completed as illustrated in FIG. 2 .
  • the groove portion 30 provided between the adjacent photoelectric conversion portions 24 is closed with the void 35 left inside the groove portion 30 by the second fixed charge film 14 . Therefore, since a difference between a refractive index of the substrate 2 (for example, 3.9 in the case of silicon (Si)) and a refractive index of the void 35 (for example, 1.0 in the case of being filled with air) is great, sufficient reflection characteristics can be obtained in the groove portion 30 between the adjacent photoelectric conversion portions 24 , it is difficult for light to be transmitted through the groove portion 30 , and optical color mixing can be curbed. Since a film thickness of the first fixed charge film 13 between the substrate 2 and the void 35 is very small, an influence on the reflection characteristics is small.
  • the photoelectric conversion portion 24 of each pixel 9 is isolated by the element isolation portion 29 in which the void 35 is formed in the groove portion 30 . Therefore, it is possible to curb leakage of the signal charge accumulated in the photoelectric conversion portion 24 to the adjacent photoelectric conversion portion 24 side. Thus, when an amount of signal charge equal to or larger than a saturated charge amount is generated in the photoelectric conversion portion 24 , it is possible to efficiently swept out the signal charge to the floating diffusion portion 34 side. This can curb the occurrence of blooming.
  • the first fixed charge film 13 having negative charge is formed in the groove portion 30 . Therefore, generation of an interface level and generation of a dark current caused by the interface level can be curbed due to a negative bias effect of the first fixed charge film 13 . Further, an inversion layer (p-type) is formed on a surface that is in contact with the first fixed charge film 13 , and positive charge is induced. Therefore, even when the p-well layer 33 or the pixel isolation layer 28 configured of the p-type semiconductor region is formed with a low p-type impurity concentration, an effect of a function of isolating the pixels 9 or curbing a dark current can be sufficiently exhibited.
  • FIG. 6 is a diagram illustrating a planar layout of the substrate 2 according to the modification example.
  • portions corresponding to FIG. 2 are denoted by the same reference signs, and duplicate description will be omitted.
  • a distance d 1 between the corner portion 43 a and the corner portion 43 c and a distance d 2 between the corner portion 43 b and the corner portion 44 d located at diagonal directions with respect to respective directions in which the groove portions 30 extend among the four corner portions 43 a, 43 b, 43 c, and 44 d of the intersection portion 32 are set to be equal to or smaller than predetermined value times a width d 0 of the groove portion 30 .
  • the predetermined value times for example, is preferably 2.5 times, more preferably 1.4 times, and most preferably 1.0 times.
  • lower limit values of the distances d 1 and d 2 are preferably larger than 0 times the width d 0 .
  • the distances d 1 and d 2 may be set to a predetermined distance or less in addition to setting the distances d 1 and d 2 to predetermined value times the width d 0 , or instead of setting the distances d 1 and d 2 to predetermined value times the width d 0 .
  • the predetermined distance is, for example, preferably 250 nm, more preferably 150 nm, and most preferably 50 nm. When such an upper limit value is set, lower limit values of the distances d 1 and d 2 are preferably larger than 0 nm.
  • the PVD method or the CVD method must be performed for a long time when the second fixed charge film 14 is formed in order to close the open end of the intersection portion 32 by the second fixed charge film 14 as illustrated in FIG. 2 , which is likely to increase a film thickness of the second fixed charge film 14 so that the second fixed charge film 14 gets taller as illustrated in FIG. 7 .
  • the solid-state imaging device 1 according to the modification example, at least one of setting the distances d 1 and d 2 to be equal to or smaller than 2.5 times of the width d 0 and setting the distances d 1 and d 2 to 250 nm or less is performed. Therefore, the second fixed charge film 14 can be lower and optical color mixing can be curbed. Further, it is possible to increase the opening area of the pixel 9 and the volume of the photoelectric conversion portion 24 , and to improve the sensitivity.
  • the corner portions 43 a, 43 b, 43 c, and 44 d come into contact with each other.
  • the distances d 1 and d 2 are made larger than 0 nm. Therefore, the corner portions 43 a, 43 b, 43 c, and 44 d do not come into contact with each other.
  • At least one of the four corner portions 43 a, 43 b, 43 c, and 44 d of the intersection portion 32 may be rounded in an arc shape when viewed from the incidence side of the light, and a radius of curvature R of the arc may be set to a predetermined value or less.
  • the predetermined value for example, 20 nm is preferable, 10 nm or less is more preferable, and 5 nm or less is most preferable.
  • a method of measuring the radius of curvature R for example, it is possible to use a method of fitting approximate curves of arcs having various radii to measured values of the shapes of the corner portions 43 a, 43 b, 43 c, and 44 d using the least squares method.
  • a lower limit value of the radius of curvature R is, for example, preferably 1 nm or more, more preferably 2 nm or more, and most preferably 3 nm or more.
  • the radius of curvature R is larger than 20 nm, setting the distances d 1 and d 2 to be equal to or smaller than 2.5 times the width d 0 or setting the distances d 1 and d 2 to 250 nm or less is likely to be difficult. Further, there is a possibility of the opening area of the pixel 9 and the volume of the photoelectric conversion portion 24 being reduced and the sensitivity being lowered. On the other hand, in the solid-state imaging device 1 according to the modification example, the radius of curvature R of the corner portions 43 a, 43 b, 43 c, and 44 d is set to 20 nm or less.
  • the radius of curvature R is set to 1 nm or more. Therefore, since the difficulty of formation of the corner portions 43 a, 43 b, 43 c, and 44 d can be reduced, and the number of steps of forming the intersection portion 32 can be reduced, an increase in manufacturing cost can be curbed.
  • a convex portion 44 protruding to the inner side of the intersection portion 32 may be formed in at least one of the four corner portions 43 a, 43 b, 43 c, and 44 d of the intersection portion 32 , as illustrated in FIGS. 8A, 8B, 8C, 8D, 8E, 9A, 9B, 9C, 9D, 9E, 10A, 10B, 10C, 10D, 10E, 11A, 11B, 11C, 11D, 11E, 12 , and 13 .
  • FIGS. 8A to 8E illustrate an example in which the convex portion 44 has an isosceles triangle shape with protruding vertices.
  • FIGS. 9A to 9E illustrate an example in which the convex portion 44 has an elliptical shape in which one end of a long axis protrudes.
  • FIGS. 10A to 10E illustrate an example in which the convex portion 44 has a perfect circular shape. Further, FIGS.
  • FIGS. 8A, 9A, 10A, and 11A illustrate an example in which convex portions 44 are provided on all of the four corner portions 43 a, 43 b, 43 c, and 44 d.
  • FIGS. 8B, 9B, 10B, and 11B illustrate an example in which the convex portions 44 are provided only on the three corner portions 43 a, 43 c, and 44 d.
  • FIGS. 8C, 8D, 9C, 9D, 10C, 10D, 11C, and 11D illustrate an example in which the convex portion 44 is provided only in two corner portions 43 a and 43 c or two corner portions 43 a and 43 d among the four corner portions 43 a, 43 b, 43 c, and 44 d.
  • FIGS. 8E, 9E, 10E, and 11E illustrate an example in which the convex portion 44 is provided only on one corner portion 43 a.
  • FIGS. 12 and 13 illustrate an example in which the arrangement of the convex portions 44 of the four corner portions 43 a, 43 b, 43 c, and 43 d is asymmetric.
  • the distances d 1 and d 2 cannot be 1.4 times or less the width d 0 .
  • the distances d 1 and d 2 can be shortened, and the distances d 1 and d 2 can be 1.4 times or less the width d 0 .
  • the solid-state imaging device 1 can be used for the pixel 9 having a square pixel structure, a double pixel structure, a quadruple pixel structure, and a rectangular pixel structure, as illustrated in FIGS. 14A, 14B, 14C, and 14D , for example.
  • the solid-state imaging device 1 can also be used for the intersection portion 32 at a center of the quadruple pixel structure.
  • the wiring layer 22 and the support substrate 23 is formed as illustrated in FIG. 5B , a TEOS layer 45 , a BARC layer 46 , and a photoresist layer 47 are stacked in this order on the back surface S 3 side of the substrate 2 as illustrated in FIGS. 15A and 15B .
  • a resist pattern 48 having an opening corresponding to the groove portion 30 extending in the Y direction is formed with respect to the photoresist layer 47 , as illustrated in FIGS. 15C and 15D .
  • the BARC layer 46 and the TEOS layer 45 are etched via the resist pattern 48 , and then the photoresist layer 47 and the BARC layer 46 are removed so that the hard mask 49 having an opening at the portion corresponding to the groove portion 30 extending in the Y direction is formed, as illustrated in FIGS. 15E and 15F .
  • the BARC layer 50 and the photoresist layer 51 are stacked in this order on the hard mask 49 , as illustrated in FIGS. 15G and 15H .
  • a V-shaped groove portion 52 is formed in the BARC layer 50 .
  • exposure and development are performed on the photoresist layer 51 through the mask having the opening at the portion corresponding to the groove portion 30 extending in the X direction. Accordingly, a resist pattern 53 having openings corresponding to the groove portion 30 extending in the X direction is formed with respect to the photoresist layer 51 , as illustrated in FIGS. 15I and 15J .
  • etching is performed on the BARC layer 50 and the TEOS layer 45 via the resist pattern 53 and then, the photoresist layer 51 and the BARC layer 50 are removed, so that the hard mask 54 having openings is formed at the portion corresponding to the groove portion 30 extending in the X direction, in addition to the portion corresponding to the groove portion 30 extending in the Y direction, as illustrated in FIGS. 15K and 15L . That is, as the hard mask 54 , a mask having openings is formed at portions corresponding to all the groove portions 30 extending in both the X and Y directions go straight to each other.
  • the substrate 2 is etched through the formed hard mask 54 so that the groove portion 30 extending in both the X direction and the Y direction is formed on the substrate 2 , as illustrated in FIGS. 15M and 15N . Accordingly, the intersection portion 32 in which the corner portions 43 a, 43 b, 43 c, and 43 d are not rounded is formed.
  • the corner portions 56 a, 56 b, 56 c, and 56 d of the resist pattern 55 corresponding to the corner portions 43 a, 43 b, 43 c and 43 d of the intersection portion 32 are rounded, as illustrated in FIGS. 16A and 16B . Therefore, when the corner portions 56 a, 56 b, 56 c, and 56 d are rounded, the corner portions 58 a, 58 b, 58 c, and 58 d of the hard mask 57 are also rounded as illustrated in FIGS. 16C and 16D , and the corner portions 43 a, 43 b, 43 c, and 43 d of the intersection portion 32 are also rounded as illustrated in FIGS. 16E and 16F .
  • the TEOS layer 45 , the BARC layer 46 , and the photoresist layer 47 are stacked in this order on the back surface S 3 side of the substrate 2 , and then exposure and development are performed on the photoresist layer 47 through the mask having the opening at the portion corresponding to the groove portion 30 extending in the Y direction, as illustrated in FIG. 15A .
  • a mask having openings having a narrowed width at a portion corresponding to a central position of the intersection portion 32 is used as the mask.
  • the resist pattern 48 that is provided at the portion corresponding to the groove portion 30 extending in the Y direction and has an opening having a narrowed width at the portion corresponding to the central position of the intersection portion 32 is formed with respect to the photoresist layer 47 , as illustrated in FIGS. 17A and 17B .
  • the BARC layer 46 and the TEOS layer 45 are etched via the resist pattern 48 and then, the photoresist layer 47 and the BARC layer 46 are removed so that the hard mask 49 in which an opening is provided at the portion corresponding to the groove portion 30 extending in the Y direction and a width at the portion corresponding to the central position of the intersection portion 32 in the opening is narrow is formed as illustrated in FIGS. 17C and 17D .
  • the BARC layer 50 and the photoresist layer 51 are stacked in this order on the hard mask 49 , as illustrated in FIG. 15D .
  • the V-shaped groove portion 52 is formed in the BARC layer 50 .
  • exposure and development are performed on the photoresist layer 51 through the mask having the opening at the portion corresponding to the groove portion 30 extending in the X direction.
  • a mask having openings having a narrowed width at a portion corresponding to the central position of the intersection portion 32 is used as the mask.
  • the resist pattern 53 that is provided at the portion corresponding to the groove portion 30 extending in the X direction and has an opening having a narrowed width at the portion corresponding to the central position of the intersection portion 32 is formed with respect to the photoresist layer 51 , as illustrated in FIGS. 17E and 17F .
  • etching is performed on the BARC layer 50 and the TEOS layer 45 via the resist pattern 53 and then, the photoresist layer 51 and the BARC layer 50 are removed so that the hard mask 54 having openings is formed at the portion corresponding to the groove portion 30 extending in the X direction, in addition to the portion corresponding to the groove portion 30 extending in the Y direction, as illustrated in FIGS. 17G and 17H .
  • FIGS. 17I and 17J an isosceles triangle shaped convex portion 44 having a protruding apex is shown as an example.
  • FIG. 18 is a diagram illustrating a planar layout of the second fixed charge film 14 according to the modification example.
  • portions corresponding to FIG. 3 are denoted by the same reference signs, and duplicate description will be omitted.
  • the solid-state imaging device 1 in the solid-state imaging device 1 according to the modification example, at least some of the open ends of the plurality of intersection portions 32 in which the groove portions 30 intersect each other are not closed by the second fixed charge film 14 . That is, open ends 38 of the groove portions 30 (open ends of the straight portions 31 ) other than the intersection portions 32 are all closed by the second fixed charge film 14 with the void 35 left inside the straight portions 31 . However, closing of open ends 39 of the intersection portion 32 by the second fixed charge film 14 is performed only on some of the open ends or is not performed on any of the open ends.
  • the second fixed charge film 14 At the open ends 39 not closed by the second fixed charge film 14 , a part of the second fixed charge film 14 enters the groove portion 30 so that a sidewall surface 40 on the open end side of the groove portion 30 is covered, as illustrated in FIG. 19 .
  • a film thickness of the second fixed charge film 14 which covers the sidewall surface 40 on the open end 39 side of the groove portion 30 is also larger on the open end 39 side of the groove portion 30 than on the back side (bottom surface side). Accordingly, the second fixed charge film 14 has a shape protruding toward an inner wall surface of the groove portion 30 from the opening at a center in a width direction of the open end 39 , and the open end 39 of the groove portion 30 is narrowed by the second fixed charge film 14 .
  • the open end 39 narrowed by the second fixed charge film 14 is closed by the insulation film 15 with the void 35 left inside the groove portion 30 .
  • a maximum width of the open end 39 of the intersection portion 32 is larger than a maximum width of the open end of the straight portion 31 . Therefore, it is necessary to reduce all groove portion widths of the groove portion 30 in order to close all the open ends 39 of the intersection portion 32 with the second fixed charge film 14 . However, when all the groove portion widths of the groove portions 30 are reduced, the number of steps of forming the groove portions 30 may increase, and the manufacturing cost may increase.
  • the solid-state imaging device 1 in the solid-state imaging device 1 according to the modification example, at least some of the open ends 39 of the plurality of intersection portions 32 in which the groove portions 30 intersect each other are not closed by the second fixed charge film 14 . Therefore, it is not necessary to reduce all the groove portion widths of the groove portions 30 , and it is possible to curb an increase in the number of steps of forming the groove portions 30 , and to curb the increase in the manufacturing cost.
  • FIGS. 20, 21A and 21B are cross-sectional configuration views of main parts of the solid-state imaging device 1 of the embodiment.
  • portions corresponding to FIG. 2 are denoted by the same reference signs and duplicate description will be omitted.
  • a configuration of the element isolation portion 29 differs from that of the solid-state imaging device 1 of the first embodiment.
  • the open end 41 of the groove portion 30 has an overhang shape in which the open end 41 of the groove portion 30 is narrower than the inside of the groove portion 30 at least on the open end side of the groove portion 30 , as illustrated in FIG. 20 .
  • a cross-sectional shape of the groove portion 30 when the groove portion 30 is cut in a depth direction may be, for example, an elliptical shape in which an opening side and a back side are narrow and a center portion side is wide, and may be a shape with a constant width in which only an opening side is narrow and a center portion and a back side are wide (a shape in which a triangle and a square are combined).
  • the first fixed charge film 13 closes the open end 41 having the overhang shape of the groove portion 30 so that the void 35 is left inside the groove portion 30 .
  • the thickness of the first fixed charge film 13 is set to, for example, a thickness of about half the groove portion width of the open end 41 so that the entire inside of the groove portion 30 is not completely filled with the first fixed charge film 13 and the open end 41 of the groove portion 30 is closed. For example, when the groove portion width of the open end 41 is about 30 nm, the thickness of the first fixed charge film 13 is about 15 nm.
  • the first fixed charge film 13 and the second fixed charge film 14 can be formed of the same materials as the materials of the first fixed charge film 13 and the second fixed charge film 14 used in the first embodiment.
  • FIGS. 21A and 21B illustrate processing of manufacturing the solid-state imaging device 1 of the second embodiment. Since the steps up to the step of adhering the support substrate 23 are the same as those of the first embodiment, duplicate description will be omitted. After the support substrate 23 is adhered, selective etching is performed in the depth direction from the back surface S 3 side of the substrate 2 (a direction from the back surface S 3 to the front surface S 2 ) at the boundary of each pixel 9 of the substrate 2 , so that, the groove portion 30 having a desired depth is formed, as illustrated in FIG. 21A .
  • a method for forming the groove portion 30 for example, a method of providing a hard mask (not illustrated) having a desired opening on the back surface S 3 of the substrate 2 and performing etching through this hard mask can be adopted.
  • an etching condition is set so that bowing occurs and the open end 41 of the groove portion 30 has the overhang shape.
  • the etching condition is optimized such that the open end 41 of the groove portion 30 narrower than the inside of the groove portion 30 can be formed.
  • the groove portion 30 illustrated in FIG. 20 is closed only by the first fixed charge film 13 with the void 35 left inside the groove portion 30 .
  • the internal space of the void 35 is formed in a grid pattern extending along the groove portion 30 , as in FIG. 3 .
  • the hard mask used for processing of the groove portion 30 is removed.
  • the sidewall surface and the bottom surface of the groove portion 30 and the entirety on the back surface S 3 side (the entirety on the light reception surface side) of the substrate 2 are continuously covered using the ALD method or the CVD method, and the first fixed charge film 13 is formed so that the open end 41 of the groove portion 30 is closed as illustrated in FIG. 21B .
  • a film forming condition is set so that the open end 41 side of the groove portion 30 is closed before the inside of the groove portion 30 is completely embedded by the first fixed charge film 13 .
  • the film forming condition is optimized such that the element isolation portion 29 having the void 35 can be formed. Accordingly, the open end 41 of the groove portion 30 illustrated in FIG. 20 is closed by the first fixed charge film 13 with the void 35 left inside the groove portion 30 .
  • the internal space of the void 35 is formed in a grid pattern extending along the groove portion
  • the solid-state imaging device 1 of the second embodiment illustrated in FIG. 20 is completed through the same step as that in the first embodiment.
  • the open end 41 of the groove portion 30 has the overhang shape in which the open end 41 is narrower than the inside of the groove portion 30 . Therefore, the groove portion 30 provided between the adjacent photoelectric conversion portions 24 can be closed by the first fixed charge film 13 with the void 35 left more reliably inside the groove portion 30 .
  • the refractive index of the substrate 2 for example, 3.9 in the case of silicon (Si)
  • the refractive index of the void 35 for example, 1.0 in the case of being filled with air
  • FIG. 22 is a cross-sectional configuration diagram of a solid-state imaging device 1 according to a modification example of the second embodiment.
  • portions corresponding to FIG. 20 are denoted by the same reference signs, and duplicate description will be omitted.
  • the solid-state imaging device 1 according to the modification example differs from that according to the second embodiment in that the second fixed charge film 14 is omitted. This can reduce the number of steps of forming the second fixed charge film 14 and manufacturing cost.
  • the present disclosure can also be applied to a back-illuminated CCD-type solid-state imaging device.
  • the element isolation portion 29 between the photoelectric conversion portions 24 is formed with the void 35 left in the groove portion 30 , such that the same effect as that in the first and second embodiments can be obtained.
  • the present disclosure can also be applied to a case in which a positive charge (hole) is used as the signal charges.
  • a material having positive fixed charge may be used as the first fixed charge film 13 and the second fixed charge film 14 , and a p-type region and n-type region in the substrate 2 may be configured in reverse. That is, a material having the same charge as the signal charge as fixed charge may be used for the first fixed charge film 13 and the second fixed charge film 14 .
  • the present disclosure is not limited to a solid-state imaging device that detects distribution of an amount of incident light of visible light and captures an image like the solid-state imaging devices 1 according to the first and second embodiments.
  • the present disclosure can be applied to a solid-state imaging device that captures distribution of an incidence amount of infrared rays, X-rays, particles, or the like as an image.
  • the present disclosure can also be applied to all solid-state imaging devices (physical quantity distribution detection devices) such as fingerprint detection sensors that detect distribution of other physical quantities such as pressure or capacitance and capture an image.
  • the present disclosure is not limited to a solid-state imaging device that scans each pixel 9 of the pixel region 3 in order in units of rows and reads a pixel signal from each pixel 9 , like the solid-state imaging devices 1 according to the first and second embodiments.
  • the present disclosure can also be applied to an XY address type solid-state imaging device that selects any pixel 9 in units of pixels and reads a signal from the selected pixel 9 in units of pixels.
  • the present disclosure is not limited to the solid-state imaging device in which an interface (light reception surface side interface) of the p-type semiconductor region 25 above the n-type semiconductor regions 27 is flat, as in the solid-state imaging device 1 according to the first and second embodiments.
  • the present disclosure can also be applied to a solid-state imaging device having a reflection prevention portion 42 having a so-called moth-eye structure in which an inverted pyramid-shaped depressed portion is formed so that an interface (an interface on the light reception surface side) of the p-type semiconductor region 25 prevents reflection of incident light, as illustrated in FIG. 23 .
  • a rectangular depressed portion may be provided instead of the inverted pyramid-shaped depressed portion of FIG. 23 , and the inside of the depressed portion may be filled with the first fixed charge film 13 , as illustrated in FIG. 25 .
  • the second fixed charge film 14 may be omitted, and the open end of the groove portion 30 may be closed by the insulation film 15 .
  • the present disclosure is not limited to the solid-state imaging device in which an interface (light reception surface side interface) of the p-type semiconductor region 25 above the n-type semiconductor region 27 is flat, as in the solid-state imaging device 1 according to the first and second embodiments.
  • the present disclosure can also be applied to a solid-state imaging device including the element isolation portion 29 penetrating the substrate 2 in a part (for example, an edge) of the pixel region, and the light shielding film 16 exposed on the front surface S 2 side of the substrate 2 in the element isolation portion 29 , as illustrated in FIG. 25 .
  • FIG. 26 is a schematic configuration diagram of the electronic apparatus 100 according to the third embodiment of the present disclosure.
  • the electronic apparatus 100 includes a solid-state imaging device 101 , an optical lens 102 , a shutter device 103 , a drive circuit 104 , and a signal processing circuit 105 .
  • the electronic apparatus 100 of the third embodiment shows an embodiment in which the solid-state imaging device 1 according to the first embodiment of the present disclosure is used for electronic apparatuses (for example, a camera) as the solid-state imaging device 101 .
  • the optical lens 102 forms an image of image light (the incident light 106 ) from the subject on the imaging surface of the solid-state imaging device 101 . Accordingly, the signal charge is accumulated in the solid-state imaging device 101 for a certain period of time.
  • the shutter device 103 controls a light irradiation period and a light shielding period of the solid-state imaging device 101 .
  • the drive circuit 104 supplies a drive signal for controlling a transfer operation of the solid-state imaging device 101 and a shutter operation of the shutter device 103 . Signal transfer of the solid-state imaging device 101 is performed by the drive signal (timing signal) supplied from the drive circuit 104 .
  • the signal processing circuit 105 performs various signal processing on a signal (pixel signal) output from the solid-state imaging device 101 .
  • a video signal subjected to signal processing is stored in a storage medium such as a memory or output to a monitor.
  • the electronic apparatus 100 to which the solid-state imaging device 1 can be applied is not limited to a camera, but can also be applied to another electronic apparatus.
  • the solid-state imaging device 1 may be applied to an imaging device such as a camera module for mobile devices such as mobile phones.
  • the solid-state imaging device 1 according to the first embodiment is used for the electronic apparatus as the solid-state imaging device 101 in the third embodiment, but other configurations may be adopted.
  • the solid-state imaging device 1 according to the second embodiment or the solid-state imaging device 1 according to the modification example may be used for electronic apparatuses.
  • the present technology can have the following configurations.
  • a solid-state imaging device including:
  • a fixed charge film which covers a sidewall surface and a bottom surface of the groove portions, and a light reception surface side of the substrate and which contains at least one of hafnium, aluminum, zirconium, tantalum, and titanium, wherein
  • the fixed charge film includes a first fixed charge film and a second fixed charge film
  • the first fixed charge film continuously covers the sidewall surface and the bottom surface of the groove portion and the entirety on the light reception surface side of the substrate such that the sidewall surface and the bottom surface forms, inside the groove portion, a groove-shaped space surrounded by the first fixed charge film
  • the second fixed charge film closes the open end of the groove portion with a void left inside the groove portion and continuously covers the entirety on the light reception surface side of the first fixed charge film.
  • the solid-state imaging device according to any one of (1) to (6), further including an insulation film which continuously covers the entirety of the fixed charge film on the light reception surface side and which contains at least one of silicon oxide, silicon nitride, and silicon oxynitride.
  • An electronic apparatus including:
  • a solid-state imaging device including a substrate, a plurality of photoelectric conversion portions formed on the substrate, groove portions provided between the adjacent photoelectric conversion portions, and a fixed charge film which covers a sidewall surface and a bottom surface of the groove portions, and a light reception surface side of the substrate and which contains at least one of hafnium, aluminum, zirconium, tantalum, and titanium;
  • an optical lens that forms an image of image light from a subject on an imaging surface of the solid-state imaging device

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