US20210074749A1 - Pixel - Google Patents
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- US20210074749A1 US20210074749A1 US17/011,900 US202017011900A US2021074749A1 US 20210074749 A1 US20210074749 A1 US 20210074749A1 US 202017011900 A US202017011900 A US 202017011900A US 2021074749 A1 US2021074749 A1 US 2021074749A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
- H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H—ELECTRICITY
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
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- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
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- H—ELECTRICITY
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
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Definitions
- the present disclosure relates generally to electronic circuits, and more specifically to electronic circuits, for example pixels, comprising photodiodes and transistors.
- An image sensor is a photosensitive electronic component used to convert electromagnetic radiation (UV, visible or IR) emitted by a scene into analog electric signals. These signals are next amplified, then digitized by one or several analog-digital converters and lastly processed in order to obtain a digital image.
- electromagnetic radiation UV, visible or IR
- the image sensor is made up of a plurality of pixels, each pixel generally comprising a photodiode and transistors. Each pixel supplies an analog signal for example corresponding to a pixel of the finished digital image.
- One embodiment addresses all or some of the drawbacks of known pixels.
- One embodiment provides a pixel comprising a photodiode and first and second transistors, the first and second transistors being coupled in series, one of the first and second transistors being a P channel transistor and the other being an N channel transistor.
- the second transistor is coupled in parallel with a third transistor of the opposite channel type from the channel type of the second transistor.
- control signals of the second and third transistors are such that the second and third transistors are on at the same times.
- the gate of the first transistor is coupled to one of the terminals of the photodiode by a fourth transistor.
- the fourth transistor has the same channel type as the first transistor.
- the gate of the first transistor is coupled to a node for applying a reference voltage by a fifth transistor.
- the fifth transistor has the same channel type as the first transistor.
- the first transistor is coupled between a node for applying a reference voltage and a central node
- the second transistor is coupled between the central node and an output node of the pixel.
- the photodiode is at least partially surrounded by isolated conductive trenches.
- certain isolated conductive trenches extend over at least part of the height of the transistors.
- the pixel comprises a first stage comprising the photodiode and a second stage comprising the transistors, the first and second stages being attached to one another.
- One embodiment provides an electronic device comprising at least one pixel as previously described.
- Another embodiment provides a method for manufacturing a pixel as previously described, the method comprising a step for manufacturing a first stage comprising the photodiode, attaching a second stage and forming transistors in the second stage.
- the method comprises forming cavities extending over the height of the transistors and at least partially over the height of the photodiode, at least some of the cavities being partially filled with conductive material and partially filled with insulating material.
- some of the cavities are completely filled with conductive material.
- FIG. 1 shows an exemplary pixel comprising a photodiode and transistors
- FIG. 2 shows characteristic variations of the pixel of FIG. 1 ;
- FIG. 3 shows an embodiment of a pixel comprising a photodiode and transistors
- FIG. 4 shows characteristic variations of the pixel of FIG. 3 ;
- FIG. 5 shows characteristic variations of another part of the pixel of FIG. 3 ;
- FIG. 6 shows another embodiment of a pixel comprising a photodiode and transistors
- FIG. 7 shows characteristic variations of the pixel of FIG. 6 ;
- FIG. 8 is a schematic cross-sectional view of an example of part of the pixel of FIG. 3 or FIG. 6 ;
- FIGS. 9A-C show steps of an exemplary a method for manufacturing the embodiment of FIG. 8 ;
- FIGS. 10A-B show other steps of an exemplary manufacturing method of the embodiment of FIG. 8 ;
- FIGS. 11A-B shows other steps of an exemplary manufacturing method of the embodiment of FIG. 8 ;
- FIG. 12 is a schematic cross-sectional view of another example of part of the pixel of FIG. 3 or FIG. 6 ;
- FIG. 13 is a schematic diagram of an electronic device, for example an image sensor.
- FIG. 1 shows an exemplary circuit comprising a photodiode. More specifically, FIG. 1 shows an exemplary pixel 100 having a 4 T structure, that is to say, a pixel comprising an electronic circuit with four transistors. It may for example be a pixel of an image sensor.
- the pixel 100 comprises a photodiode 102 .
- the photodiode 102 receives radiation from a scene and transforms it into electric charges.
- the charges in question are holes.
- the photodiode 102 is coupled, preferably connected, by its cathode, to a node for applying a reference voltage, for example a voltage VNWELL.
- the anode of the photodiode 102 is coupled to a node N 1 by means of the conduction terminals (source and drain) of a transfer transistor 104 .
- the transistor 104 in this example is a P channel MOS transistor.
- the gate of the transistor 104 receives a control signal TG.
- the signal TG is for example a signal alternating between a high value, for example about 3.5 V, and a low value, for example about 0 V.
- the transfer transistor 104 makes it possible to transfer the electronic charges generated by the photodiode 102 onto the node N 1 .
- the node N 1 is coupled to a node for applying a voltage VRST by means of a reset transistor 106 (transistor RESET).
- the transistor 106 in this example is a P channel MOS transistor.
- the gate of the transistor 106 receives a control signal VR.
- the signal VR is for example a signal able to switch between a high value, for example about 3.5 V, and a low value, for example about 0 V.
- the substrate of the transistor 106 can be biased by the voltage VNWELL.
- the voltage VNWELL is for example substantially equal to 2.5 V.
- the voltage VRST is, in this example, approximately equal to 0.5 V.
- the reset transistor 106 makes it possible to reset the voltage VSF on the node N 1 to a value V 0 .
- the voltage VSF on the node N 1 is equal to a value V 0 that depends on the voltage VRST, for example greater than the voltage VRST.
- the node N 1 is also coupled to a node for applying a reference voltage, for example the voltage VNWELL, by means of a capacitor 108 SN.
- the capacitor 108 for example makes it possible to store the electric charges coming from the photodiode 102 .
- the node N 1 is also coupled, preferably connected, to the gate of a transistor 110 of the common drain type (Source follower).
- the transistor 110 is coupled, preferably connected, in series with a read transistor 112 , and for example a current source 114 .
- the current source represents a reading row or column of a pixel matrix. More specifically, the transistor 110 is coupled by its drain and source terminals between a node for applying a reference voltage VRT and a node N 2 , the transistor 112 is coupled between the node N 2 and a node N 3 .
- the current source 114 is for example coupled between the node N 3 and a node for applying a reference voltage VDD.
- the transistors 110 and 112 in this example are P channel MOS transistors.
- the transistor 112 receives a control voltage VRS on its gate.
- the signal VRS is for example a signal able to switch between a high value, for example about 3.5 V, and a low value, for example about 0 V.
- the substrates of the transistors 110 and 112 are for example biased by the voltage VNWELL.
- the transistor 110 makes it possible to obtain, at the node N 2 , a voltage representative of the quantity of charges located on the node N 1 . More specifically, the voltage on the node N 2 is substantially equal to the value of the voltage VSF multiplied by the gain of the transistor 110 plus an offset value Voffset.
- the value Voffset is the voltage measured at the node N 2 when the voltage VSF is nil.
- the transistor 112 makes it possible to read the representative voltage on the reading row or column. More specifically, the transistor 112 makes it possible to choose, among a matrix of pixels similar to the pixel 100 , which pixel must be read.
- the node N 3 is thus an output node of the pixel 100 .
- the output signal of the pixel is a representative value of the radiation received by the photodiode.
- the output signal is the value on the node N 3 when the pixel is read.
- all of the transistors of the pixel 100 are transistors having a same type of channel, for example P channel transistors.
- the voltage VSF on the node N 1 is reset to the value V 0 depending on the voltage VRST.
- the transistor 104 is turned on.
- the charges generated by the photodiode 102 move toward the node N 1 and cause the voltage VSF to vary from the value V 0 to the reset.
- a voltage representative of the number of charges on the node N 1 is thus obtained on the level of the node N 2 and can be read by the image sensor at the output node N 3 , when the transistor 112 is on.
- the read transistor 112 preferably minimizes the leak to pass when the transistor 112 is off, but the transistor 112 preferably has a gain close to 1 when it is on, such that the voltage on the node N 3 is substantially equal to the voltage on the node N 2 .
- the transistor 112 is strongly reversed and works in the linear zone.
- FIG. 2 shows characteristic variations of the circuit of FIG. 1 .
- the transistor 104 is considered to be in an ideal off state, that is to say, without leaks. More specifically, FIG. 2 shows, as a function of the value (in volts) of the voltage VRST:
- the gain between the node N 3 and the node for applying the voltage VRST that is to say, the gain of the reading chain, for example in the case where the transistor 104 is off, preferably perfectly off (curve 154 ).
- the curve 152 is substantially parallel to the curve 150 .
- This value range is for example between about 0.8 V and about 1.8.
- the gain is substantially constant and greater than 0.9, that is to say, close to 1.
- the gain is substantially equal to 0.75 V.
- the reset voltage VRST should be part of this value range, and for example greater than the value 0.8.
- FIG. 3 shows an embodiment of a circuit comprising a photodiode. More specifically, FIG. 3 shows a pixel 170 .
- the pixel 170 is for example comprised in an electronic device, for example an image sensor.
- the electronic device for example comprises at least one pixel 170 , preferably a matrix of pixels 170 .
- the pixel corresponds to the unit of an image, for example in a sensor.
- An image sensor comprises a plurality of substantially identical pixels each comprising the same components.
- the elements described in FIG. 3 are components of the described pixel and are reproduced in each pixel of an image sensor.
- the pixel 170 comprises the elements of the pixel 100 of FIG. 1 , referenced in the same way, with the exception of the transistor 112 , which is replaced by an assembly 172 .
- the charges generated in the pixel 170 are holes.
- the pixel 170 comprises the photodiode 102 .
- the photodiode 102 receives, like in the example of FIG. 1 , radiation from a scene and transforms it into electric charges.
- the photodiode 102 is coupled, preferably connected, by its cathode, to a node for applying a reference voltage, for example the voltage VNWELL.
- the anode of the photodiode 102 is coupled to the node N 1 by means of the conduction terminals (source and drain) of the transfer transistor 104 .
- the transistor 104 in this example is a P channel MOS transistor.
- the gate of the transistor 104 receives the control signal TG previously described.
- the transfer transistor 104 makes it possible to transfer the electronic charges generated by the photodiode 102 onto the node N 1 .
- the node N 1 is coupled to a node for applying a voltage VRST by means of the reset transistor 106 .
- the transistor 106 in this example is a P channel MOS transistor.
- the gate of the transistor 106 receives a control signal VR, previously described.
- the substrate of the transistor 106 can be biased by a voltage VNWELL, previously described.
- the reset transistor 106 makes it possible to reset the voltage VSF on the node N 1 to a value V 0 .
- the voltage VSF on the node N 1 is equal to a value V 0 that depends on the voltage VRST, for example greater than the voltage VRST.
- the node N 1 is also coupled to a node for applying a reference voltage, for example the voltage VNWELL, by means of the capacitor 108 SN.
- the capacitor 108 for example makes it possible to store the electric charges coming from the photodiode 102 .
- the node N 1 is also coupled, preferably connected, to the gate of the transistor 110 of the common drain type (source follower).
- the transistor 110 is coupled, preferably connected, in series with the assembly 172 , and for example a current source 114 .
- the current source represents a reading row or column of a pixel matrix. More specifically, the transistor 110 is coupled by its drain and source terminals between a node for applying a reference voltage VRT and a node N 2 , the assembly 172 is coupled between the node N 2 and a node N 3 .
- the current source 114 is for example coupled between the node N 3 and a node for applying a reference voltage VDD.
- the transistor 110 is a P channel MOS transistor.
- the substrate of the transistor 110 is for example biased by the voltage VNWELL.
- the transistor 110 makes it possible to obtain, at the node N 2 , a voltage representative of the quantity of charges located on the node N 1 . More specifically, the voltage on the node N 2 is substantially equal to the value of the voltage VSF multiplied by the gain of the transistor 110 plus the offset value Voffset.
- the assembly 172 makes it possible to read the representative voltage on the reading row or column. More specifically, the assembly 172 makes it possible to choose, among a matrix of pixels similar to the pixel 100 , the pixel to be read.
- the node N 3 is thus an output node of the pixel 100 .
- the output signal of the pixel is a representative value of the radiation received by the photodiode.
- the output signal is the value on the node N 3 when the pixel is read.
- the assembly 172 comprises two transistors, a transistor 174 and a transistor 176 .
- the transistors 174 and 176 are coupled, preferably connected, in parallel by their sources and drains between the nodes N 2 and N 3 . More specifically, in the example of FIG. 3 , the source of the transistor 174 is connected to the drain of the transistor 176 . Likewise, the drain of the transistor 174 is connected to the source of the transistor 176 . The drain of the transistor 176 and the source of the transistor 174 are coupled, preferably connected, to the node N 3 . The source of the transistor 176 and the drain of the transistor 174 are coupled, preferably connected, to the node N 2 .
- the transistor 174 in this example is a P channel MOS transistor.
- the gate of the transistor 174 receives the control signal VRS.
- the substrate of the transistor 174 is biased by the voltage VNWELL.
- the transistor 176 is an N channel MOS transistor.
- the gate of the transistor 176 receives a control signal VRS*.
- the control signal VRS* is the signal opposite the signal VRS.
- the control signal VRS* is equal to a low value, and vice versa.
- the control signal VRS is equal to a non-nil and positive value
- the control signal VRS* is nil
- the signal VRS* is equal to a non-nil and positive value.
- the substrate of the transistor 176 is biased by a voltage VPWELL.
- the voltage VPWELL is for example approximately equal to 0.
- all of the transistors of the pixel 170 have the same channel type, for example P, with the exception of the transistor 176 .
- the pixel 170 is an integrated circuit.
- the transistors 104 , 106 , 110 , 174 and 176 , as well as the photodiode 102 and the capacitor 108 , are preferably formed in the integrated circuit.
- the pixel 170 therefore comprises a so-called common drain transistor 110 (source follower) coupled, preferably connected, in series with a read transistor 176 with the opposite channel type relative to that of the so-called common drain transistor 110 .
- the read and common drain transistors are coupled between a node for applying a reference voltage (VRT) and an output node (N 3 ).
- VRT reference voltage
- N 3 output node
- the so-called common drain transistor 110 is a P-channel transistor and the read transistor 176 is an N channel transistor.
- the read transistor 176 is also in parallel with a read transistor 174 with the same channel type as the so-called common drain transistor, in this example the P channel transistor.
- FIG. 4 shows characteristic variations of part of the circuit of FIG. 3 .
- FIG. 4 shows characteristic variations of the assembly 172 .
- FIG. 4 shows, as a function of time (Time (s)):
- curves 202 , 204 , 206 and 208 depend on the value of the input voltage, that is to say, the voltage on node N 2 (curve 200 ).
- the transistors are perfect transistors.
- the curve 202 is substantially parallel, or even substantially equal, to the curve 200 during a first period, then moves away therefrom during a second period.
- the first period for example corresponds, over all of the values considered in FIG. 4 , to the period preceding a moment T 1
- the second period corresponds, over all of the considered values, to the period following the moment T 1 .
- the moment T 1 is substantially equal to 0.82 s, which corresponds to a value V 1 of the voltage on the node N 2 , substantially equal to 0.82 V.
- the gain shown by the curve 206 , is high during the first period, then decreases during the second period. During the first period, the gain is greater than 0.8, or even greater than 0.9, and is therefore close to 1.
- the curve 204 In the case where only the transistor 174 is on, during the first period, the curve 204 is distant from the curve 200 and comes closer thereto. During the second period, the curve 204 is substantially parallel to the curve 200 and is close thereto. Thus, the gain, shown by the curve 208 , is small during the first part and increases until becoming, in the second part, greater than 0.8, or even 0.9, and therefore close to 1.
- the curves 206 and 208 intersect at the moment T 1 , corresponding to the value V 1 of the voltage on the node N 2 .
- the gains are both approximately equal to 0.8.
- the gain of the assembly 172 is higher by going through the transistor 176 .
- the gain of the assembly 172 is higher by going through the transistor 174 .
- the assembly 172 is on, that is to say, the transistors 174 and 176 are both on.
- the control voltages VRS and VRS* being opposite one another, the two transistors become on substantially at the same time.
- the current coming from the node N 2 and passing through the assembly 172 passes through the transistor 174 or 176 having the highest gain.
- the current passes through the transistor 176
- the voltage on the node N 2 is greater than V 1
- the current passes through the transistor 174 .
- the gain of the assembly 172 is therefore always equal to the maximum of the gains of the transistors 174 and 176 .
- the gain of the assembly 172 is always greater than 0.8, mostly greater than 0.9, over the range of values of the voltage on the node N 2 considered in FIG. 4 .
- the value range in which the gain is close to 1 is wider than the value range described in relation with FIGS. 1 and 2 , in which the assembly 172 is related by the transistor 112 .
- FIG. 5 shows characteristic variations of another part of the circuit of FIG. 3 .
- FIG. 5 shows characteristic variations of the pixel 170 , the transistor 104 being considered in an ideal off state, that is to say, without leaks.
- FIG. 5 shows, as a function of the value (in volts) of the voltage VRST:
- FIG. 5 therefore comprises, for the embodiment of FIG. 3 , curves showing the same elements as the curves of FIG. 2 for the example of FIG. 1 .
- the node N 3 is still considered to be the output of the system and the value of the voltage on the node for applying the voltage VRST is the input of the system.
- the curve representing the voltage on the node N 3 comprises a substantially linear part, substantially parallel to the curve 250 showing the input voltage, here the voltage VRST.
- This linear part corresponds to a range of values of the voltage VRST in which the gain is substantially constant at a value greater than 0.9.
- the value range in question extends, in the example of FIG. 5 , between a voltage V 2 equal to about 0.25 V and a voltage V 3 equal to about 1.8 V. In FIG. 2 , this value range extends approximately between 0.8 V and 1.8 V. The value range making it possible to obtain a high gain has therefore been expanded, in particular toward the low voltage values VRST.
- One advantage of the embodiment of FIG. 3 is that it is possible to broaden the value range while adding only one component.
- FIG. 6 shows another embodiment of a circuit comprising a photodiode.
- FIG. 6 shows a pixel 275 , comprising the elements of the pixel 170 , with the exception of the assembly 172 , which, in this embodiment, is replaced by a single transistor 277 .
- the charges generated in the pixel 275 are holes.
- the pixel 275 is for example comprised in an electronic device, for example an image sensor.
- the electronic device for example comprises at least one pixel 275 , preferably a matrix of pixels 275 .
- the pixel corresponds to the unit of an image, for example in a sensor.
- An image sensor comprises a plurality of substantially identical pixels each comprising the same components.
- the elements described in FIG. 6 are components of the described pixel and are reproduced in each pixel of an image sensor.
- the transistor 277 is coupled, preferably connected, between the nodes N 2 and N 3 by its sources and drain.
- the transistor 277 in this example is an N channel MOS transistor.
- the gate of the transistor 277 receives the control signal VRS* previously defined.
- the substrate of the transistor 277 is biased by the voltage VPWELL.
- all of the transistors of the pixel 275 have the same channel type, for example P, with the exception of the transistor 277 .
- the pixel 275 therefore comprises a so-called common drain transistor 110 coupled in series with a read transistor 227 with the opposite channel type relative to that of the so-called common drain transistor, between a node for applying a reference voltage (VRT) and an output node (N 3 ).
- the so-called common drain transistor 110 is a P-channel transistor and the read transistor 277 is an N channel transistor.
- the transistor 277 is not in parallel with a transistor with the opposite channel type (in this case, the P channel).
- FIG. 7 shows characteristic variations of the circuit of FIG. 6 .
- FIG. 7 shows characteristic variations of the pixel 275 , the transistor 104 being considered in an ideal off state, that is to say, without leaks.
- FIG. 7 shows, as a function of the value (in volts) of the voltage VRST:
- FIG. 7 therefore comprises, for the embodiment of FIG. 6 , curves showing the same elements as the curves of FIG. 2 for the example of FIG. 1 and, for the embodiment of FIG. 3 , of FIG. 5 .
- the curve 302 is substantially parallel to the curve 300 .
- This value range is for example between a voltage V 4 equal to about 0.3 V and a voltage V 5 equal to about 1.25 V.
- the gain is substantially constant and greater than 0.8, mostly and greater than 0.9, that is to say, close to 1.
- the curve 302 moves away from the curve 300 .
- the gain is therefore smaller than the gain in the value range, for example less than 0.8.
- the range of values in the case of the embodiment of FIG. 6 is narrower than in the case of the embodiment of FIG. 3 , but includes values lower than that of the value range of the example of FIG. 1 .
- the embodiment of FIG. 6 therefore makes it possible to reset the node N 1 to a value below 0.8 V while keeping a gain greater than 0.8, unlike the example of FIG. 1 .
- FIGS. 8 to 12 show embodiments of pixels.
- the pixels are integrated circuits and comprise at least one P channel transistor and one N channel transistor.
- FIG. 8 is a schematic cross-sectional view of an example of part of the pixel 325 of FIG. 3 or FIG. 6 .
- the pixel 325 comprises two stages: a first stage 327 and a second stage 329 above the first stage 327 .
- the first stage 327 comprises a photodiode 102 .
- the photodiode is for example formed in a P-doped substrate.
- the photodiode 102 is at least partially surrounded by isolated conductive trenches 331 .
- the trenches 331 comprise a conductive core 333 and an insulating sheath 335 .
- the conductive core 333 is for example made from polycrystalline silicon and the insulating sheath is for example made from silicon oxide.
- the insulating sheath covers the partitions and the lower face of the conductive core.
- the sheath preferably also covers at least part of the upper face.
- the conductive core 333 is for example biased so as to form an electromagnetic field.
- the electromagnetic field for example makes it possible to control the path of the charges generated by the photodiode 102 .
- the polarization of the trenches 331 is also suitable for the operation of one type of transistors. This polarization could disrupt the operation of the transistors of the other type.
- the polarization of the trenches 331 is also suitable for the operation of the P channel transistors. It is therefore useful to separate the N channel transistors from the trenches 331 so as to ensure an optimal operation of the N channel transistors.
- the substrate comprising the photodiode 102 and the trenches 331 is covered by an insulating layer 336 .
- the insulating layer 336 extends at least above the photodiodes and trenches 331 .
- the layer 336 is covered by an attachment layer 338 .
- the attachment layer 338 is an insulating layer.
- the second stage covering the first stage 329 , comprises the transistors of the pixel 325 . This for example involves the transistors 104 , 106 , 110 , 174 , 176 or 277 .
- FIG. 8 In the example of FIG. 8 , two MOS transistors are shown: an N channel transistor 337 and a P channel transistor 339 .
- all of the transistors of the pixel are located in the second stage.
- the N channel transistor 337 is represented by N wells 341 forming the source and drain of the transistor 337 .
- the wells 341 are separated by a P well 343 .
- the gate 345 of the transistor 337 is shown by a block located on the upper face of the wells 341 and 343 .
- the P channel transistor 339 is represented by P wells 347 forming the source and drain of the transistor 339 .
- the wells 347 are separated by an N well 349 .
- the gate 351 of the transistor 339 is shown by a block located on the upper face of the wells 347 and 349 .
- the transistors 337 and 339 are separated from one another, and optionally from other components located in the second stage 329 , by insulating walls 353 .
- the insulating walls are for example made from silicon oxide.
- the insulating walls 353 preferably extend over the height of the wells 341 , 347 .
- the insulating walls 353 only extend in the second stage 329 and therefore not in the first stage 327 .
- the transistors 337 and 339 as well as the insulating walls 353 rest on an insulating layer 355 .
- the face of the insulating layer 355 opposite the transistors is covered by an attachment layer 357 .
- the attachment layer is preferably an insulating layer. All of the transistors of the second stage are therefore separated from the first stage by the insulating layer 355 and the attachment layer 357 .
- the attachment layers 338 and 357 are attached to one another.
- the attachment layers are for example layers of glue.
- the first and second stages 327 and 329 are for example attached to one another by the attachment layers 338 and 357 .
- the second stage also comprises an insulating layer 360 in particular covering the transistors and the insulating walls 353 .
- Conductive vias 362 reach the substrate of the first stage 327 .
- the vias 362 pass through the insulating layers 336 and 355 , the attachment layers 338 and 357 , the insulating walls 353 and, at least partially, the insulating layer 360 .
- the conductive vias 362 thus for example reach the conductive cores of the trenches 331 and the photodiode 102 .
- FIGS. 9A to 11B show steps of a manufacturing method of the embodiment of FIG. 8 .
- FIGS. 9A-9C show steps of an exemplary a method for manufacturing the embodiment of FIG. 8 .
- the first stage 327 is partially formed.
- the photodiode 102 and the isolated conductive trenches 331 are formed in a semiconductor substrate 900 , for example a silicon substrate.
- a semiconductor substrate 900 for example a silicon substrate.
- other components not shown can be formed in the first stage.
- the first stage only comprises photodiodes, for example arranged in matrix form, and isolated conductive trenches.
- the insulating layer 336 and the attachment layer 338 of the first stage 327 are formed on the substrate 900 .
- the second stage is partially formed.
- the second stage 329 comprises a semiconductor substrate.
- the substrate of the second stage is of the SOI (Semiconductor On Insulator) type, and therefore comprises an insulating layer 902 located between the layers 904 and 906 of semiconductor material.
- the layer 904 therefore covers the layer 902 , which covers the layer 906 .
- the layer 904 is for example the layer in which the transistors will be formed.
- the thickness of the layer 904 is therefore sufficient to contain the wells of the transistors.
- the insulating layer 355 and the attachment layer 357 of the second stage 329 are formed on the substrate. More specifically, the layer 355 is formed on the layer 904 and the layer 357 is formed on the layer 355 .
- the first and second stages are therefore formed separately.
- FIGS. 10A-B show other steps of an exemplary manufacturing method of the embodiment of FIG. 8 .
- the first and second stages are placed in contact. More specifically, the first and second stages are attached to one another by the attachment layers 357 and 338 . To that end, the attachment layers 357 and 338 are placed in contact.
- the substrate of the second stage is thinned.
- the layers 902 and 906 are removed, and the layer 904 is still present.
- the layer 904 is used as etching stop layer during the thinning.
- the substrate of the second stage may be a solid substrate rather than the SOI type.
- the solid substrate is then thinned until reaching a sufficient thickness to contain the wells of the transistors.
- FIGS. 11A-11B show other steps of an exemplary manufacturing method of the embodiment of FIG. 8 .
- the transistors 337 and 339 are formed in the layer 904 .
- the transistors 337 and 339 are also separated by the insulating walls 353 .
- other components not shown can be formed in the second stage.
- the formation of the transistors comprises forming doped wells 341 , 343 , 347 and 349 and forming gates 345 and 351 .
- the formation of the transistors can for example be done at low enough temperatures, for example below about 700° C., not to disrupt the operation of the photodiodes.
- the insulating layer 360 of the second stage is formed on the transistors and on the layer 904 .
- the conductive vias 362 are next formed through the insulating layers 336 and 355 , the attachment layers 338 and 357 , insulating walls 353 and, at least partially, the insulating layer 360 .
- the vias 362 are conductive vias each comprising a conductive core.
- the vias are insulated conductive vias.
- the vias comprise an insulating sheath surrounding the side partitions of the insulating cores.
- the vias 362 make it possible to electrically connect the two stages. For example, vias 362 are formed through the second stage so as to reach the upper faces of the isolated conductive trenches.
- FIG. 12 is a schematic cross-sectional view of another example of part of the pixel 375 like that of FIG. 3 or FIG. 6 .
- the pixel 375 comprises a photodiode 102 .
- the photodiode is for example formed in a P-doped region 376 of the substrate.
- the photodiode 102 is at least partially surrounded by isolated conductive trenches 331 .
- the trenches 331 comprise a conductive core 333 and an insulating sheath 335 .
- the insulating sheath covers the side partitions and the lower face of the conductive core.
- the sheath preferably covers at least part of the upper face of the conductive core.
- the conductive core 333 is for example made from polycrystalline silicon and the insulating sheath is for example made from silicon oxide.
- Transistors are located above the photodiode. This preferably involves transistors 104 , 106 , 110 , 174 , 176 or 277 . Two transistors are shown: an N channel transistor 377 and a P channel transistor 379 .
- the N channel transistor 377 is represented by N wells 381 forming the source and drain of the transistor 377 .
- the wells 381 are located in, and separated by, a P well 383 .
- the gate 385 of the transistor 377 is shown by a block located on the upper face of the wells 381 and 383 .
- the P channel transistor 379 is represented by P wells 387 forming the source and drain of the transistor 379 .
- the wells 387 are located in, and separated by, an N well 389 .
- the gate 391 of the transistor 379 is shown by a block located on the upper face of the wells 387 and 389 .
- the wells 383 and 389 of the transistors 377 and 379 are separated from the P-doped region of the substrate in which the photodiode 102 is located by an N-doped (N+) semiconductor layer 393 , for example having a dopant concentration greater than that of the wells 381 and 389 .
- Some of the transistors are separated from one another by insulating walls 395 , for example made from silicon oxide.
- the insulating walls 395 preferably extend over the entire height of the transistors.
- the insulating walls 395 for example extend from the upper face of the wells 381 or 387 to the upper face of the photodiode 102 .
- the walls 395 extend in the photodiode 102 .
- the conductive core 333 is for example biased so as to form an electromagnetic field.
- the electromagnetic field for example makes it possible to control the path of the charges generated by the photodiode 102 .
- the polarization of the trenches 331 is also suitable for the operation of one type of transistors. This polarization could disrupt the operation of the transistors of the other type.
- the polarization of the trenches 331 is suitable for the operation of the P channel transistors. It is therefore useful to separate the N channel transistors from the trenches 331 so as to ensure an optimal operation of the N channel transistors.
- Some trenches 331 a extend up to the upper face of the wells 389 .
- the trenches 331 a are not adjacent to the transistors for which the polarization of the trenches is not appropriate. More specifically, the trenches 331 a are not used to isolate the transistors for which the polarization of the trenches is not appropriate from the adjacent transistors.
- Insulating walls 400 are located on the trenches 331 b .
- the insulating walls 400 preferably extend from the trench 331 b to the upper face of the wells 381 or 387 .
- the walls 400 preferably extend over the entire height of the transistors.
- the walls 400 covering the trenches 331 b for example separate certain transistors for which the polarization of the trenches is not appropriate from adjacent transistors.
- the trenches 331 a can all be replaced by trenches 331 b .
- the trenches 331 of the pixel all extend in the region of the substrate in which the photodiode 102 is formed, but none of the trenches 331 extend over the height of the transistors.
- the photodiode and the transistors are formed in a substrate, the transistors covering the region 376 in which the photodiode is formed. This comprises forming doped regions of the photodiode, doped wells 381 , 383 , 387 and 389 and gates.
- the insulating walls 395 are formed between certain transistors.
- Cavities are formed in the locations of the trenches 331 .
- the cavities extend in the substrate from the upper face of the substrate, for example from the upper face of the wells.
- the cavities extend over at least part of the height of the substrate, including over the entire height of the transistors and preferably over the entire height of the photodiode.
- a layer of insulating material is formed on the partitions and the bottom of the cavities so as to form the insulating sheath 335 .
- the cavities are next filled with conductive material.
- the cavities are preferably filled until reaching the level of the upper face of the wells 381 , 383 , 387 and 389 .
- the conductive material is next removed in the upper parts of the cavities in which the trenches 331 b are formed.
- the conductive material is for example removed in these cavities up to the level of the upper face of the region 376 .
- FIGS. 8 and 9 make it possible to ensure that the polarization of the isolated conductive trenches, which is generally configured for structures only comprising one type of transistors (with N channel or P channel), has no negative impact on the transistors of the other type.
- FIG. 13 is a schematic diagram of an electronic device 401 , for example an image sensor.
- the electronic device 401 includes a matrix 402 of pixels that may be any of the pixels 170 , 275 , 325 , and 375 shown in FIGS. 3, 6, 8, and 12 , respectively. Each pixel corresponds to the unit of an image produced by the image sensor.
- the device 401 also includes a control circuit 404 configured to supply the control signals VR, TG, VRS, and VRS*.
- the voltage V 0 is lower than the voltage VSF.
- the drain of the transistor 176 and the source of the transistor 174 are coupled, preferably connected, to the node N 2 .
- the source of the transistor 176 and the drain of the transistor 174 are then coupled to the node N 3 .
Abstract
Description
- The present disclosure relates generally to electronic circuits, and more specifically to electronic circuits, for example pixels, comprising photodiodes and transistors.
- An image sensor is a photosensitive electronic component used to convert electromagnetic radiation (UV, visible or IR) emitted by a scene into analog electric signals. These signals are next amplified, then digitized by one or several analog-digital converters and lastly processed in order to obtain a digital image.
- The image sensor is made up of a plurality of pixels, each pixel generally comprising a photodiode and transistors. Each pixel supplies an analog signal for example corresponding to a pixel of the finished digital image.
- One embodiment addresses all or some of the drawbacks of known pixels.
- One embodiment provides a pixel comprising a photodiode and first and second transistors, the first and second transistors being coupled in series, one of the first and second transistors being a P channel transistor and the other being an N channel transistor.
- According to one embodiment, the second transistor is coupled in parallel with a third transistor of the opposite channel type from the channel type of the second transistor.
- According to one embodiment, the control signals of the second and third transistors are such that the second and third transistors are on at the same times.
- According to one embodiment, the gate of the first transistor is coupled to one of the terminals of the photodiode by a fourth transistor.
- According to one embodiment, the fourth transistor has the same channel type as the first transistor.
- According to one embodiment, the gate of the first transistor is coupled to a node for applying a reference voltage by a fifth transistor.
- According to one embodiment, the fifth transistor has the same channel type as the first transistor.
- According to one embodiment, the first transistor is coupled between a node for applying a reference voltage and a central node, and the second transistor is coupled between the central node and an output node of the pixel.
- According to one embodiment, the photodiode is at least partially surrounded by isolated conductive trenches.
- According to one embodiment, certain isolated conductive trenches extend over at least part of the height of the transistors.
- According to one embodiment, the pixel comprises a first stage comprising the photodiode and a second stage comprising the transistors, the first and second stages being attached to one another.
- One embodiment provides an electronic device comprising at least one pixel as previously described.
- Another embodiment provides a method for manufacturing a pixel as previously described, the method comprising a step for manufacturing a first stage comprising the photodiode, attaching a second stage and forming transistors in the second stage.
- According to one embodiment, the method comprises forming cavities extending over the height of the transistors and at least partially over the height of the photodiode, at least some of the cavities being partially filled with conductive material and partially filled with insulating material.
- According to one embodiment, some of the cavities are completely filled with conductive material.
- The foregoing features and advantages, as well as others, will be described in detail in the following description of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:
-
FIG. 1 shows an exemplary pixel comprising a photodiode and transistors; -
FIG. 2 shows characteristic variations of the pixel ofFIG. 1 ; -
FIG. 3 shows an embodiment of a pixel comprising a photodiode and transistors; -
FIG. 4 shows characteristic variations of the pixel ofFIG. 3 ; -
FIG. 5 shows characteristic variations of another part of the pixel ofFIG. 3 ; -
FIG. 6 shows another embodiment of a pixel comprising a photodiode and transistors; -
FIG. 7 shows characteristic variations of the pixel ofFIG. 6 ; -
FIG. 8 is a schematic cross-sectional view of an example of part of the pixel ofFIG. 3 orFIG. 6 ; -
FIGS. 9A-C show steps of an exemplary a method for manufacturing the embodiment ofFIG. 8 ; -
FIGS. 10A-B show other steps of an exemplary manufacturing method of the embodiment ofFIG. 8 ; -
FIGS. 11A-B shows other steps of an exemplary manufacturing method of the embodiment ofFIG. 8 ; -
FIG. 12 is a schematic cross-sectional view of another example of part of the pixel ofFIG. 3 orFIG. 6 ; and -
FIG. 13 is a schematic diagram of an electronic device, for example an image sensor. - Like features have been designated by like references in the various figures. In particular, the structural and/or functional features that are common among the various embodiments may have the same references and may dispose identical structural, dimensional and material properties.
- For the sake of clarity, only the operations and elements that are useful for an understanding of the embodiments described herein have been illustrated and described in detail.
- Unless indicated otherwise, when reference is made to two elements connected together, this signifies a direct connection without any intermediate elements other than conductors, and when reference is made to two elements coupled together, this signifies that these two elements can be connected or they can be coupled via one or more other elements.
- In the following disclosure, unless indicated otherwise, when reference is made to absolute positional qualifiers, such as the terms “front”, “back”, “top”, “bottom”, “left”, “right”, etc., or to relative positional qualifiers, such as the terms “above”, “below”, “higher”, “lower”, etc., or to qualifiers of orientation, such as “horizontal”, “vertical”, etc., reference is made to the orientation shown in the figures.
- Unless specified otherwise, the expressions “around”, “approximately”, “substantially” and “in the order of” signify within 10%, and preferably within 5%.
-
FIG. 1 shows an exemplary circuit comprising a photodiode. More specifically,FIG. 1 shows anexemplary pixel 100 having a 4T structure, that is to say, a pixel comprising an electronic circuit with four transistors. It may for example be a pixel of an image sensor. - The
pixel 100 comprises aphotodiode 102. Thephotodiode 102 receives radiation from a scene and transforms it into electric charges. In the illustrated example, the charges in question are holes. - The
photodiode 102 is coupled, preferably connected, by its cathode, to a node for applying a reference voltage, for example a voltage VNWELL. The anode of thephotodiode 102 is coupled to a node N1 by means of the conduction terminals (source and drain) of atransfer transistor 104. Thetransistor 104 in this example is a P channel MOS transistor. The gate of thetransistor 104 receives a control signal TG. The signal TG is for example a signal alternating between a high value, for example about 3.5 V, and a low value, for example about 0 V. - The
transfer transistor 104 makes it possible to transfer the electronic charges generated by thephotodiode 102 onto the node N1. - The node N1 is coupled to a node for applying a voltage VRST by means of a reset transistor 106 (transistor RESET). The
transistor 106 in this example is a P channel MOS transistor. The gate of thetransistor 106 receives a control signal VR. The signal VR is for example a signal able to switch between a high value, for example about 3.5 V, and a low value, for example about 0 V. Furthermore, the substrate of thetransistor 106 can be biased by the voltage VNWELL. The voltage VNWELL is for example substantially equal to 2.5 V. The voltage VRST is, in this example, approximately equal to 0.5 V. - The
reset transistor 106 makes it possible to reset the voltage VSF on the node N1 to a value V0. Thus, during the reset, the voltage VSF on the node N1 is equal to a value V0 that depends on the voltage VRST, for example greater than the voltage VRST. - The node N1 is also coupled to a node for applying a reference voltage, for example the voltage VNWELL, by means of a
capacitor 108 SN. - The
capacitor 108 for example makes it possible to store the electric charges coming from thephotodiode 102. - The node N1 is also coupled, preferably connected, to the gate of a
transistor 110 of the common drain type (Source Follower). Thetransistor 110 is coupled, preferably connected, in series with aread transistor 112, and for example acurrent source 114. The current source represents a reading row or column of a pixel matrix. More specifically, thetransistor 110 is coupled by its drain and source terminals between a node for applying a reference voltage VRT and a node N2, thetransistor 112 is coupled between the node N2 and a node N3. Thecurrent source 114 is for example coupled between the node N3 and a node for applying a reference voltage VDD. Thetransistors - The
transistor 112 receives a control voltage VRS on its gate. The signal VRS is for example a signal able to switch between a high value, for example about 3.5 V, and a low value, for example about 0 V. The substrates of thetransistors - The
transistor 110 makes it possible to obtain, at the node N2, a voltage representative of the quantity of charges located on the node N1. More specifically, the voltage on the node N2 is substantially equal to the value of the voltage VSF multiplied by the gain of thetransistor 110 plus an offset value Voffset. The value Voffset is the voltage measured at the node N2 when the voltage VSF is nil. - The
transistor 112 makes it possible to read the representative voltage on the reading row or column. More specifically, thetransistor 112 makes it possible to choose, among a matrix of pixels similar to thepixel 100, which pixel must be read. - The node N3 is thus an output node of the
pixel 100. The output signal of the pixel is a representative value of the radiation received by the photodiode. The output signal is the value on the node N3 when the pixel is read. - In this example, all of the transistors of the
pixel 100 are transistors having a same type of channel, for example P channel transistors. - Thus, during the operation of the
pixel 100, the voltage VSF on the node N1 is reset to the value V0 depending on the voltage VRST. Thetransistor 104 is turned on. The charges generated by thephotodiode 102 move toward the node N1 and cause the voltage VSF to vary from the value V0 to the reset. A voltage representative of the number of charges on the node N1 is thus obtained on the level of the node N2 and can be read by the image sensor at the output node N3, when thetransistor 112 is on. - For optimal reading, the
read transistor 112 preferably minimizes the leak to pass when thetransistor 112 is off, but thetransistor 112 preferably has a gain close to 1 when it is on, such that the voltage on the node N3 is substantially equal to the voltage on the node N2. Thetransistor 112 is strongly reversed and works in the linear zone. -
FIG. 2 shows characteristic variations of the circuit ofFIG. 1 . Thetransistor 104 is considered to be in an ideal off state, that is to say, without leaks. More specifically,FIG. 2 shows, as a function of the value (in volts) of the voltage VRST: - the voltage VRST (curve 150);
- the voltage on the node N3 (curve 152); and
- the gain between the node N3 and the node for applying the voltage VRST, that is to say, the gain of the reading chain, for example in the case where the
transistor 104 is off, preferably perfectly off (curve 154). - One can see that over a range of values of the voltage VRST, the
curve 152 is substantially parallel to thecurve 150. This value range is for example between about 0.8 V and about 1.8. Thus, for this value range, the gain is substantially constant and greater than 0.9, that is to say, close to 1. For a voltage VRST substantially equal to 0.5 V, as is for example the case in the example ofFIG. 1 , the gain is substantially equal to 0.75 V. - In order to obtain a gain close to the
value 1, the reset voltage VRST should be part of this value range, and for example greater than the value 0.8. - In order to decrease the consumption of the
pixel 100, one may wish to decrease the voltage VRST. It is therefore desirable for the range of values in which the gain is constant and high also to cover values of the lower voltage VRST, while keeping the same performance. - In other cases, one may wish to be able to function at lower values and higher values of the voltage VRST.
- In order to shift the value range toward the lower values, that is to say, to modify the value range in which the gain of the
transistor 112 is maximal, one could have decreased the value of the threshold voltage of thetransistor 112. However, this would have caused an increase in the leaks of the transistor and therefore a decrease in the performance of the pixel. -
FIG. 3 shows an embodiment of a circuit comprising a photodiode. More specifically,FIG. 3 shows apixel 170. Thepixel 170 is for example comprised in an electronic device, for example an image sensor. The electronic device for example comprises at least onepixel 170, preferably a matrix ofpixels 170. - The pixel corresponds to the unit of an image, for example in a sensor. An image sensor comprises a plurality of substantially identical pixels each comprising the same components. Thus, the elements described in
FIG. 3 are components of the described pixel and are reproduced in each pixel of an image sensor. - The
pixel 170 comprises the elements of thepixel 100 ofFIG. 1 , referenced in the same way, with the exception of thetransistor 112, which is replaced by anassembly 172. Like in the case of thepixel 100, the charges generated in thepixel 170 are holes. - In particular, the
pixel 170 comprises thephotodiode 102. Thephotodiode 102 receives, like in the example ofFIG. 1 , radiation from a scene and transforms it into electric charges. - The
photodiode 102 is coupled, preferably connected, by its cathode, to a node for applying a reference voltage, for example the voltage VNWELL. The anode of thephotodiode 102 is coupled to the node N1 by means of the conduction terminals (source and drain) of thetransfer transistor 104. Thetransistor 104 in this example is a P channel MOS transistor. The gate of thetransistor 104 receives the control signal TG previously described. - The
transfer transistor 104 makes it possible to transfer the electronic charges generated by thephotodiode 102 onto the node N1. - The node N1 is coupled to a node for applying a voltage VRST by means of the
reset transistor 106. Thetransistor 106 in this example is a P channel MOS transistor. The gate of thetransistor 106 receives a control signal VR, previously described. Additionally, the substrate of thetransistor 106 can be biased by a voltage VNWELL, previously described. - The
reset transistor 106 makes it possible to reset the voltage VSF on the node N1 to a value V0. Thus, during the reset, the voltage VSF on the node N1 is equal to a value V0 that depends on the voltage VRST, for example greater than the voltage VRST. - The node N1 is also coupled to a node for applying a reference voltage, for example the voltage VNWELL, by means of the
capacitor 108 SN. - The
capacitor 108 for example makes it possible to store the electric charges coming from thephotodiode 102. - The node N1 is also coupled, preferably connected, to the gate of the
transistor 110 of the common drain type (source follower). Thetransistor 110 is coupled, preferably connected, in series with theassembly 172, and for example acurrent source 114. The current source represents a reading row or column of a pixel matrix. More specifically, thetransistor 110 is coupled by its drain and source terminals between a node for applying a reference voltage VRT and a node N2, theassembly 172 is coupled between the node N2 and a node N3. Thecurrent source 114 is for example coupled between the node N3 and a node for applying a reference voltage VDD. In this example, thetransistor 110 is a P channel MOS transistor. The substrate of thetransistor 110 is for example biased by the voltage VNWELL. - The
transistor 110 makes it possible to obtain, at the node N2, a voltage representative of the quantity of charges located on the node N1. More specifically, the voltage on the node N2 is substantially equal to the value of the voltage VSF multiplied by the gain of thetransistor 110 plus the offset value Voffset. - The
assembly 172 makes it possible to read the representative voltage on the reading row or column. More specifically, theassembly 172 makes it possible to choose, among a matrix of pixels similar to thepixel 100, the pixel to be read. - The node N3 is thus an output node of the
pixel 100. The output signal of the pixel is a representative value of the radiation received by the photodiode. The output signal is the value on the node N3 when the pixel is read. - The
assembly 172 comprises two transistors, atransistor 174 and atransistor 176. Thetransistors FIG. 3 , the source of thetransistor 174 is connected to the drain of thetransistor 176. Likewise, the drain of thetransistor 174 is connected to the source of thetransistor 176. The drain of thetransistor 176 and the source of thetransistor 174 are coupled, preferably connected, to the node N3. The source of thetransistor 176 and the drain of thetransistor 174 are coupled, preferably connected, to the node N2. - The
transistor 174 in this example is a P channel MOS transistor. The gate of thetransistor 174 receives the control signal VRS. The substrate of thetransistor 174 is biased by the voltage VNWELL. - The
transistor 176 is an N channel MOS transistor. The gate of thetransistor 176 receives a control signal VRS*. The control signal VRS* is the signal opposite the signal VRS. When the control signal VRS is equal to a high value, the control signal VRS* is equal to a low value, and vice versa. For example, when the control signal VRS is equal to a non-nil and positive value, the control signal VRS* is nil, and when the signal VRS is nil, the signal VRS* is equal to a non-nil and positive value. The substrate of thetransistor 176 is biased by a voltage VPWELL. The voltage VPWELL is for example approximately equal to 0. - For example, all of the transistors of the
pixel 170 have the same channel type, for example P, with the exception of thetransistor 176. - Preferably, the
pixel 170 is an integrated circuit. Thetransistors photodiode 102 and thecapacitor 108, are preferably formed in the integrated circuit. - The
pixel 170 therefore comprises a so-called common drain transistor 110 (source follower) coupled, preferably connected, in series with aread transistor 176 with the opposite channel type relative to that of the so-calledcommon drain transistor 110. The read and common drain transistors are coupled between a node for applying a reference voltage (VRT) and an output node (N3). In this example, the so-calledcommon drain transistor 110 is a P-channel transistor and theread transistor 176 is an N channel transistor. Theread transistor 176 is also in parallel with aread transistor 174 with the same channel type as the so-called common drain transistor, in this example the P channel transistor. -
FIG. 4 shows characteristic variations of part of the circuit ofFIG. 3 . In particular,FIG. 4 shows characteristic variations of theassembly 172.FIG. 4 shows, as a function of time (Time (s)): -
- the voltage on the node N2 (curve 200), which corresponds to an input value and which has been deliberately made to vary linearly.
Curve 200 is therefore an increasing line, with equation y=x; - the voltage on the node N3 in the case where only the
transistor 176 is on (curve 202), thetransistor 174 then being off; - the voltage on the node N3 in the case where only the
transistor 174 is on (curve 204), thetransistor 176 then being off; - the gain of the
assembly 172 between the node N2 and the node N3 in the case where only thetransistor 176 is on (curve 206), thetransistor 174 then being off; and - the gain of the
assembly 172 between the node N2 and the node N3 in the case where only thetransistor 174 is on (curve 208), thetransistor 176 then being off.
- the voltage on the node N2 (curve 200), which corresponds to an input value and which has been deliberately made to vary linearly.
- The variations of the
curves - In this example, it is considered that the transistors are perfect transistors.
- In the case where only the
transistor 176 is on, thecurve 202 is substantially parallel, or even substantially equal, to thecurve 200 during a first period, then moves away therefrom during a second period. The first period for example corresponds, over all of the values considered inFIG. 4 , to the period preceding a moment T1, and the second period corresponds, over all of the considered values, to the period following the moment T1. In this example, the moment T1 is substantially equal to 0.82 s, which corresponds to a value V1 of the voltage on the node N2, substantially equal to 0.82 V. As a result, the gain, shown by thecurve 206, is high during the first period, then decreases during the second period. During the first period, the gain is greater than 0.8, or even greater than 0.9, and is therefore close to 1. - In the case where only the
transistor 174 is on, during the first period, thecurve 204 is distant from thecurve 200 and comes closer thereto. During the second period, thecurve 204 is substantially parallel to thecurve 200 and is close thereto. Thus, the gain, shown by thecurve 208, is small during the first part and increases until becoming, in the second part, greater than 0.8, or even 0.9, and therefore close to 1. - One can see that the
curves assembly 172 is higher by going through thetransistor 176. After the moment T1, that is to say, for values of the voltage on the node N2 greater than V1, the gain of theassembly 172 is higher by going through thetransistor 174. - During an operating step of the
pixel 170, and more particularly during the reading of thepixel 170, theassembly 172 is on, that is to say, thetransistors - The current coming from the node N2 and passing through the
assembly 172 passes through thetransistor transistor 176, and when the voltage on the node N2 is greater than V1, the current passes through thetransistor 174. - The gain of the
assembly 172 is therefore always equal to the maximum of the gains of thetransistors FIG. 4 , the gain of theassembly 172 is always greater than 0.8, mostly greater than 0.9, over the range of values of the voltage on the node N2 considered inFIG. 4 . The value range in which the gain is close to 1 is wider than the value range described in relation withFIGS. 1 and 2 , in which theassembly 172 is related by thetransistor 112. -
FIG. 5 shows characteristic variations of another part of the circuit ofFIG. 3 . In particular,FIG. 5 shows characteristic variations of thepixel 170, thetransistor 104 being considered in an ideal off state, that is to say, without leaks. -
FIG. 5 shows, as a function of the value (in volts) of the voltage VRST: -
- the voltage VRST (curve 250);
- the voltage on the node N3 (curve 252); and
- the gain between the node N3 and the node for applying the voltage VRST (curve 254).
-
FIG. 5 therefore comprises, for the embodiment ofFIG. 3 , curves showing the same elements as the curves ofFIG. 2 for the example ofFIG. 1 . - The node N3 is still considered to be the output of the system and the value of the voltage on the node for applying the voltage VRST is the input of the system.
- Like in
FIG. 2 , the curve representing the voltage on the node N3, here thecurve 252, comprises a substantially linear part, substantially parallel to thecurve 250 showing the input voltage, here the voltage VRST. This linear part corresponds to a range of values of the voltage VRST in which the gain is substantially constant at a value greater than 0.9. - The value range in question extends, in the example of
FIG. 5 , between a voltage V2 equal to about 0.25 V and a voltage V3 equal to about 1.8 V. InFIG. 2 , this value range extends approximately between 0.8 V and 1.8 V. The value range making it possible to obtain a high gain has therefore been expanded, in particular toward the low voltage values VRST. - In the embodiment of
FIG. 3 , it is thus possible to choose the reset voltage VRST in a wider value range while retaining a high gain. - One advantage of the embodiment of
FIG. 3 is that it is possible to broaden the value range while adding only one component. -
FIG. 6 shows another embodiment of a circuit comprising a photodiode. In particular,FIG. 6 shows apixel 275, comprising the elements of thepixel 170, with the exception of theassembly 172, which, in this embodiment, is replaced by asingle transistor 277. Like in the case of thepixel 170, the charges generated in thepixel 275 are holes. - The
pixel 275 is for example comprised in an electronic device, for example an image sensor. The electronic device for example comprises at least onepixel 275, preferably a matrix ofpixels 275. - The pixel corresponds to the unit of an image, for example in a sensor. An image sensor comprises a plurality of substantially identical pixels each comprising the same components. Thus, the elements described in
FIG. 6 are components of the described pixel and are reproduced in each pixel of an image sensor. - The
transistor 277 is coupled, preferably connected, between the nodes N2 and N3 by its sources and drain. Thetransistor 277 in this example is an N channel MOS transistor. The gate of thetransistor 277 receives the control signal VRS* previously defined. The substrate of thetransistor 277 is biased by the voltage VPWELL. - For example, all of the transistors of the
pixel 275 have the same channel type, for example P, with the exception of thetransistor 277. - The
pixel 275 therefore comprises a so-calledcommon drain transistor 110 coupled in series with a read transistor 227 with the opposite channel type relative to that of the so-called common drain transistor, between a node for applying a reference voltage (VRT) and an output node (N3). In this example, the so-calledcommon drain transistor 110 is a P-channel transistor and theread transistor 277 is an N channel transistor. In this embodiment, thetransistor 277 is not in parallel with a transistor with the opposite channel type (in this case, the P channel). -
FIG. 7 shows characteristic variations of the circuit ofFIG. 6 . In particular,FIG. 7 shows characteristic variations of thepixel 275, thetransistor 104 being considered in an ideal off state, that is to say, without leaks. -
FIG. 7 shows, as a function of the value (in volts) of the voltage VRST: -
- the voltage VRST (curve 300); and
- the voltage on the node N3 (curve 302).
-
FIG. 7 therefore comprises, for the embodiment ofFIG. 6 , curves showing the same elements as the curves ofFIG. 2 for the example ofFIG. 1 and, for the embodiment ofFIG. 3 , ofFIG. 5 . - One can see that over a range of values of the voltage VRST, the
curve 302 is substantially parallel to thecurve 300. This value range is for example between a voltage V4 equal to about 0.3 V and a voltage V5 equal to about 1.25 V. Thus, for this value range, the gain, not shown, is substantially constant and greater than 0.8, mostly and greater than 0.9, that is to say, close to 1. - Outside this value range, the
curve 302 moves away from thecurve 300. The gain is therefore smaller than the gain in the value range, for example less than 0.8. - The range of values in the case of the embodiment of
FIG. 6 is narrower than in the case of the embodiment ofFIG. 3 , but includes values lower than that of the value range of the example ofFIG. 1 . The embodiment ofFIG. 6 therefore makes it possible to reset the node N1 to a value below 0.8 V while keeping a gain greater than 0.8, unlike the example ofFIG. 1 . -
FIGS. 8 to 12 show embodiments of pixels. In these embodiments, the pixels are integrated circuits and comprise at least one P channel transistor and one N channel transistor. -
FIG. 8 is a schematic cross-sectional view of an example of part of thepixel 325 ofFIG. 3 orFIG. 6 . - The
pixel 325 comprises two stages: afirst stage 327 and asecond stage 329 above thefirst stage 327. - The
first stage 327 comprises aphotodiode 102. The photodiode is for example formed in a P-doped substrate. Thephotodiode 102 is at least partially surrounded by isolatedconductive trenches 331. - The
trenches 331 comprise aconductive core 333 and an insulatingsheath 335. Theconductive core 333 is for example made from polycrystalline silicon and the insulating sheath is for example made from silicon oxide. The insulating sheath covers the partitions and the lower face of the conductive core. The sheath preferably also covers at least part of the upper face. - When the
pixel 325 is operating, theconductive core 333 is for example biased so as to form an electromagnetic field. The electromagnetic field for example makes it possible to control the path of the charges generated by thephotodiode 102. The polarization of thetrenches 331 is also suitable for the operation of one type of transistors. This polarization could disrupt the operation of the transistors of the other type. In this example, the polarization of thetrenches 331 is also suitable for the operation of the P channel transistors. It is therefore useful to separate the N channel transistors from thetrenches 331 so as to ensure an optimal operation of the N channel transistors. - The substrate comprising the
photodiode 102 and thetrenches 331 is covered by an insulatinglayer 336. The insulatinglayer 336 extends at least above the photodiodes andtrenches 331. - The
layer 336 is covered by anattachment layer 338. Preferably, theattachment layer 338 is an insulating layer. - The second stage, covering the
first stage 329, comprises the transistors of thepixel 325. This for example involves thetransistors - In the example of
FIG. 8 , two MOS transistors are shown: anN channel transistor 337 and aP channel transistor 339. - Preferably, all of the transistors of the pixel are located in the second stage. There is preferably no transistor, preferably no electronic component other than the photodiodes, in the first stage.
- The
N channel transistor 337 is represented byN wells 341 forming the source and drain of thetransistor 337. Thewells 341 are separated by aP well 343. Thegate 345 of thetransistor 337 is shown by a block located on the upper face of thewells - The
P channel transistor 339 is represented byP wells 347 forming the source and drain of thetransistor 339. Thewells 347 are separated by an N well 349. Thegate 351 of thetransistor 339 is shown by a block located on the upper face of thewells - The
transistors second stage 329, by insulatingwalls 353. The insulating walls are for example made from silicon oxide. The insulatingwalls 353 preferably extend over the height of thewells walls 353 only extend in thesecond stage 329 and therefore not in thefirst stage 327. - The
transistors walls 353 rest on an insulatinglayer 355. The face of the insulatinglayer 355 opposite the transistors is covered by anattachment layer 357. The attachment layer is preferably an insulating layer. All of the transistors of the second stage are therefore separated from the first stage by the insulatinglayer 355 and theattachment layer 357. - The attachment layers 338 and 357 are attached to one another. The attachment layers are for example layers of glue. The first and
second stages - The second stage also comprises an insulating
layer 360 in particular covering the transistors and the insulatingwalls 353. -
Conductive vias 362 reach the substrate of thefirst stage 327. Thevias 362 pass through the insulatinglayers walls 353 and, at least partially, the insulatinglayer 360. Theconductive vias 362 thus for example reach the conductive cores of thetrenches 331 and thephotodiode 102. -
FIGS. 9A to 11B show steps of a manufacturing method of the embodiment ofFIG. 8 . -
FIGS. 9A-9C show steps of an exemplary a method for manufacturing the embodiment ofFIG. 8 . - During the step of
FIG. 9A , thefirst stage 327 is partially formed. Thephotodiode 102 and the isolatedconductive trenches 331 are formed in asemiconductor substrate 900, for example a silicon substrate. Optionally, other components not shown can be formed in the first stage. Preferably, the first stage only comprises photodiodes, for example arranged in matrix form, and isolated conductive trenches. - During the step of
FIG. 9B , the insulatinglayer 336 and theattachment layer 338 of thefirst stage 327 are formed on thesubstrate 900. - During the step of
FIG. 9C , the second stage is partially formed. In this step, thesecond stage 329 comprises a semiconductor substrate. In the example ofFIGS. 9A-11B , the substrate of the second stage is of the SOI (Semiconductor On Insulator) type, and therefore comprises an insulatinglayer 902 located between thelayers layer 904 therefore covers thelayer 902, which covers thelayer 906. - The
layer 904 is for example the layer in which the transistors will be formed. The thickness of thelayer 904 is therefore sufficient to contain the wells of the transistors. - Additionally, the insulating
layer 355 and theattachment layer 357 of thesecond stage 329 are formed on the substrate. More specifically, thelayer 355 is formed on thelayer 904 and thelayer 357 is formed on thelayer 355. - The first and second stages are therefore formed separately.
-
FIGS. 10A-B show other steps of an exemplary manufacturing method of the embodiment ofFIG. 8 . - During the step of
FIG. 10A , the first and second stages are placed in contact. More specifically, the first and second stages are attached to one another by the attachment layers 357 and 338. To that end, the attachment layers 357 and 338 are placed in contact. - During the step of
FIG. 10B , the substrate of the second stage is thinned. In the example ofFIGS. 9A to 11B , thelayers layer 904 is still present. Thelayer 904 is used as etching stop layer during the thinning. - As a variant, the substrate of the second stage may be a solid substrate rather than the SOI type. The solid substrate is then thinned until reaching a sufficient thickness to contain the wells of the transistors.
-
FIGS. 11A-11B show other steps of an exemplary manufacturing method of the embodiment ofFIG. 8 . - During the step of
FIG. 11A , thetransistors layer 904. Thetransistors walls 353. Optionally, other components not shown can be formed in the second stage. - In particular, the formation of the transistors comprises forming doped
wells gates - Based on the constraints regarding thermal budgets on the first stage, the formation of the transistors can for example be done at low enough temperatures, for example below about 700° C., not to disrupt the operation of the photodiodes.
- During the step of
FIG. 11B , the insulatinglayer 360 of the second stage is formed on the transistors and on thelayer 904. - The
conductive vias 362 are next formed through the insulatinglayers walls 353 and, at least partially, the insulatinglayer 360. Thevias 362 are conductive vias each comprising a conductive core. Preferably, the vias are insulated conductive vias. Preferably, the vias comprise an insulating sheath surrounding the side partitions of the insulating cores. Thevias 362 make it possible to electrically connect the two stages. For example, vias 362 are formed through the second stage so as to reach the upper faces of the isolated conductive trenches. -
FIG. 12 is a schematic cross-sectional view of another example of part of thepixel 375 like that ofFIG. 3 orFIG. 6 . - The
pixel 375 comprises aphotodiode 102. The photodiode is for example formed in a P-dopedregion 376 of the substrate. Thephotodiode 102 is at least partially surrounded by isolatedconductive trenches 331. - The
trenches 331 comprise aconductive core 333 and an insulatingsheath 335. The insulating sheath covers the side partitions and the lower face of the conductive core. The sheath preferably covers at least part of the upper face of the conductive core. Theconductive core 333 is for example made from polycrystalline silicon and the insulating sheath is for example made from silicon oxide. - Transistors are located above the photodiode. This preferably involves
transistors N channel transistor 377 and aP channel transistor 379. - The
N channel transistor 377 is represented byN wells 381 forming the source and drain of thetransistor 377. Thewells 381 are located in, and separated by, aP well 383. Thegate 385 of thetransistor 377 is shown by a block located on the upper face of thewells - The
P channel transistor 379 is represented byP wells 387 forming the source and drain of thetransistor 379. Thewells 387 are located in, and separated by, an N well 389. Thegate 391 of thetransistor 379 is shown by a block located on the upper face of thewells - The
wells transistors photodiode 102 is located by an N-doped (N+)semiconductor layer 393, for example having a dopant concentration greater than that of thewells - Some of the transistors, for example the
transistors walls 395, for example made from silicon oxide. The insulatingwalls 395 preferably extend over the entire height of the transistors. The insulatingwalls 395 for example extend from the upper face of thewells photodiode 102. Optionally, thewalls 395 extend in thephotodiode 102. - When the
pixel 375 is operating, theconductive core 333 is for example biased so as to form an electromagnetic field. The electromagnetic field for example makes it possible to control the path of the charges generated by thephotodiode 102. - The polarization of the
trenches 331 is also suitable for the operation of one type of transistors. This polarization could disrupt the operation of the transistors of the other type. In this example, the polarization of thetrenches 331 is suitable for the operation of the P channel transistors. It is therefore useful to separate the N channel transistors from thetrenches 331 so as to ensure an optimal operation of the N channel transistors. - Some
trenches 331 a extend up to the upper face of thewells 389. Thetrenches 331 a are not adjacent to the transistors for which the polarization of the trenches is not appropriate. More specifically, thetrenches 331 a are not used to isolate the transistors for which the polarization of the trenches is not appropriate from the adjacent transistors. - Certain
other trenches 331 b only extend to the upper face of thesubstrate 102. Insulatingwalls 400 are located on thetrenches 331 b. The insulatingwalls 400 preferably extend from thetrench 331 b to the upper face of thewells walls 400 preferably extend over the entire height of the transistors. - The
walls 400 covering thetrenches 331 b for example separate certain transistors for which the polarization of the trenches is not appropriate from adjacent transistors. - As a variant, the
trenches 331 a can all be replaced bytrenches 331 b. Thus, thetrenches 331 of the pixel all extend in the region of the substrate in which thephotodiode 102 is formed, but none of thetrenches 331 extend over the height of the transistors. - An exemplary manufacturing method of the embodiment of
FIG. 9 is described below. - During this method, the photodiode and the transistors are formed in a substrate, the transistors covering the
region 376 in which the photodiode is formed. This comprises forming doped regions of the photodiode, dopedwells - The insulating
walls 395 are formed between certain transistors. - Cavities are formed in the locations of the
trenches 331. The cavities extend in the substrate from the upper face of the substrate, for example from the upper face of the wells. The cavities extend over at least part of the height of the substrate, including over the entire height of the transistors and preferably over the entire height of the photodiode. - A layer of insulating material is formed on the partitions and the bottom of the cavities so as to form the insulating
sheath 335. - The cavities are next filled with conductive material. The cavities are preferably filled until reaching the level of the upper face of the
wells - The conductive material is next removed in the upper parts of the cavities in which the
trenches 331 b are formed. The conductive material is for example removed in these cavities up to the level of the upper face of theregion 376. - The structure examples of
FIGS. 8 and 9 make it possible to ensure that the polarization of the isolated conductive trenches, which is generally configured for structures only comprising one type of transistors (with N channel or P channel), has no negative impact on the transistors of the other type. -
FIG. 13 is a schematic diagram of anelectronic device 401, for example an image sensor. Theelectronic device 401 includes amatrix 402 of pixels that may be any of thepixels FIGS. 3, 6, 8, and 12 , respectively. Each pixel corresponds to the unit of an image produced by the image sensor. Thedevice 401 also includes acontrol circuit 404 configured to supply the control signals VR, TG, VRS, and VRS*. - Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these embodiments can be combined and other variants will readily occur to those skilled in the art. In particular, although all of the structures previously illustrated and described are structures configured for the case where the charges are holes, it is clear that the embodiments can adapt to the case where the electric charges are electrons. The P channel transistors are then replaced by N channel transistors and vice versa.
- In such a case, the voltage V0 is lower than the voltage VSF. Additionally, the drain of the
transistor 176 and the source of thetransistor 174 are coupled, preferably connected, to the node N2. The source of thetransistor 176 and the drain of thetransistor 174 are then coupled to the node N3. - The simulations and graphs have been done for transistors having specific characteristics (dimensions, threshold voltage, etc.); however, the behavior of the embodiments remains the same for transistors having different characteristics.
- Finally, the practical implementation of the embodiments and variants described herein is within the capabilities of those skilled in the art based on the functional description provided hereinabove.
- The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.
Claims (20)
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US11195872B2 (en) * | 2018-08-24 | 2021-12-07 | Stmicroelectronics (Crolles 2) Sas | Low-noise wide dynamic range image sensor |
US20230017723A1 (en) * | 2021-07-16 | 2023-01-19 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and manufacturing method of the same |
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KR100782463B1 (en) * | 2005-04-13 | 2007-12-05 | (주)실리콘화일 | Separation type unit pixel of image sensor having 3 dimension structure and manufacture method thereof |
US20110267505A1 (en) * | 2010-04-29 | 2011-11-03 | Bart Dierickx | Pixel with reduced 1/f noise |
US9083899B2 (en) * | 2013-02-21 | 2015-07-14 | Omnivision Technologies, Inc. | Circuit structure for providing conversion gain of a pixel array |
US9356066B2 (en) * | 2013-03-15 | 2016-05-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure for stacked device and method |
CN204966510U (en) | 2014-06-20 | 2016-01-13 | 意法半导体股份有限公司 | Broad -band gap high density semiconductor switch device |
US9602750B2 (en) * | 2014-11-25 | 2017-03-21 | Semiconductor Components Industries, Llc | Image sensor pixels having built-in variable gain feedback amplifier circuitry |
JP6863368B2 (en) * | 2016-03-28 | 2021-04-21 | ソニーグループ株式会社 | Signal processing equipment and methods, image sensors, and electronic devices |
US10225499B2 (en) * | 2016-04-11 | 2019-03-05 | Semiconductor Components Industries, Llc | Backside illuminated global shutter pixel with active reset |
KR102574973B1 (en) * | 2018-09-17 | 2023-09-06 | 에스케이하이닉스 주식회사 | Image Sensor Having a P-type Isolation Structure |
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US20230017723A1 (en) * | 2021-07-16 | 2023-01-19 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and manufacturing method of the same |
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